1/* vi: ts=8 sw=8 2 * 3 * TI 3410/5052 USB Serial Driver Header 4 * 5 * Copyright (C) 2004 Texas Instruments 6 * 7 * This driver is based on the Linux io_ti driver, which is 8 * Copyright (C) 2000-2002 Inside Out Networks 9 * Copyright (C) 2001-2002 Greg Kroah-Hartman 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or 14 * (at your option) any later version. 15 * 16 * For questions or problems with this driver, contact Texas Instruments 17 * technical support, or Al Borchers <alborchers@steinerpoint.com>, or 18 * Peter Berger <pberger@brimson.com>. 19 */ 20 21#ifndef _TI_3410_5052_H_ 22#define _TI_3410_5052_H_ 23 24/* Configuration ids */ 25#define TI_BOOT_CONFIG 1 26#define TI_ACTIVE_CONFIG 2 27 28/* Vendor and product ids */ 29#define TI_VENDOR_ID 0x0451 30#define TI_3410_PRODUCT_ID 0x3410 31#define TI_3410_EZ430_ID 0xF430 /* TI ez430 development tool */ 32#define TI_5052_BOOT_PRODUCT_ID 0x5052 /* no EEPROM, no firmware */ 33#define TI_5152_BOOT_PRODUCT_ID 0x5152 /* no EEPROM, no firmware */ 34#define TI_5052_EEPROM_PRODUCT_ID 0x505A /* EEPROM, no firmware */ 35#define TI_5052_FIRMWARE_PRODUCT_ID 0x505F /* firmware is running */ 36 37/* Commands */ 38#define TI_GET_VERSION 0x01 39#define TI_GET_PORT_STATUS 0x02 40#define TI_GET_PORT_DEV_INFO 0x03 41#define TI_GET_CONFIG 0x04 42#define TI_SET_CONFIG 0x05 43#define TI_OPEN_PORT 0x06 44#define TI_CLOSE_PORT 0x07 45#define TI_START_PORT 0x08 46#define TI_STOP_PORT 0x09 47#define TI_TEST_PORT 0x0A 48#define TI_PURGE_PORT 0x0B 49#define TI_RESET_EXT_DEVICE 0x0C 50#define TI_WRITE_DATA 0x80 51#define TI_READ_DATA 0x81 52#define TI_REQ_TYPE_CLASS 0x82 53 54/* Module identifiers */ 55#define TI_I2C_PORT 0x01 56#define TI_IEEE1284_PORT 0x02 57#define TI_UART1_PORT 0x03 58#define TI_UART2_PORT 0x04 59#define TI_RAM_PORT 0x05 60 61/* Modem status */ 62#define TI_MSR_DELTA_CTS 0x01 63#define TI_MSR_DELTA_DSR 0x02 64#define TI_MSR_DELTA_RI 0x04 65#define TI_MSR_DELTA_CD 0x08 66#define TI_MSR_CTS 0x10 67#define TI_MSR_DSR 0x20 68#define TI_MSR_RI 0x40 69#define TI_MSR_CD 0x80 70#define TI_MSR_DELTA_MASK 0x0F 71#define TI_MSR_MASK 0xF0 72 73/* Line status */ 74#define TI_LSR_OVERRUN_ERROR 0x01 75#define TI_LSR_PARITY_ERROR 0x02 76#define TI_LSR_FRAMING_ERROR 0x04 77#define TI_LSR_BREAK 0x08 78#define TI_LSR_ERROR 0x0F 79#define TI_LSR_RX_FULL 0x10 80#define TI_LSR_TX_EMPTY 0x20 81 82/* Line control */ 83#define TI_LCR_BREAK 0x40 84 85/* Modem control */ 86#define TI_MCR_LOOP 0x04 87#define TI_MCR_DTR 0x10 88#define TI_MCR_RTS 0x20 89 90/* Mask settings */ 91#define TI_UART_ENABLE_RTS_IN 0x0001 92#define TI_UART_DISABLE_RTS 0x0002 93#define TI_UART_ENABLE_PARITY_CHECKING 0x0008 94#define TI_UART_ENABLE_DSR_OUT 0x0010 95#define TI_UART_ENABLE_CTS_OUT 0x0020 96#define TI_UART_ENABLE_X_OUT 0x0040 97#define TI_UART_ENABLE_XA_OUT 0x0080 98#define TI_UART_ENABLE_X_IN 0x0100 99#define TI_UART_ENABLE_DTR_IN 0x0800 100#define TI_UART_DISABLE_DTR 0x1000 101#define TI_UART_ENABLE_MS_INTS 0x2000 102#define TI_UART_ENABLE_AUTO_START_DMA 0x4000 103 104/* Parity */ 105#define TI_UART_NO_PARITY 0x00 106#define TI_UART_ODD_PARITY 0x01 107#define TI_UART_EVEN_PARITY 0x02 108#define TI_UART_MARK_PARITY 0x03 109#define TI_UART_SPACE_PARITY 0x04 110 111/* Stop bits */ 112#define TI_UART_1_STOP_BITS 0x00 113#define TI_UART_1_5_STOP_BITS 0x01 114#define TI_UART_2_STOP_BITS 0x02 115 116/* Bits per character */ 117#define TI_UART_5_DATA_BITS 0x00 118#define TI_UART_6_DATA_BITS 0x01 119#define TI_UART_7_DATA_BITS 0x02 120#define TI_UART_8_DATA_BITS 0x03 121 122/* 232/485 modes */ 123#define TI_UART_232 0x00 124#define TI_UART_485_RECEIVER_DISABLED 0x01 125#define TI_UART_485_RECEIVER_ENABLED 0x02 126 127/* Pipe transfer mode and timeout */ 128#define TI_PIPE_MODE_CONTINOUS 0x01 129#define TI_PIPE_MODE_MASK 0x03 130#define TI_PIPE_TIMEOUT_MASK 0x7C 131#define TI_PIPE_TIMEOUT_ENABLE 0x80 132 133/* Config struct */ 134struct ti_uart_config { 135 __u16 wBaudRate; 136 __u16 wFlags; 137 __u8 bDataBits; 138 __u8 bParity; 139 __u8 bStopBits; 140 char cXon; 141 char cXoff; 142 __u8 bUartMode; 143} __attribute__((packed)); 144 145/* Get port status */ 146struct ti_port_status { 147 __u8 bCmdCode; 148 __u8 bModuleId; 149 __u8 bErrorCode; 150 __u8 bMSR; 151 __u8 bLSR; 152} __attribute__((packed)); 153 154/* Purge modes */ 155#define TI_PURGE_OUTPUT 0x00 156#define TI_PURGE_INPUT 0x80 157 158/* Read/Write data */ 159#define TI_RW_DATA_ADDR_SFR 0x10 160#define TI_RW_DATA_ADDR_IDATA 0x20 161#define TI_RW_DATA_ADDR_XDATA 0x30 162#define TI_RW_DATA_ADDR_CODE 0x40 163#define TI_RW_DATA_ADDR_GPIO 0x50 164#define TI_RW_DATA_ADDR_I2C 0x60 165#define TI_RW_DATA_ADDR_FLASH 0x70 166#define TI_RW_DATA_ADDR_DSP 0x80 167 168#define TI_RW_DATA_UNSPECIFIED 0x00 169#define TI_RW_DATA_BYTE 0x01 170#define TI_RW_DATA_WORD 0x02 171#define TI_RW_DATA_DOUBLE_WORD 0x04 172 173struct ti_write_data_bytes { 174 __u8 bAddrType; 175 __u8 bDataType; 176 __u8 bDataCounter; 177 __be16 wBaseAddrHi; 178 __be16 wBaseAddrLo; 179 __u8 bData[0]; 180} __attribute__((packed)); 181 182struct ti_read_data_request { 183 __u8 bAddrType; 184 __u8 bDataType; 185 __u8 bDataCounter; 186 __be16 wBaseAddrHi; 187 __be16 wBaseAddrLo; 188} __attribute__((packed)); 189 190struct ti_read_data_bytes { 191 __u8 bCmdCode; 192 __u8 bModuleId; 193 __u8 bErrorCode; 194 __u8 bData[0]; 195} __attribute__((packed)); 196 197/* Interrupt struct */ 198struct ti_interrupt { 199 __u8 bICode; 200 __u8 bIInfo; 201} __attribute__((packed)); 202 203/* Interrupt codes */ 204#define TI_GET_PORT_FROM_CODE(c) (((c) >> 4) - 3) 205#define TI_GET_FUNC_FROM_CODE(c) ((c) & 0x0f) 206#define TI_CODE_HARDWARE_ERROR 0xFF 207#define TI_CODE_DATA_ERROR 0x03 208#define TI_CODE_MODEM_STATUS 0x04 209 210/* Download firmware max packet size */ 211#define TI_DOWNLOAD_MAX_PACKET_SIZE 64 212 213/* Firmware image header */ 214struct ti_firmware_header { 215 __le16 wLength; 216 __u8 bCheckSum; 217} __attribute__((packed)); 218 219/* UART addresses */ 220#define TI_UART1_BASE_ADDR 0xFFA0 /* UART 1 base address */ 221#define TI_UART2_BASE_ADDR 0xFFB0 /* UART 2 base address */ 222#define TI_UART_OFFSET_LCR 0x0002 /* UART MCR register offset */ 223#define TI_UART_OFFSET_MCR 0x0004 /* UART MCR register offset */ 224 225#endif /* _TI_3410_5052_H_ */ 226