1/* 2 * OHCI HCD (Host Controller Driver) for USB. 3 * 4 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at> 5 * (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net> 6 * 7 * This file is licenced under the GPL. 8 */ 9 10#include <linux/irq.h> 11 12static void urb_free_priv (struct ohci_hcd *hc, urb_priv_t *urb_priv) 13{ 14 int last = urb_priv->length - 1; 15 16 if (last >= 0) { 17 int i; 18 struct td *td; 19 20 for (i = 0; i <= last; i++) { 21 td = urb_priv->td [i]; 22 if (td) 23 td_free (hc, td); 24 } 25 } 26 27 list_del (&urb_priv->pending); 28 kfree (urb_priv); 29} 30 31/*-------------------------------------------------------------------------*/ 32 33/* 34 * URB goes back to driver, and isn't reissued. 35 * It's completely gone from HC data structures. 36 * PRECONDITION: ohci lock held, irqs blocked. 37 */ 38static void 39finish_urb (struct ohci_hcd *ohci, struct urb *urb) 40__releases(ohci->lock) 41__acquires(ohci->lock) 42{ 43 // ASSERT (urb->hcpriv != 0); 44 45 urb_free_priv (ohci, urb->hcpriv); 46 urb->hcpriv = NULL; 47 48 spin_lock (&urb->lock); 49 if (likely (urb->status == -EINPROGRESS)) 50 urb->status = 0; 51 /* report short control reads right even though the data TD always 52 * has TD_R set. (much simpler, but creates the 1-td limit.) 53 */ 54 if (unlikely (urb->transfer_flags & URB_SHORT_NOT_OK) 55 && unlikely (usb_pipecontrol (urb->pipe)) 56 && urb->actual_length < urb->transfer_buffer_length 57 && usb_pipein (urb->pipe) 58 && urb->status == 0) { 59 urb->status = -EREMOTEIO; 60 } 61 spin_unlock (&urb->lock); 62 63 switch (usb_pipetype (urb->pipe)) { 64 case PIPE_ISOCHRONOUS: 65 ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs--; 66 break; 67 case PIPE_INTERRUPT: 68 ohci_to_hcd(ohci)->self.bandwidth_int_reqs--; 69 break; 70 } 71 72#ifdef OHCI_VERBOSE_DEBUG 73 urb_print (urb, "RET", usb_pipeout (urb->pipe)); 74#endif 75 76 /* urb->complete() can reenter this HCD */ 77 spin_unlock (&ohci->lock); 78 usb_hcd_giveback_urb (ohci_to_hcd(ohci), urb); 79 spin_lock (&ohci->lock); 80 81 /* stop periodic dma if it's not needed */ 82 if (ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs == 0 83 && ohci_to_hcd(ohci)->self.bandwidth_int_reqs == 0) { 84 ohci->hc_control &= ~(OHCI_CTRL_PLE|OHCI_CTRL_IE); 85 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control); 86 } 87} 88 89 90/*-------------------------------------------------------------------------* 91 * ED handling functions 92 *-------------------------------------------------------------------------*/ 93 94/* search for the right schedule branch to use for a periodic ed. 95 * does some load balancing; returns the branch, or negative errno. 96 */ 97static int balance (struct ohci_hcd *ohci, int interval, int load) 98{ 99 int i, branch = -ENOSPC; 100 101 /* iso periods can be huge; iso tds specify frame numbers */ 102 if (interval > NUM_INTS) 103 interval = NUM_INTS; 104 105 /* search for the least loaded schedule branch of that period 106 * that has enough bandwidth left unreserved. 107 */ 108 for (i = 0; i < interval ; i++) { 109 if (branch < 0 || ohci->load [branch] > ohci->load [i]) { 110 int j; 111 112 /* usb 1.1 says 90% of one frame */ 113 for (j = i; j < NUM_INTS; j += interval) { 114 if ((ohci->load [j] + load) > 900) 115 break; 116 } 117 if (j < NUM_INTS) 118 continue; 119 branch = i; 120 } 121 } 122 return branch; 123} 124 125/*-------------------------------------------------------------------------*/ 126 127/* both iso and interrupt requests have periods; this routine puts them 128 * into the schedule tree in the apppropriate place. most iso devices use 129 * 1msec periods, but that's not required. 130 */ 131static void periodic_link (struct ohci_hcd *ohci, struct ed *ed) 132{ 133 unsigned i; 134 135 ohci_vdbg (ohci, "link %sed %p branch %d [%dus.], interval %d\n", 136 (ed->hwINFO & cpu_to_hc32 (ohci, ED_ISO)) ? "iso " : "", 137 ed, ed->branch, ed->load, ed->interval); 138 139 for (i = ed->branch; i < NUM_INTS; i += ed->interval) { 140 struct ed **prev = &ohci->periodic [i]; 141 __hc32 *prev_p = &ohci->hcca->int_table [i]; 142 struct ed *here = *prev; 143 144 /* sorting each branch by period (slow before fast) 145 * lets us share the faster parts of the tree. 146 * (plus maybe: put interrupt eds before iso) 147 */ 148 while (here && ed != here) { 149 if (ed->interval > here->interval) 150 break; 151 prev = &here->ed_next; 152 prev_p = &here->hwNextED; 153 here = *prev; 154 } 155 if (ed != here) { 156 ed->ed_next = here; 157 if (here) 158 ed->hwNextED = *prev_p; 159 wmb (); 160 *prev = ed; 161 *prev_p = cpu_to_hc32(ohci, ed->dma); 162 wmb(); 163 } 164 ohci->load [i] += ed->load; 165 } 166 ohci_to_hcd(ohci)->self.bandwidth_allocated += ed->load / ed->interval; 167} 168 169/* link an ed into one of the HC chains */ 170 171static int ed_schedule (struct ohci_hcd *ohci, struct ed *ed) 172{ 173 int branch; 174 175 if (ohci_to_hcd(ohci)->state == HC_STATE_QUIESCING) 176 return -EAGAIN; 177 178 ed->state = ED_OPER; 179 ed->ed_prev = NULL; 180 ed->ed_next = NULL; 181 ed->hwNextED = 0; 182 wmb (); 183 184 /* we care about rm_list when setting CLE/BLE in case the HC was at 185 * work on some TD when CLE/BLE was turned off, and isn't quiesced 186 * yet. finish_unlinks() restarts as needed, some upcoming INTR_SF. 187 * 188 * control and bulk EDs are doubly linked (ed_next, ed_prev), but 189 * periodic ones are singly linked (ed_next). that's because the 190 * periodic schedule encodes a tree like figure 3-5 in the ohci 191 * spec: each qh can have several "previous" nodes, and the tree 192 * doesn't have unused/idle descriptors. 193 */ 194 switch (ed->type) { 195 case PIPE_CONTROL: 196 if (ohci->ed_controltail == NULL) { 197 WARN_ON (ohci->hc_control & OHCI_CTRL_CLE); 198 ohci_writel (ohci, ed->dma, 199 &ohci->regs->ed_controlhead); 200 } else { 201 ohci->ed_controltail->ed_next = ed; 202 ohci->ed_controltail->hwNextED = cpu_to_hc32 (ohci, 203 ed->dma); 204 } 205 ed->ed_prev = ohci->ed_controltail; 206 if (!ohci->ed_controltail && !ohci->ed_rm_list) { 207 wmb(); 208 ohci->hc_control |= OHCI_CTRL_CLE; 209 ohci_writel (ohci, 0, &ohci->regs->ed_controlcurrent); 210 ohci_writel (ohci, ohci->hc_control, 211 &ohci->regs->control); 212 } 213 ohci->ed_controltail = ed; 214 break; 215 216 case PIPE_BULK: 217 if (ohci->ed_bulktail == NULL) { 218 WARN_ON (ohci->hc_control & OHCI_CTRL_BLE); 219 ohci_writel (ohci, ed->dma, &ohci->regs->ed_bulkhead); 220 } else { 221 ohci->ed_bulktail->ed_next = ed; 222 ohci->ed_bulktail->hwNextED = cpu_to_hc32 (ohci, 223 ed->dma); 224 } 225 ed->ed_prev = ohci->ed_bulktail; 226 if (!ohci->ed_bulktail && !ohci->ed_rm_list) { 227 wmb(); 228 ohci->hc_control |= OHCI_CTRL_BLE; 229 ohci_writel (ohci, 0, &ohci->regs->ed_bulkcurrent); 230 ohci_writel (ohci, ohci->hc_control, 231 &ohci->regs->control); 232 } 233 ohci->ed_bulktail = ed; 234 break; 235 236 // case PIPE_INTERRUPT: 237 // case PIPE_ISOCHRONOUS: 238 default: 239 branch = balance (ohci, ed->interval, ed->load); 240 if (branch < 0) { 241 ohci_dbg (ohci, 242 "ERR %d, interval %d msecs, load %d\n", 243 branch, ed->interval, ed->load); 244 return branch; 245 } 246 ed->branch = branch; 247 periodic_link (ohci, ed); 248 } 249 250 /* the HC may not see the schedule updates yet, but if it does 251 * then they'll be properly ordered. 252 */ 253 return 0; 254} 255 256/*-------------------------------------------------------------------------*/ 257 258/* scan the periodic table to find and unlink this ED */ 259static void periodic_unlink (struct ohci_hcd *ohci, struct ed *ed) 260{ 261 int i; 262 263 for (i = ed->branch; i < NUM_INTS; i += ed->interval) { 264 struct ed *temp; 265 struct ed **prev = &ohci->periodic [i]; 266 __hc32 *prev_p = &ohci->hcca->int_table [i]; 267 268 while (*prev && (temp = *prev) != ed) { 269 prev_p = &temp->hwNextED; 270 prev = &temp->ed_next; 271 } 272 if (*prev) { 273 *prev_p = ed->hwNextED; 274 *prev = ed->ed_next; 275 } 276 ohci->load [i] -= ed->load; 277 } 278 ohci_to_hcd(ohci)->self.bandwidth_allocated -= ed->load / ed->interval; 279 280 ohci_vdbg (ohci, "unlink %sed %p branch %d [%dus.], interval %d\n", 281 (ed->hwINFO & cpu_to_hc32 (ohci, ED_ISO)) ? "iso " : "", 282 ed, ed->branch, ed->load, ed->interval); 283} 284 285/* unlink an ed from one of the HC chains. 286 * just the link to the ed is unlinked. 287 * the link from the ed still points to another operational ed or 0 288 * so the HC can eventually finish the processing of the unlinked ed 289 * (assuming it already started that, which needn't be true). 290 * 291 * ED_UNLINK is a transient state: the HC may still see this ED, but soon 292 * it won't. ED_SKIP means the HC will finish its current transaction, 293 * but won't start anything new. The TD queue may still grow; device 294 * drivers don't know about this HCD-internal state. 295 * 296 * When the HC can't see the ED, something changes ED_UNLINK to one of: 297 * 298 * - ED_OPER: when there's any request queued, the ED gets rescheduled 299 * immediately. HC should be working on them. 300 * 301 * - ED_IDLE: when there's no TD queue. there's no reason for the HC 302 * to care about this ED; safe to disable the endpoint. 303 * 304 * When finish_unlinks() runs later, after SOF interrupt, it will often 305 * complete one or more URB unlinks before making that state change. 306 */ 307static void ed_deschedule (struct ohci_hcd *ohci, struct ed *ed) 308{ 309 ed->hwINFO |= cpu_to_hc32 (ohci, ED_SKIP); 310 wmb (); 311 ed->state = ED_UNLINK; 312 313 /* To deschedule something from the control or bulk list, just 314 * clear CLE/BLE and wait. There's no safe way to scrub out list 315 * head/current registers until later, and "later" isn't very 316 * tightly specified. Figure 6-5 and Section 6.4.2.2 show how 317 * the HC is reading the ED queues (while we modify them). 318 * 319 * For now, ed_schedule() is "later". It might be good paranoia 320 * to scrub those registers in finish_unlinks(), in case of bugs 321 * that make the HC try to use them. 322 */ 323 switch (ed->type) { 324 case PIPE_CONTROL: 325 /* remove ED from the HC's list: */ 326 if (ed->ed_prev == NULL) { 327 if (!ed->hwNextED) { 328 ohci->hc_control &= ~OHCI_CTRL_CLE; 329 ohci_writel (ohci, ohci->hc_control, 330 &ohci->regs->control); 331 // a ohci_readl() later syncs CLE with the HC 332 } else 333 ohci_writel (ohci, 334 hc32_to_cpup (ohci, &ed->hwNextED), 335 &ohci->regs->ed_controlhead); 336 } else { 337 ed->ed_prev->ed_next = ed->ed_next; 338 ed->ed_prev->hwNextED = ed->hwNextED; 339 } 340 /* remove ED from the HCD's list: */ 341 if (ohci->ed_controltail == ed) { 342 ohci->ed_controltail = ed->ed_prev; 343 if (ohci->ed_controltail) 344 ohci->ed_controltail->ed_next = NULL; 345 } else if (ed->ed_next) { 346 ed->ed_next->ed_prev = ed->ed_prev; 347 } 348 break; 349 350 case PIPE_BULK: 351 /* remove ED from the HC's list: */ 352 if (ed->ed_prev == NULL) { 353 if (!ed->hwNextED) { 354 ohci->hc_control &= ~OHCI_CTRL_BLE; 355 ohci_writel (ohci, ohci->hc_control, 356 &ohci->regs->control); 357 // a ohci_readl() later syncs BLE with the HC 358 } else 359 ohci_writel (ohci, 360 hc32_to_cpup (ohci, &ed->hwNextED), 361 &ohci->regs->ed_bulkhead); 362 } else { 363 ed->ed_prev->ed_next = ed->ed_next; 364 ed->ed_prev->hwNextED = ed->hwNextED; 365 } 366 /* remove ED from the HCD's list: */ 367 if (ohci->ed_bulktail == ed) { 368 ohci->ed_bulktail = ed->ed_prev; 369 if (ohci->ed_bulktail) 370 ohci->ed_bulktail->ed_next = NULL; 371 } else if (ed->ed_next) { 372 ed->ed_next->ed_prev = ed->ed_prev; 373 } 374 break; 375 376 // case PIPE_INTERRUPT: 377 // case PIPE_ISOCHRONOUS: 378 default: 379 periodic_unlink (ohci, ed); 380 break; 381 } 382} 383 384 385/*-------------------------------------------------------------------------*/ 386 387/* get and maybe (re)init an endpoint. init _should_ be done only as part 388 * of enumeration, usb_set_configuration() or usb_set_interface(). 389 */ 390static struct ed *ed_get ( 391 struct ohci_hcd *ohci, 392 struct usb_host_endpoint *ep, 393 struct usb_device *udev, 394 unsigned int pipe, 395 int interval 396) { 397 struct ed *ed; 398 unsigned long flags; 399 400 spin_lock_irqsave (&ohci->lock, flags); 401 402 if (!(ed = ep->hcpriv)) { 403 struct td *td; 404 int is_out; 405 u32 info; 406 407 ed = ed_alloc (ohci, GFP_ATOMIC); 408 if (!ed) { 409 /* out of memory */ 410 goto done; 411 } 412 413 /* dummy td; end of td list for ed */ 414 td = td_alloc (ohci, GFP_ATOMIC); 415 if (!td) { 416 /* out of memory */ 417 ed_free (ohci, ed); 418 ed = NULL; 419 goto done; 420 } 421 ed->dummy = td; 422 ed->hwTailP = cpu_to_hc32 (ohci, td->td_dma); 423 ed->hwHeadP = ed->hwTailP; /* ED_C, ED_H zeroed */ 424 ed->state = ED_IDLE; 425 426 is_out = !(ep->desc.bEndpointAddress & USB_DIR_IN); 427 428 info = usb_pipedevice (pipe); 429 ed->type = usb_pipetype(pipe); 430 431 info |= (ep->desc.bEndpointAddress & ~USB_DIR_IN) << 7; 432 info |= le16_to_cpu(ep->desc.wMaxPacketSize) << 16; 433 if (udev->speed == USB_SPEED_LOW) 434 info |= ED_LOWSPEED; 435 /* only control transfers store pids in tds */ 436 if (ed->type != PIPE_CONTROL) { 437 info |= is_out ? ED_OUT : ED_IN; 438 if (ed->type != PIPE_BULK) { 439 /* periodic transfers... */ 440 if (ed->type == PIPE_ISOCHRONOUS) 441 info |= ED_ISO; 442 else if (interval > 32) /* iso can be bigger */ 443 interval = 32; 444 ed->interval = interval; 445 ed->load = usb_calc_bus_time ( 446 udev->speed, !is_out, 447 ed->type == PIPE_ISOCHRONOUS, 448 le16_to_cpu(ep->desc.wMaxPacketSize)) 449 / 1000; 450 } 451 } 452 ed->hwINFO = cpu_to_hc32(ohci, info); 453 454 ep->hcpriv = ed; 455 } 456 457done: 458 spin_unlock_irqrestore (&ohci->lock, flags); 459 return ed; 460} 461 462/*-------------------------------------------------------------------------*/ 463 464/* request unlinking of an endpoint from an operational HC. 465 * put the ep on the rm_list 466 * real work is done at the next start frame (SF) hardware interrupt 467 * caller guarantees HCD is running, so hardware access is safe, 468 * and that ed->state is ED_OPER 469 */ 470static void start_ed_unlink (struct ohci_hcd *ohci, struct ed *ed) 471{ 472 ed->hwINFO |= cpu_to_hc32 (ohci, ED_DEQUEUE); 473 ed_deschedule (ohci, ed); 474 475 /* rm_list is just singly linked, for simplicity */ 476 ed->ed_next = ohci->ed_rm_list; 477 ed->ed_prev = NULL; 478 ohci->ed_rm_list = ed; 479 480 /* enable SOF interrupt */ 481 ohci_writel (ohci, OHCI_INTR_SF, &ohci->regs->intrstatus); 482 ohci_writel (ohci, OHCI_INTR_SF, &ohci->regs->intrenable); 483 // flush those writes, and get latest HCCA contents 484 (void) ohci_readl (ohci, &ohci->regs->control); 485 486 /* SF interrupt might get delayed; record the frame counter value that 487 * indicates when the HC isn't looking at it, so concurrent unlinks 488 * behave. frame_no wraps every 2^16 msec, and changes right before 489 * SF is triggered. 490 */ 491 ed->tick = ohci_frame_no(ohci) + 1; 492 493} 494 495/*-------------------------------------------------------------------------* 496 * TD handling functions 497 *-------------------------------------------------------------------------*/ 498 499/* enqueue next TD for this URB (OHCI spec 5.2.8.2) */ 500 501static void 502td_fill (struct ohci_hcd *ohci, u32 info, 503 dma_addr_t data, int len, 504 struct urb *urb, int index) 505{ 506 struct td *td, *td_pt; 507 struct urb_priv *urb_priv = urb->hcpriv; 508 int is_iso = info & TD_ISO; 509 int hash; 510 511 // ASSERT (index < urb_priv->length); 512 513 /* aim for only one interrupt per urb. mostly applies to control 514 * and iso; other urbs rarely need more than one TD per urb. 515 * this way, only final tds (or ones with an error) cause IRQs. 516 * at least immediately; use DI=6 in case any control request is 517 * tempted to die part way through. (and to force the hc to flush 518 * its donelist soonish, even on unlink paths.) 519 * 520 * NOTE: could delay interrupts even for the last TD, and get fewer 521 * interrupts ... increasing per-urb latency by sharing interrupts. 522 * Drivers that queue bulk urbs may request that behavior. 523 */ 524 if (index != (urb_priv->length - 1) 525 || (urb->transfer_flags & URB_NO_INTERRUPT)) 526 info |= TD_DI_SET (6); 527 528 /* use this td as the next dummy */ 529 td_pt = urb_priv->td [index]; 530 531 /* fill the old dummy TD */ 532 td = urb_priv->td [index] = urb_priv->ed->dummy; 533 urb_priv->ed->dummy = td_pt; 534 535 td->ed = urb_priv->ed; 536 td->next_dl_td = NULL; 537 td->index = index; 538 td->urb = urb; 539 td->data_dma = data; 540 if (!len) 541 data = 0; 542 543 td->hwINFO = cpu_to_hc32 (ohci, info); 544 if (is_iso) { 545 td->hwCBP = cpu_to_hc32 (ohci, data & 0xFFFFF000); 546 *ohci_hwPSWp(ohci, td, 0) = cpu_to_hc16 (ohci, 547 (data & 0x0FFF) | 0xE000); 548 td->ed->last_iso = info & 0xffff; 549 } else { 550 td->hwCBP = cpu_to_hc32 (ohci, data); 551 } 552 if (data) 553 td->hwBE = cpu_to_hc32 (ohci, data + len - 1); 554 else 555 td->hwBE = 0; 556 td->hwNextTD = cpu_to_hc32 (ohci, td_pt->td_dma); 557 558 /* append to queue */ 559 list_add_tail (&td->td_list, &td->ed->td_list); 560 561 /* hash it for later reverse mapping */ 562 hash = TD_HASH_FUNC (td->td_dma); 563 td->td_hash = ohci->td_hash [hash]; 564 ohci->td_hash [hash] = td; 565 566 /* HC might read the TD (or cachelines) right away ... */ 567 wmb (); 568 td->ed->hwTailP = td->hwNextTD; 569} 570 571/*-------------------------------------------------------------------------*/ 572 573/* Prepare all TDs of a transfer, and queue them onto the ED. 574 * Caller guarantees HC is active. 575 * Usually the ED is already on the schedule, so TDs might be 576 * processed as soon as they're queued. 577 */ 578static void td_submit_urb ( 579 struct ohci_hcd *ohci, 580 struct urb *urb 581) { 582 struct urb_priv *urb_priv = urb->hcpriv; 583 dma_addr_t data; 584 int data_len = urb->transfer_buffer_length; 585 int cnt = 0; 586 u32 info = 0; 587 int is_out = usb_pipeout (urb->pipe); 588 int periodic = 0; 589 590 /* OHCI handles the bulk/interrupt data toggles itself. We just 591 * use the device toggle bits for resetting, and rely on the fact 592 * that resetting toggle is meaningless if the endpoint is active. 593 */ 594 if (!usb_gettoggle (urb->dev, usb_pipeendpoint (urb->pipe), is_out)) { 595 usb_settoggle (urb->dev, usb_pipeendpoint (urb->pipe), 596 is_out, 1); 597 urb_priv->ed->hwHeadP &= ~cpu_to_hc32 (ohci, ED_C); 598 } 599 600 urb_priv->td_cnt = 0; 601 list_add (&urb_priv->pending, &ohci->pending); 602 603 if (data_len) 604 data = urb->transfer_dma; 605 else 606 data = 0; 607 608 /* NOTE: TD_CC is set so we can tell which TDs the HC processed by 609 * using TD_CC_GET, as well as by seeing them on the done list. 610 * (CC = NotAccessed ... 0x0F, or 0x0E in PSWs for ISO.) 611 */ 612 switch (urb_priv->ed->type) { 613 614 /* Bulk and interrupt are identical except for where in the schedule 615 * their EDs live. 616 */ 617 case PIPE_INTERRUPT: 618 /* ... and periodic urbs have extra accounting */ 619 periodic = ohci_to_hcd(ohci)->self.bandwidth_int_reqs++ == 0 620 && ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs == 0; 621 /* FALLTHROUGH */ 622 case PIPE_BULK: 623 info = is_out 624 ? TD_T_TOGGLE | TD_CC | TD_DP_OUT 625 : TD_T_TOGGLE | TD_CC | TD_DP_IN; 626 /* TDs _could_ transfer up to 8K each */ 627 while (data_len > 4096) { 628 td_fill (ohci, info, data, 4096, urb, cnt); 629 data += 4096; 630 data_len -= 4096; 631 cnt++; 632 } 633 /* maybe avoid ED halt on final TD short read */ 634 if (!(urb->transfer_flags & URB_SHORT_NOT_OK)) 635 info |= TD_R; 636 td_fill (ohci, info, data, data_len, urb, cnt); 637 cnt++; 638 if ((urb->transfer_flags & URB_ZERO_PACKET) 639 && cnt < urb_priv->length) { 640 td_fill (ohci, info, 0, 0, urb, cnt); 641 cnt++; 642 } 643 /* maybe kickstart bulk list */ 644 if (urb_priv->ed->type == PIPE_BULK) { 645 wmb (); 646 ohci_writel (ohci, OHCI_BLF, &ohci->regs->cmdstatus); 647 } 648 break; 649 650 /* control manages DATA0/DATA1 toggle per-request; SETUP resets it, 651 * any DATA phase works normally, and the STATUS ack is special. 652 */ 653 case PIPE_CONTROL: 654 info = TD_CC | TD_DP_SETUP | TD_T_DATA0; 655 td_fill (ohci, info, urb->setup_dma, 8, urb, cnt++); 656 if (data_len > 0) { 657 info = TD_CC | TD_R | TD_T_DATA1; 658 info |= is_out ? TD_DP_OUT : TD_DP_IN; 659 /* NOTE: mishandles transfers >8K, some >4K */ 660 td_fill (ohci, info, data, data_len, urb, cnt++); 661 } 662 info = (is_out || data_len == 0) 663 ? TD_CC | TD_DP_IN | TD_T_DATA1 664 : TD_CC | TD_DP_OUT | TD_T_DATA1; 665 td_fill (ohci, info, data, 0, urb, cnt++); 666 /* maybe kickstart control list */ 667 wmb (); 668 ohci_writel (ohci, OHCI_CLF, &ohci->regs->cmdstatus); 669 break; 670 671 /* ISO has no retransmit, so no toggle; and it uses special TDs. 672 * Each TD could handle multiple consecutive frames (interval 1); 673 * we could often reduce the number of TDs here. 674 */ 675 case PIPE_ISOCHRONOUS: 676 for (cnt = 0; cnt < urb->number_of_packets; cnt++) { 677 int frame = urb->start_frame; 678 679 // roll-around ... exotic case (and OHCI has 680 // a 2^16 iso range, vs other HCs max of 2^10) 681 frame += cnt * urb->interval; 682 frame &= 0xffff; 683 td_fill (ohci, TD_CC | TD_ISO | frame, 684 data + urb->iso_frame_desc [cnt].offset, 685 urb->iso_frame_desc [cnt].length, urb, cnt); 686 } 687 periodic = ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs++ == 0 688 && ohci_to_hcd(ohci)->self.bandwidth_int_reqs == 0; 689 break; 690 } 691 692 /* start periodic dma if needed */ 693 if (periodic) { 694 wmb (); 695 ohci->hc_control |= OHCI_CTRL_PLE|OHCI_CTRL_IE; 696 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control); 697 } 698 699 // ASSERT (urb_priv->length == cnt); 700} 701 702/*-------------------------------------------------------------------------* 703 * Done List handling functions 704 *-------------------------------------------------------------------------*/ 705 706/* calculate transfer length/status and update the urb 707 * PRECONDITION: irqsafe (only for urb->status locking) 708 */ 709static void td_done (struct ohci_hcd *ohci, struct urb *urb, struct td *td) 710{ 711 u32 tdINFO = hc32_to_cpup (ohci, &td->hwINFO); 712 int cc = 0; 713 714 list_del (&td->td_list); 715 716 /* ISO ... drivers see per-TD length/status */ 717 if (tdINFO & TD_ISO) { 718 u16 tdPSW = ohci_hwPSW (ohci, td, 0); 719 int dlen = 0; 720 721 /* NOTE: assumes FC in tdINFO == 0, and that 722 * only the first of 0..MAXPSW psws is used. 723 */ 724 725 cc = (tdPSW >> 12) & 0xF; 726 if (tdINFO & TD_CC) /* hc didn't touch? */ 727 return; 728 729 if (usb_pipeout (urb->pipe)) 730 dlen = urb->iso_frame_desc [td->index].length; 731 else { 732 /* short reads are always OK for ISO */ 733 if (cc == TD_DATAUNDERRUN) 734 cc = TD_CC_NOERROR; 735 dlen = tdPSW & 0x3ff; 736 } 737 urb->actual_length += dlen; 738 urb->iso_frame_desc [td->index].actual_length = dlen; 739 urb->iso_frame_desc [td->index].status = cc_to_error [cc]; 740 741 if (cc != TD_CC_NOERROR) 742 ohci_vdbg (ohci, 743 "urb %p iso td %p (%d) len %d cc %d\n", 744 urb, td, 1 + td->index, dlen, cc); 745 746 /* BULK, INT, CONTROL ... drivers see aggregate length/status, 747 * except that "setup" bytes aren't counted and "short" transfers 748 * might not be reported as errors. 749 */ 750 } else { 751 int type = usb_pipetype (urb->pipe); 752 u32 tdBE = hc32_to_cpup (ohci, &td->hwBE); 753 754 cc = TD_CC_GET (tdINFO); 755 756 /* update packet status if needed (short is normally ok) */ 757 if (cc == TD_DATAUNDERRUN 758 && !(urb->transfer_flags & URB_SHORT_NOT_OK)) 759 cc = TD_CC_NOERROR; 760 if (cc != TD_CC_NOERROR && cc < 0x0E) { 761 spin_lock (&urb->lock); 762 if (urb->status == -EINPROGRESS) 763 urb->status = cc_to_error [cc]; 764 spin_unlock (&urb->lock); 765 } 766 767 /* count all non-empty packets except control SETUP packet */ 768 if ((type != PIPE_CONTROL || td->index != 0) && tdBE != 0) { 769 if (td->hwCBP == 0) 770 urb->actual_length += tdBE - td->data_dma + 1; 771 else 772 urb->actual_length += 773 hc32_to_cpup (ohci, &td->hwCBP) 774 - td->data_dma; 775 } 776 777 if (cc != TD_CC_NOERROR && cc < 0x0E) 778 ohci_vdbg (ohci, 779 "urb %p td %p (%d) cc %d, len=%d/%d\n", 780 urb, td, 1 + td->index, cc, 781 urb->actual_length, 782 urb->transfer_buffer_length); 783 } 784} 785 786/*-------------------------------------------------------------------------*/ 787 788static inline struct td * 789ed_halted (struct ohci_hcd *ohci, struct td *td, int cc, struct td *rev) 790{ 791 struct urb *urb = td->urb; 792 struct ed *ed = td->ed; 793 struct list_head *tmp = td->td_list.next; 794 __hc32 toggle = ed->hwHeadP & cpu_to_hc32 (ohci, ED_C); 795 796 /* clear ed halt; this is the td that caused it, but keep it inactive 797 * until its urb->complete() has a chance to clean up. 798 */ 799 ed->hwINFO |= cpu_to_hc32 (ohci, ED_SKIP); 800 wmb (); 801 ed->hwHeadP &= ~cpu_to_hc32 (ohci, ED_H); 802 803 /* put any later tds from this urb onto the donelist, after 'td', 804 * order won't matter here: no errors, and nothing was transferred. 805 * also patch the ed so it looks as if those tds completed normally. 806 */ 807 while (tmp != &ed->td_list) { 808 struct td *next; 809 __hc32 info; 810 811 next = list_entry (tmp, struct td, td_list); 812 tmp = next->td_list.next; 813 814 if (next->urb != urb) 815 break; 816 817 /* NOTE: if multi-td control DATA segments get supported, 818 * this urb had one of them, this td wasn't the last td 819 * in that segment (TD_R clear), this ed halted because 820 * of a short read, _and_ URB_SHORT_NOT_OK is clear ... 821 * then we need to leave the control STATUS packet queued 822 * and clear ED_SKIP. 823 */ 824 info = next->hwINFO; 825 info |= cpu_to_hc32 (ohci, TD_DONE); 826 info &= ~cpu_to_hc32 (ohci, TD_CC); 827 next->hwINFO = info; 828 829 next->next_dl_td = rev; 830 rev = next; 831 832 ed->hwHeadP = next->hwNextTD | toggle; 833 } 834 835 /* help for troubleshooting: report anything that 836 * looks odd ... that doesn't include protocol stalls 837 * (or maybe some other things) 838 */ 839 switch (cc) { 840 case TD_DATAUNDERRUN: 841 if ((urb->transfer_flags & URB_SHORT_NOT_OK) == 0) 842 break; 843 /* fallthrough */ 844 case TD_CC_STALL: 845 if (usb_pipecontrol (urb->pipe)) 846 break; 847 /* fallthrough */ 848 default: 849 ohci_dbg (ohci, 850 "urb %p path %s ep%d%s %08x cc %d --> status %d\n", 851 urb, urb->dev->devpath, 852 usb_pipeendpoint (urb->pipe), 853 usb_pipein (urb->pipe) ? "in" : "out", 854 hc32_to_cpu (ohci, td->hwINFO), 855 cc, cc_to_error [cc]); 856 } 857 858 return rev; 859} 860 861/* replies to the request have to be on a FIFO basis so 862 * we unreverse the hc-reversed done-list 863 */ 864static struct td *dl_reverse_done_list (struct ohci_hcd *ohci) 865{ 866 u32 td_dma; 867 struct td *td_rev = NULL; 868 struct td *td = NULL; 869 870 td_dma = hc32_to_cpup (ohci, &ohci->hcca->done_head); 871 ohci->hcca->done_head = 0; 872 wmb(); 873 874 /* get TD from hc's singly linked list, and 875 * prepend to ours. ed->td_list changes later. 876 */ 877 while (td_dma) { 878 int cc; 879 880 td = dma_to_td (ohci, td_dma); 881 if (!td) { 882 ohci_err (ohci, "bad entry %8x\n", td_dma); 883 break; 884 } 885 886 td->hwINFO |= cpu_to_hc32 (ohci, TD_DONE); 887 cc = TD_CC_GET (hc32_to_cpup (ohci, &td->hwINFO)); 888 889 /* Non-iso endpoints can halt on error; un-halt, 890 * and dequeue any other TDs from this urb. 891 * No other TD could have caused the halt. 892 */ 893 if (cc != TD_CC_NOERROR 894 && (td->ed->hwHeadP & cpu_to_hc32 (ohci, ED_H))) 895 td_rev = ed_halted (ohci, td, cc, td_rev); 896 897 td->next_dl_td = td_rev; 898 td_rev = td; 899 td_dma = hc32_to_cpup (ohci, &td->hwNextTD); 900 } 901 return td_rev; 902} 903 904/*-------------------------------------------------------------------------*/ 905 906/* there are some urbs/eds to unlink; called in_irq(), with HCD locked */ 907static void 908finish_unlinks (struct ohci_hcd *ohci, u16 tick) 909{ 910 struct ed *ed, **last; 911 912rescan_all: 913 for (last = &ohci->ed_rm_list, ed = *last; ed != NULL; ed = *last) { 914 struct list_head *entry, *tmp; 915 int completed, modified; 916 __hc32 *prev; 917 918 /* only take off EDs that the HC isn't using, accounting for 919 * frame counter wraps and EDs with partially retired TDs 920 */ 921 if (likely (HC_IS_RUNNING(ohci_to_hcd(ohci)->state))) { 922 if (tick_before (tick, ed->tick)) { 923skip_ed: 924 last = &ed->ed_next; 925 continue; 926 } 927 928 if (!list_empty (&ed->td_list)) { 929 struct td *td; 930 u32 head; 931 932 td = list_entry (ed->td_list.next, struct td, 933 td_list); 934 head = hc32_to_cpu (ohci, ed->hwHeadP) & 935 TD_MASK; 936 937 /* INTR_WDH may need to clean up first */ 938 if (td->td_dma != head) 939 goto skip_ed; 940 } 941 } 942 943 /* reentrancy: if we drop the schedule lock, someone might 944 * have modified this list. normally it's just prepending 945 * entries (which we'd ignore), but paranoia won't hurt. 946 */ 947 *last = ed->ed_next; 948 ed->ed_next = NULL; 949 modified = 0; 950 951 /* unlink urbs as requested, but rescan the list after 952 * we call a completion since it might have unlinked 953 * another (earlier) urb 954 * 955 * When we get here, the HC doesn't see this ed. But it 956 * must not be rescheduled until all completed URBs have 957 * been given back to the driver. 958 */ 959rescan_this: 960 completed = 0; 961 prev = &ed->hwHeadP; 962 list_for_each_safe (entry, tmp, &ed->td_list) { 963 struct td *td; 964 struct urb *urb; 965 urb_priv_t *urb_priv; 966 __hc32 savebits; 967 968 td = list_entry (entry, struct td, td_list); 969 urb = td->urb; 970 urb_priv = td->urb->hcpriv; 971 972 if (urb->status == -EINPROGRESS) { 973 prev = &td->hwNextTD; 974 continue; 975 } 976 977 /* patch pointer hc uses */ 978 savebits = *prev & ~cpu_to_hc32 (ohci, TD_MASK); 979 *prev = td->hwNextTD | savebits; 980 981 /* HC may have partly processed this TD */ 982 td_done (ohci, urb, td); 983 urb_priv->td_cnt++; 984 985 /* if URB is done, clean up */ 986 if (urb_priv->td_cnt == urb_priv->length) { 987 modified = completed = 1; 988 finish_urb (ohci, urb); 989 } 990 } 991 if (completed && !list_empty (&ed->td_list)) 992 goto rescan_this; 993 994 /* ED's now officially unlinked, hc doesn't see */ 995 ed->state = ED_IDLE; 996 ed->hwHeadP &= ~cpu_to_hc32(ohci, ED_H); 997 ed->hwNextED = 0; 998 wmb (); 999 ed->hwINFO &= ~cpu_to_hc32 (ohci, ED_SKIP | ED_DEQUEUE); 1000 1001 /* but if there's work queued, reschedule */ 1002 if (!list_empty (&ed->td_list)) { 1003 if (HC_IS_RUNNING(ohci_to_hcd(ohci)->state)) 1004 ed_schedule (ohci, ed); 1005 } 1006 1007 if (modified) 1008 goto rescan_all; 1009 } 1010 1011 /* maybe reenable control and bulk lists */ 1012 if (HC_IS_RUNNING(ohci_to_hcd(ohci)->state) 1013 && ohci_to_hcd(ohci)->state != HC_STATE_QUIESCING 1014 && !ohci->ed_rm_list) { 1015 u32 command = 0, control = 0; 1016 1017 if (ohci->ed_controltail) { 1018 command |= OHCI_CLF; 1019 if (ohci->flags & OHCI_QUIRK_ZFMICRO) 1020 mdelay(1); 1021 if (!(ohci->hc_control & OHCI_CTRL_CLE)) { 1022 control |= OHCI_CTRL_CLE; 1023 ohci_writel (ohci, 0, 1024 &ohci->regs->ed_controlcurrent); 1025 } 1026 } 1027 if (ohci->ed_bulktail) { 1028 command |= OHCI_BLF; 1029 if (ohci->flags & OHCI_QUIRK_ZFMICRO) 1030 mdelay(1); 1031 if (!(ohci->hc_control & OHCI_CTRL_BLE)) { 1032 control |= OHCI_CTRL_BLE; 1033 ohci_writel (ohci, 0, 1034 &ohci->regs->ed_bulkcurrent); 1035 } 1036 } 1037 1038 /* CLE/BLE to enable, CLF/BLF to (maybe) kickstart */ 1039 if (control) { 1040 ohci->hc_control |= control; 1041 if (ohci->flags & OHCI_QUIRK_ZFMICRO) 1042 mdelay(1); 1043 ohci_writel (ohci, ohci->hc_control, 1044 &ohci->regs->control); 1045 } 1046 if (command) { 1047 if (ohci->flags & OHCI_QUIRK_ZFMICRO) 1048 mdelay(1); 1049 ohci_writel (ohci, command, &ohci->regs->cmdstatus); 1050 } 1051 } 1052} 1053 1054 1055 1056/*-------------------------------------------------------------------------*/ 1057 1058/* 1059 * Process normal completions (error or success) and clean the schedules. 1060 * 1061 * This is the main path for handing urbs back to drivers. The only other 1062 * path is finish_unlinks(), which unlinks URBs using ed_rm_list, instead of 1063 * scanning the (re-reversed) donelist as this does. 1064 */ 1065static void 1066dl_done_list (struct ohci_hcd *ohci) 1067{ 1068 struct td *td = dl_reverse_done_list (ohci); 1069 1070 while (td) { 1071 struct td *td_next = td->next_dl_td; 1072 struct urb *urb = td->urb; 1073 urb_priv_t *urb_priv = urb->hcpriv; 1074 struct ed *ed = td->ed; 1075 1076 /* update URB's length and status from TD */ 1077 td_done (ohci, urb, td); 1078 urb_priv->td_cnt++; 1079 1080 /* If all this urb's TDs are done, call complete() */ 1081 if (urb_priv->td_cnt == urb_priv->length) 1082 finish_urb (ohci, urb); 1083 1084 /* clean schedule: unlink EDs that are no longer busy */ 1085 if (list_empty (&ed->td_list)) { 1086 if (ed->state == ED_OPER) 1087 start_ed_unlink (ohci, ed); 1088 1089 /* ... reenabling halted EDs only after fault cleanup */ 1090 } else if ((ed->hwINFO & cpu_to_hc32 (ohci, 1091 ED_SKIP | ED_DEQUEUE)) 1092 == cpu_to_hc32 (ohci, ED_SKIP)) { 1093 td = list_entry (ed->td_list.next, struct td, td_list); 1094 if (!(td->hwINFO & cpu_to_hc32 (ohci, TD_DONE))) { 1095 ed->hwINFO &= ~cpu_to_hc32 (ohci, ED_SKIP); 1096 /* ... hc may need waking-up */ 1097 switch (ed->type) { 1098 case PIPE_CONTROL: 1099 ohci_writel (ohci, OHCI_CLF, 1100 &ohci->regs->cmdstatus); 1101 break; 1102 case PIPE_BULK: 1103 ohci_writel (ohci, OHCI_BLF, 1104 &ohci->regs->cmdstatus); 1105 break; 1106 } 1107 } 1108 } 1109 1110 td = td_next; 1111 } 1112} 1113