1/* sunsab.c: ASYNC Driver for the SIEMENS SAB82532 DUSCC. 2 * 3 * Copyright (C) 1997 Eddie C. Dost (ecd@skynet.be) 4 * Copyright (C) 2002, 2006 David S. Miller (davem@davemloft.net) 5 * 6 * Rewrote buffer handling to use CIRC(Circular Buffer) macros. 7 * Maxim Krasnyanskiy <maxk@qualcomm.com> 8 * 9 * Fixed to use tty_get_baud_rate, and to allow for arbitrary baud 10 * rates to be programmed into the UART. Also eliminated a lot of 11 * duplicated code in the console setup. 12 * Theodore Ts'o <tytso@mit.edu>, 2001-Oct-12 13 * 14 * Ported to new 2.5.x UART layer. 15 * David S. Miller <davem@davemloft.net> 16 */ 17 18#include <linux/module.h> 19#include <linux/kernel.h> 20#include <linux/errno.h> 21#include <linux/tty.h> 22#include <linux/tty_flip.h> 23#include <linux/major.h> 24#include <linux/string.h> 25#include <linux/ptrace.h> 26#include <linux/ioport.h> 27#include <linux/circ_buf.h> 28#include <linux/serial.h> 29#include <linux/sysrq.h> 30#include <linux/console.h> 31#include <linux/spinlock.h> 32#include <linux/slab.h> 33#include <linux/delay.h> 34#include <linux/init.h> 35 36#include <asm/io.h> 37#include <asm/irq.h> 38#include <asm/prom.h> 39#include <asm/of_device.h> 40 41#if defined(CONFIG_SERIAL_SUNZILOG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 42#define SUPPORT_SYSRQ 43#endif 44 45#include <linux/serial_core.h> 46 47#include "suncore.h" 48#include "sunsab.h" 49 50struct uart_sunsab_port { 51 struct uart_port port; /* Generic UART port */ 52 union sab82532_async_regs __iomem *regs; /* Chip registers */ 53 unsigned long irqflags; /* IRQ state flags */ 54 int dsr; /* Current DSR state */ 55 unsigned int cec_timeout; /* Chip poll timeout... */ 56 unsigned int tec_timeout; /* likewise */ 57 unsigned char interrupt_mask0;/* ISR0 masking */ 58 unsigned char interrupt_mask1;/* ISR1 masking */ 59 unsigned char pvr_dtr_bit; /* Which PVR bit is DTR */ 60 unsigned char pvr_dsr_bit; /* Which PVR bit is DSR */ 61 int type; /* SAB82532 version */ 62 63 /* Setting configuration bits while the transmitter is active 64 * can cause garbage characters to get emitted by the chip. 65 * Therefore, we cache such writes here and do the real register 66 * write the next time the transmitter becomes idle. 67 */ 68 unsigned int cached_ebrg; 69 unsigned char cached_mode; 70 unsigned char cached_pvr; 71 unsigned char cached_dafo; 72}; 73 74/* 75 * This assumes you have a 29.4912 MHz clock for your UART. 76 */ 77#define SAB_BASE_BAUD ( 29491200 / 16 ) 78 79static char *sab82532_version[16] = { 80 "V1.0", "V2.0", "V3.2", "V(0x03)", 81 "V(0x04)", "V(0x05)", "V(0x06)", "V(0x07)", 82 "V(0x08)", "V(0x09)", "V(0x0a)", "V(0x0b)", 83 "V(0x0c)", "V(0x0d)", "V(0x0e)", "V(0x0f)" 84}; 85 86#define SAB82532_MAX_TEC_TIMEOUT 200000 /* 1 character time (at 50 baud) */ 87#define SAB82532_MAX_CEC_TIMEOUT 50000 /* 2.5 TX CLKs (at 50 baud) */ 88 89#define SAB82532_RECV_FIFO_SIZE 32 /* Standard async fifo sizes */ 90#define SAB82532_XMIT_FIFO_SIZE 32 91 92static __inline__ void sunsab_tec_wait(struct uart_sunsab_port *up) 93{ 94 int timeout = up->tec_timeout; 95 96 while ((readb(&up->regs->r.star) & SAB82532_STAR_TEC) && --timeout) 97 udelay(1); 98} 99 100static __inline__ void sunsab_cec_wait(struct uart_sunsab_port *up) 101{ 102 int timeout = up->cec_timeout; 103 104 while ((readb(&up->regs->r.star) & SAB82532_STAR_CEC) && --timeout) 105 udelay(1); 106} 107 108static struct tty_struct * 109receive_chars(struct uart_sunsab_port *up, 110 union sab82532_irq_status *stat) 111{ 112 struct tty_struct *tty = NULL; 113 unsigned char buf[32]; 114 int saw_console_brk = 0; 115 int free_fifo = 0; 116 int count = 0; 117 int i; 118 119 if (up->port.info != NULL) /* Unopened serial console */ 120 tty = up->port.info->tty; 121 122 /* Read number of BYTES (Character + Status) available. */ 123 if (stat->sreg.isr0 & SAB82532_ISR0_RPF) { 124 count = SAB82532_RECV_FIFO_SIZE; 125 free_fifo++; 126 } 127 128 if (stat->sreg.isr0 & SAB82532_ISR0_TCD) { 129 count = readb(&up->regs->r.rbcl) & (SAB82532_RECV_FIFO_SIZE - 1); 130 free_fifo++; 131 } 132 133 /* Issue a FIFO read command in case we where idle. */ 134 if (stat->sreg.isr0 & SAB82532_ISR0_TIME) { 135 sunsab_cec_wait(up); 136 writeb(SAB82532_CMDR_RFRD, &up->regs->w.cmdr); 137 return tty; 138 } 139 140 if (stat->sreg.isr0 & SAB82532_ISR0_RFO) 141 free_fifo++; 142 143 /* Read the FIFO. */ 144 for (i = 0; i < count; i++) 145 buf[i] = readb(&up->regs->r.rfifo[i]); 146 147 /* Issue Receive Message Complete command. */ 148 if (free_fifo) { 149 sunsab_cec_wait(up); 150 writeb(SAB82532_CMDR_RMC, &up->regs->w.cmdr); 151 } 152 153 /* Count may be zero for BRK, so we check for it here */ 154 if ((stat->sreg.isr1 & SAB82532_ISR1_BRK) && 155 (up->port.line == up->port.cons->index)) 156 saw_console_brk = 1; 157 158 for (i = 0; i < count; i++) { 159 unsigned char ch = buf[i], flag; 160 161 if (tty == NULL) { 162 uart_handle_sysrq_char(&up->port, ch); 163 continue; 164 } 165 166 flag = TTY_NORMAL; 167 up->port.icount.rx++; 168 169 if (unlikely(stat->sreg.isr0 & (SAB82532_ISR0_PERR | 170 SAB82532_ISR0_FERR | 171 SAB82532_ISR0_RFO)) || 172 unlikely(stat->sreg.isr1 & SAB82532_ISR1_BRK)) { 173 /* 174 * For statistics only 175 */ 176 if (stat->sreg.isr1 & SAB82532_ISR1_BRK) { 177 stat->sreg.isr0 &= ~(SAB82532_ISR0_PERR | 178 SAB82532_ISR0_FERR); 179 up->port.icount.brk++; 180 /* 181 * We do the SysRQ and SAK checking 182 * here because otherwise the break 183 * may get masked by ignore_status_mask 184 * or read_status_mask. 185 */ 186 if (uart_handle_break(&up->port)) 187 continue; 188 } else if (stat->sreg.isr0 & SAB82532_ISR0_PERR) 189 up->port.icount.parity++; 190 else if (stat->sreg.isr0 & SAB82532_ISR0_FERR) 191 up->port.icount.frame++; 192 if (stat->sreg.isr0 & SAB82532_ISR0_RFO) 193 up->port.icount.overrun++; 194 195 /* 196 * Mask off conditions which should be ingored. 197 */ 198 stat->sreg.isr0 &= (up->port.read_status_mask & 0xff); 199 stat->sreg.isr1 &= ((up->port.read_status_mask >> 8) & 0xff); 200 201 if (stat->sreg.isr1 & SAB82532_ISR1_BRK) { 202 flag = TTY_BREAK; 203 } else if (stat->sreg.isr0 & SAB82532_ISR0_PERR) 204 flag = TTY_PARITY; 205 else if (stat->sreg.isr0 & SAB82532_ISR0_FERR) 206 flag = TTY_FRAME; 207 } 208 209 if (uart_handle_sysrq_char(&up->port, ch)) 210 continue; 211 212 if ((stat->sreg.isr0 & (up->port.ignore_status_mask & 0xff)) == 0 && 213 (stat->sreg.isr1 & ((up->port.ignore_status_mask >> 8) & 0xff)) == 0) 214 tty_insert_flip_char(tty, ch, flag); 215 if (stat->sreg.isr0 & SAB82532_ISR0_RFO) 216 tty_insert_flip_char(tty, 0, TTY_OVERRUN); 217 } 218 219 if (saw_console_brk) 220 sun_do_break(); 221 222 return tty; 223} 224 225static void sunsab_stop_tx(struct uart_port *); 226static void sunsab_tx_idle(struct uart_sunsab_port *); 227 228static void transmit_chars(struct uart_sunsab_port *up, 229 union sab82532_irq_status *stat) 230{ 231 struct circ_buf *xmit = &up->port.info->xmit; 232 int i; 233 234 if (stat->sreg.isr1 & SAB82532_ISR1_ALLS) { 235 up->interrupt_mask1 |= SAB82532_IMR1_ALLS; 236 writeb(up->interrupt_mask1, &up->regs->w.imr1); 237 set_bit(SAB82532_ALLS, &up->irqflags); 238 } 239 240 241 if (!(readb(&up->regs->r.star) & SAB82532_STAR_XFW)) 242 return; 243 244 set_bit(SAB82532_XPR, &up->irqflags); 245 sunsab_tx_idle(up); 246 247 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) { 248 up->interrupt_mask1 |= SAB82532_IMR1_XPR; 249 writeb(up->interrupt_mask1, &up->regs->w.imr1); 250 return; 251 } 252 253 up->interrupt_mask1 &= ~(SAB82532_IMR1_ALLS|SAB82532_IMR1_XPR); 254 writeb(up->interrupt_mask1, &up->regs->w.imr1); 255 clear_bit(SAB82532_ALLS, &up->irqflags); 256 257 /* Stuff 32 bytes into Transmit FIFO. */ 258 clear_bit(SAB82532_XPR, &up->irqflags); 259 for (i = 0; i < up->port.fifosize; i++) { 260 writeb(xmit->buf[xmit->tail], 261 &up->regs->w.xfifo[i]); 262 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 263 up->port.icount.tx++; 264 if (uart_circ_empty(xmit)) 265 break; 266 } 267 268 /* Issue a Transmit Frame command. */ 269 sunsab_cec_wait(up); 270 writeb(SAB82532_CMDR_XF, &up->regs->w.cmdr); 271 272 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 273 uart_write_wakeup(&up->port); 274 275 if (uart_circ_empty(xmit)) 276 sunsab_stop_tx(&up->port); 277} 278 279static void check_status(struct uart_sunsab_port *up, 280 union sab82532_irq_status *stat) 281{ 282 if (stat->sreg.isr0 & SAB82532_ISR0_CDSC) 283 uart_handle_dcd_change(&up->port, 284 !(readb(&up->regs->r.vstr) & SAB82532_VSTR_CD)); 285 286 if (stat->sreg.isr1 & SAB82532_ISR1_CSC) 287 uart_handle_cts_change(&up->port, 288 (readb(&up->regs->r.star) & SAB82532_STAR_CTS)); 289 290 if ((readb(&up->regs->r.pvr) & up->pvr_dsr_bit) ^ up->dsr) { 291 up->dsr = (readb(&up->regs->r.pvr) & up->pvr_dsr_bit) ? 0 : 1; 292 up->port.icount.dsr++; 293 } 294 295 wake_up_interruptible(&up->port.info->delta_msr_wait); 296} 297 298static irqreturn_t sunsab_interrupt(int irq, void *dev_id) 299{ 300 struct uart_sunsab_port *up = dev_id; 301 struct tty_struct *tty; 302 union sab82532_irq_status status; 303 unsigned long flags; 304 305 spin_lock_irqsave(&up->port.lock, flags); 306 307 status.stat = 0; 308 if (readb(&up->regs->r.gis) & SAB82532_GIS_ISA0) 309 status.sreg.isr0 = readb(&up->regs->r.isr0); 310 if (readb(&up->regs->r.gis) & SAB82532_GIS_ISA1) 311 status.sreg.isr1 = readb(&up->regs->r.isr1); 312 313 tty = NULL; 314 if (status.stat) { 315 if ((status.sreg.isr0 & (SAB82532_ISR0_TCD | SAB82532_ISR0_TIME | 316 SAB82532_ISR0_RFO | SAB82532_ISR0_RPF)) || 317 (status.sreg.isr1 & SAB82532_ISR1_BRK)) 318 tty = receive_chars(up, &status); 319 if ((status.sreg.isr0 & SAB82532_ISR0_CDSC) || 320 (status.sreg.isr1 & SAB82532_ISR1_CSC)) 321 check_status(up, &status); 322 if (status.sreg.isr1 & (SAB82532_ISR1_ALLS | SAB82532_ISR1_XPR)) 323 transmit_chars(up, &status); 324 } 325 326 spin_unlock(&up->port.lock); 327 328 if (tty) 329 tty_flip_buffer_push(tty); 330 331 up++; 332 333 spin_lock(&up->port.lock); 334 335 status.stat = 0; 336 if (readb(&up->regs->r.gis) & SAB82532_GIS_ISB0) 337 status.sreg.isr0 = readb(&up->regs->r.isr0); 338 if (readb(&up->regs->r.gis) & SAB82532_GIS_ISB1) 339 status.sreg.isr1 = readb(&up->regs->r.isr1); 340 341 tty = NULL; 342 if (status.stat) { 343 if ((status.sreg.isr0 & (SAB82532_ISR0_TCD | SAB82532_ISR0_TIME | 344 SAB82532_ISR0_RFO | SAB82532_ISR0_RPF)) || 345 (status.sreg.isr1 & SAB82532_ISR1_BRK)) 346 347 tty = receive_chars(up, &status); 348 if ((status.sreg.isr0 & SAB82532_ISR0_CDSC) || 349 (status.sreg.isr1 & (SAB82532_ISR1_BRK | SAB82532_ISR1_CSC))) 350 check_status(up, &status); 351 if (status.sreg.isr1 & (SAB82532_ISR1_ALLS | SAB82532_ISR1_XPR)) 352 transmit_chars(up, &status); 353 } 354 355 spin_unlock_irqrestore(&up->port.lock, flags); 356 357 if (tty) 358 tty_flip_buffer_push(tty); 359 360 return IRQ_HANDLED; 361} 362 363/* port->lock is not held. */ 364static unsigned int sunsab_tx_empty(struct uart_port *port) 365{ 366 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port; 367 int ret; 368 369 /* Do not need a lock for a state test like this. */ 370 if (test_bit(SAB82532_ALLS, &up->irqflags)) 371 ret = TIOCSER_TEMT; 372 else 373 ret = 0; 374 375 return ret; 376} 377 378/* port->lock held by caller. */ 379static void sunsab_set_mctrl(struct uart_port *port, unsigned int mctrl) 380{ 381 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port; 382 383 if (mctrl & TIOCM_RTS) { 384 up->cached_mode &= ~SAB82532_MODE_FRTS; 385 up->cached_mode |= SAB82532_MODE_RTS; 386 } else { 387 up->cached_mode |= (SAB82532_MODE_FRTS | 388 SAB82532_MODE_RTS); 389 } 390 if (mctrl & TIOCM_DTR) { 391 up->cached_pvr &= ~(up->pvr_dtr_bit); 392 } else { 393 up->cached_pvr |= up->pvr_dtr_bit; 394 } 395 396 set_bit(SAB82532_REGS_PENDING, &up->irqflags); 397 if (test_bit(SAB82532_XPR, &up->irqflags)) 398 sunsab_tx_idle(up); 399} 400 401/* port->lock is held by caller and interrupts are disabled. */ 402static unsigned int sunsab_get_mctrl(struct uart_port *port) 403{ 404 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port; 405 unsigned char val; 406 unsigned int result; 407 408 result = 0; 409 410 val = readb(&up->regs->r.pvr); 411 result |= (val & up->pvr_dsr_bit) ? 0 : TIOCM_DSR; 412 413 val = readb(&up->regs->r.vstr); 414 result |= (val & SAB82532_VSTR_CD) ? 0 : TIOCM_CAR; 415 416 val = readb(&up->regs->r.star); 417 result |= (val & SAB82532_STAR_CTS) ? TIOCM_CTS : 0; 418 419 return result; 420} 421 422/* port->lock held by caller. */ 423static void sunsab_stop_tx(struct uart_port *port) 424{ 425 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port; 426 427 up->interrupt_mask1 |= SAB82532_IMR1_XPR; 428 writeb(up->interrupt_mask1, &up->regs->w.imr1); 429} 430 431/* port->lock held by caller. */ 432static void sunsab_tx_idle(struct uart_sunsab_port *up) 433{ 434 if (test_bit(SAB82532_REGS_PENDING, &up->irqflags)) { 435 u8 tmp; 436 437 clear_bit(SAB82532_REGS_PENDING, &up->irqflags); 438 writeb(up->cached_mode, &up->regs->rw.mode); 439 writeb(up->cached_pvr, &up->regs->rw.pvr); 440 writeb(up->cached_dafo, &up->regs->w.dafo); 441 442 writeb(up->cached_ebrg & 0xff, &up->regs->w.bgr); 443 tmp = readb(&up->regs->rw.ccr2); 444 tmp &= ~0xc0; 445 tmp |= (up->cached_ebrg >> 2) & 0xc0; 446 writeb(tmp, &up->regs->rw.ccr2); 447 } 448} 449 450/* port->lock held by caller. */ 451static void sunsab_start_tx(struct uart_port *port) 452{ 453 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port; 454 struct circ_buf *xmit = &up->port.info->xmit; 455 int i; 456 457 up->interrupt_mask1 &= ~(SAB82532_IMR1_ALLS|SAB82532_IMR1_XPR); 458 writeb(up->interrupt_mask1, &up->regs->w.imr1); 459 460 if (!test_bit(SAB82532_XPR, &up->irqflags)) 461 return; 462 463 clear_bit(SAB82532_ALLS, &up->irqflags); 464 clear_bit(SAB82532_XPR, &up->irqflags); 465 466 for (i = 0; i < up->port.fifosize; i++) { 467 writeb(xmit->buf[xmit->tail], 468 &up->regs->w.xfifo[i]); 469 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 470 up->port.icount.tx++; 471 if (uart_circ_empty(xmit)) 472 break; 473 } 474 475 /* Issue a Transmit Frame command. */ 476 sunsab_cec_wait(up); 477 writeb(SAB82532_CMDR_XF, &up->regs->w.cmdr); 478} 479 480/* port->lock is not held. */ 481static void sunsab_send_xchar(struct uart_port *port, char ch) 482{ 483 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port; 484 unsigned long flags; 485 486 spin_lock_irqsave(&up->port.lock, flags); 487 488 sunsab_tec_wait(up); 489 writeb(ch, &up->regs->w.tic); 490 491 spin_unlock_irqrestore(&up->port.lock, flags); 492} 493 494/* port->lock held by caller. */ 495static void sunsab_stop_rx(struct uart_port *port) 496{ 497 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port; 498 499 up->interrupt_mask0 |= SAB82532_ISR0_TCD; 500 writeb(up->interrupt_mask1, &up->regs->w.imr0); 501} 502 503/* port->lock held by caller. */ 504static void sunsab_enable_ms(struct uart_port *port) 505{ 506 /* For now we always receive these interrupts. */ 507} 508 509/* port->lock is not held. */ 510static void sunsab_break_ctl(struct uart_port *port, int break_state) 511{ 512 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port; 513 unsigned long flags; 514 unsigned char val; 515 516 spin_lock_irqsave(&up->port.lock, flags); 517 518 val = up->cached_dafo; 519 if (break_state) 520 val |= SAB82532_DAFO_XBRK; 521 else 522 val &= ~SAB82532_DAFO_XBRK; 523 up->cached_dafo = val; 524 525 set_bit(SAB82532_REGS_PENDING, &up->irqflags); 526 if (test_bit(SAB82532_XPR, &up->irqflags)) 527 sunsab_tx_idle(up); 528 529 spin_unlock_irqrestore(&up->port.lock, flags); 530} 531 532/* port->lock is not held. */ 533static int sunsab_startup(struct uart_port *port) 534{ 535 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port; 536 unsigned long flags; 537 unsigned char tmp; 538 539 spin_lock_irqsave(&up->port.lock, flags); 540 541 /* 542 * Wait for any commands or immediate characters 543 */ 544 sunsab_cec_wait(up); 545 sunsab_tec_wait(up); 546 547 /* 548 * Clear the FIFO buffers. 549 */ 550 writeb(SAB82532_CMDR_RRES, &up->regs->w.cmdr); 551 sunsab_cec_wait(up); 552 writeb(SAB82532_CMDR_XRES, &up->regs->w.cmdr); 553 554 /* 555 * Clear the interrupt registers. 556 */ 557 (void) readb(&up->regs->r.isr0); 558 (void) readb(&up->regs->r.isr1); 559 560 /* 561 * Now, initialize the UART 562 */ 563 writeb(0, &up->regs->w.ccr0); /* power-down */ 564 writeb(SAB82532_CCR0_MCE | SAB82532_CCR0_SC_NRZ | 565 SAB82532_CCR0_SM_ASYNC, &up->regs->w.ccr0); 566 writeb(SAB82532_CCR1_ODS | SAB82532_CCR1_BCR | 7, &up->regs->w.ccr1); 567 writeb(SAB82532_CCR2_BDF | SAB82532_CCR2_SSEL | 568 SAB82532_CCR2_TOE, &up->regs->w.ccr2); 569 writeb(0, &up->regs->w.ccr3); 570 writeb(SAB82532_CCR4_MCK4 | SAB82532_CCR4_EBRG, &up->regs->w.ccr4); 571 up->cached_mode = (SAB82532_MODE_RTS | SAB82532_MODE_FCTS | 572 SAB82532_MODE_RAC); 573 writeb(up->cached_mode, &up->regs->w.mode); 574 writeb(SAB82532_RFC_DPS|SAB82532_RFC_RFTH_32, &up->regs->w.rfc); 575 576 tmp = readb(&up->regs->rw.ccr0); 577 tmp |= SAB82532_CCR0_PU; /* power-up */ 578 writeb(tmp, &up->regs->rw.ccr0); 579 580 /* 581 * Finally, enable interrupts 582 */ 583 up->interrupt_mask0 = (SAB82532_IMR0_PERR | SAB82532_IMR0_FERR | 584 SAB82532_IMR0_PLLA); 585 writeb(up->interrupt_mask0, &up->regs->w.imr0); 586 up->interrupt_mask1 = (SAB82532_IMR1_BRKT | SAB82532_IMR1_ALLS | 587 SAB82532_IMR1_XOFF | SAB82532_IMR1_TIN | 588 SAB82532_IMR1_CSC | SAB82532_IMR1_XON | 589 SAB82532_IMR1_XPR); 590 writeb(up->interrupt_mask1, &up->regs->w.imr1); 591 set_bit(SAB82532_ALLS, &up->irqflags); 592 set_bit(SAB82532_XPR, &up->irqflags); 593 594 spin_unlock_irqrestore(&up->port.lock, flags); 595 596 return 0; 597} 598 599/* port->lock is not held. */ 600static void sunsab_shutdown(struct uart_port *port) 601{ 602 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port; 603 unsigned long flags; 604 605 spin_lock_irqsave(&up->port.lock, flags); 606 607 /* Disable Interrupts */ 608 up->interrupt_mask0 = 0xff; 609 writeb(up->interrupt_mask0, &up->regs->w.imr0); 610 up->interrupt_mask1 = 0xff; 611 writeb(up->interrupt_mask1, &up->regs->w.imr1); 612 613 /* Disable break condition */ 614 up->cached_dafo = readb(&up->regs->rw.dafo); 615 up->cached_dafo &= ~SAB82532_DAFO_XBRK; 616 writeb(up->cached_dafo, &up->regs->rw.dafo); 617 618 /* Disable Receiver */ 619 up->cached_mode &= ~SAB82532_MODE_RAC; 620 writeb(up->cached_mode, &up->regs->rw.mode); 621 622 623 spin_unlock_irqrestore(&up->port.lock, flags); 624} 625 626/* 627 * This is used to figure out the divisor speeds. 628 * 629 * The formula is: Baud = SAB_BASE_BAUD / ((N + 1) * (1 << M)), 630 * 631 * with 0 <= N < 64 and 0 <= M < 16 632 */ 633 634static void calc_ebrg(int baud, int *n_ret, int *m_ret) 635{ 636 int n, m; 637 638 if (baud == 0) { 639 *n_ret = 0; 640 *m_ret = 0; 641 return; 642 } 643 644 /* 645 * We scale numbers by 10 so that we get better accuracy 646 * without having to use floating point. Here we increment m 647 * until n is within the valid range. 648 */ 649 n = (SAB_BASE_BAUD * 10) / baud; 650 m = 0; 651 while (n >= 640) { 652 n = n / 2; 653 m++; 654 } 655 n = (n+5) / 10; 656 /* 657 * We try very hard to avoid speeds with M == 0 since they may 658 * not work correctly for XTAL frequences above 10 MHz. 659 */ 660 if ((m == 0) && ((n & 1) == 0)) { 661 n = n / 2; 662 m++; 663 } 664 *n_ret = n - 1; 665 *m_ret = m; 666} 667 668/* Internal routine, port->lock is held and local interrupts are disabled. */ 669static void sunsab_convert_to_sab(struct uart_sunsab_port *up, unsigned int cflag, 670 unsigned int iflag, unsigned int baud, 671 unsigned int quot) 672{ 673 unsigned char dafo; 674 int bits, n, m; 675 676 /* Byte size and parity */ 677 switch (cflag & CSIZE) { 678 case CS5: dafo = SAB82532_DAFO_CHL5; bits = 7; break; 679 case CS6: dafo = SAB82532_DAFO_CHL6; bits = 8; break; 680 case CS7: dafo = SAB82532_DAFO_CHL7; bits = 9; break; 681 case CS8: dafo = SAB82532_DAFO_CHL8; bits = 10; break; 682 /* Never happens, but GCC is too dumb to figure it out */ 683 default: dafo = SAB82532_DAFO_CHL5; bits = 7; break; 684 } 685 686 if (cflag & CSTOPB) { 687 dafo |= SAB82532_DAFO_STOP; 688 bits++; 689 } 690 691 if (cflag & PARENB) { 692 dafo |= SAB82532_DAFO_PARE; 693 bits++; 694 } 695 696 if (cflag & PARODD) { 697 dafo |= SAB82532_DAFO_PAR_ODD; 698 } else { 699 dafo |= SAB82532_DAFO_PAR_EVEN; 700 } 701 up->cached_dafo = dafo; 702 703 calc_ebrg(baud, &n, &m); 704 705 up->cached_ebrg = n | (m << 6); 706 707 up->tec_timeout = (10 * 1000000) / baud; 708 up->cec_timeout = up->tec_timeout >> 2; 709 710 /* CTS flow control flags */ 711 /* We encode read_status_mask and ignore_status_mask like so: 712 * 713 * --------------------- 714 * | ... | ISR1 | ISR0 | 715 * --------------------- 716 * .. 15 8 7 0 717 */ 718 719 up->port.read_status_mask = (SAB82532_ISR0_TCD | SAB82532_ISR0_TIME | 720 SAB82532_ISR0_RFO | SAB82532_ISR0_RPF | 721 SAB82532_ISR0_CDSC); 722 up->port.read_status_mask |= (SAB82532_ISR1_CSC | 723 SAB82532_ISR1_ALLS | 724 SAB82532_ISR1_XPR) << 8; 725 if (iflag & INPCK) 726 up->port.read_status_mask |= (SAB82532_ISR0_PERR | 727 SAB82532_ISR0_FERR); 728 if (iflag & (BRKINT | PARMRK)) 729 up->port.read_status_mask |= (SAB82532_ISR1_BRK << 8); 730 731 /* 732 * Characteres to ignore 733 */ 734 up->port.ignore_status_mask = 0; 735 if (iflag & IGNPAR) 736 up->port.ignore_status_mask |= (SAB82532_ISR0_PERR | 737 SAB82532_ISR0_FERR); 738 if (iflag & IGNBRK) { 739 up->port.ignore_status_mask |= (SAB82532_ISR1_BRK << 8); 740 /* 741 * If we're ignoring parity and break indicators, 742 * ignore overruns too (for real raw support). 743 */ 744 if (iflag & IGNPAR) 745 up->port.ignore_status_mask |= SAB82532_ISR0_RFO; 746 } 747 748 /* 749 * ignore all characters if CREAD is not set 750 */ 751 if ((cflag & CREAD) == 0) 752 up->port.ignore_status_mask |= (SAB82532_ISR0_RPF | 753 SAB82532_ISR0_TCD); 754 755 uart_update_timeout(&up->port, cflag, 756 (up->port.uartclk / (16 * quot))); 757 758 /* Now schedule a register update when the chip's 759 * transmitter is idle. 760 */ 761 up->cached_mode |= SAB82532_MODE_RAC; 762 set_bit(SAB82532_REGS_PENDING, &up->irqflags); 763 if (test_bit(SAB82532_XPR, &up->irqflags)) 764 sunsab_tx_idle(up); 765} 766 767/* port->lock is not held. */ 768static void sunsab_set_termios(struct uart_port *port, struct ktermios *termios, 769 struct ktermios *old) 770{ 771 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port; 772 unsigned long flags; 773 unsigned int baud = uart_get_baud_rate(port, termios, old, 0, 4000000); 774 unsigned int quot = uart_get_divisor(port, baud); 775 776 spin_lock_irqsave(&up->port.lock, flags); 777 sunsab_convert_to_sab(up, termios->c_cflag, termios->c_iflag, baud, quot); 778 spin_unlock_irqrestore(&up->port.lock, flags); 779} 780 781static const char *sunsab_type(struct uart_port *port) 782{ 783 struct uart_sunsab_port *up = (void *)port; 784 static char buf[36]; 785 786 sprintf(buf, "SAB82532 %s", sab82532_version[up->type]); 787 return buf; 788} 789 790static void sunsab_release_port(struct uart_port *port) 791{ 792} 793 794static int sunsab_request_port(struct uart_port *port) 795{ 796 return 0; 797} 798 799static void sunsab_config_port(struct uart_port *port, int flags) 800{ 801} 802 803static int sunsab_verify_port(struct uart_port *port, struct serial_struct *ser) 804{ 805 return -EINVAL; 806} 807 808static struct uart_ops sunsab_pops = { 809 .tx_empty = sunsab_tx_empty, 810 .set_mctrl = sunsab_set_mctrl, 811 .get_mctrl = sunsab_get_mctrl, 812 .stop_tx = sunsab_stop_tx, 813 .start_tx = sunsab_start_tx, 814 .send_xchar = sunsab_send_xchar, 815 .stop_rx = sunsab_stop_rx, 816 .enable_ms = sunsab_enable_ms, 817 .break_ctl = sunsab_break_ctl, 818 .startup = sunsab_startup, 819 .shutdown = sunsab_shutdown, 820 .set_termios = sunsab_set_termios, 821 .type = sunsab_type, 822 .release_port = sunsab_release_port, 823 .request_port = sunsab_request_port, 824 .config_port = sunsab_config_port, 825 .verify_port = sunsab_verify_port, 826}; 827 828static struct uart_driver sunsab_reg = { 829 .owner = THIS_MODULE, 830 .driver_name = "serial", 831 .dev_name = "ttyS", 832 .major = TTY_MAJOR, 833}; 834 835static struct uart_sunsab_port *sunsab_ports; 836static int num_channels; 837 838#ifdef CONFIG_SERIAL_SUNSAB_CONSOLE 839 840static void sunsab_console_putchar(struct uart_port *port, int c) 841{ 842 struct uart_sunsab_port *up = (struct uart_sunsab_port *)port; 843 unsigned long flags; 844 845 spin_lock_irqsave(&up->port.lock, flags); 846 847 sunsab_tec_wait(up); 848 writeb(c, &up->regs->w.tic); 849 850 spin_unlock_irqrestore(&up->port.lock, flags); 851} 852 853static void sunsab_console_write(struct console *con, const char *s, unsigned n) 854{ 855 struct uart_sunsab_port *up = &sunsab_ports[con->index]; 856 857 uart_console_write(&up->port, s, n, sunsab_console_putchar); 858 sunsab_tec_wait(up); 859} 860 861static int sunsab_console_setup(struct console *con, char *options) 862{ 863 struct uart_sunsab_port *up = &sunsab_ports[con->index]; 864 unsigned long flags; 865 unsigned int baud, quot; 866 867 /* 868 * The console framework calls us for each and every port 869 * registered. Defer the console setup until the requested 870 * port has been properly discovered. A bit of a hack, 871 * though... 872 */ 873 if (up->port.type != PORT_SUNSAB) 874 return -1; 875 876 printk("Console: ttyS%d (SAB82532)\n", 877 (sunsab_reg.minor - 64) + con->index); 878 879 sunserial_console_termios(con); 880 881 switch (con->cflag & CBAUD) { 882 case B150: baud = 150; break; 883 case B300: baud = 300; break; 884 case B600: baud = 600; break; 885 case B1200: baud = 1200; break; 886 case B2400: baud = 2400; break; 887 case B4800: baud = 4800; break; 888 default: case B9600: baud = 9600; break; 889 case B19200: baud = 19200; break; 890 case B38400: baud = 38400; break; 891 case B57600: baud = 57600; break; 892 case B115200: baud = 115200; break; 893 case B230400: baud = 230400; break; 894 case B460800: baud = 460800; break; 895 }; 896 897 /* 898 * Temporary fix. 899 */ 900 spin_lock_init(&up->port.lock); 901 902 /* 903 * Initialize the hardware 904 */ 905 sunsab_startup(&up->port); 906 907 spin_lock_irqsave(&up->port.lock, flags); 908 909 /* 910 * Finally, enable interrupts 911 */ 912 up->interrupt_mask0 = SAB82532_IMR0_PERR | SAB82532_IMR0_FERR | 913 SAB82532_IMR0_PLLA | SAB82532_IMR0_CDSC; 914 writeb(up->interrupt_mask0, &up->regs->w.imr0); 915 up->interrupt_mask1 = SAB82532_IMR1_BRKT | SAB82532_IMR1_ALLS | 916 SAB82532_IMR1_XOFF | SAB82532_IMR1_TIN | 917 SAB82532_IMR1_CSC | SAB82532_IMR1_XON | 918 SAB82532_IMR1_XPR; 919 writeb(up->interrupt_mask1, &up->regs->w.imr1); 920 921 quot = uart_get_divisor(&up->port, baud); 922 sunsab_convert_to_sab(up, con->cflag, 0, baud, quot); 923 sunsab_set_mctrl(&up->port, TIOCM_DTR | TIOCM_RTS); 924 925 spin_unlock_irqrestore(&up->port.lock, flags); 926 927 return 0; 928} 929 930static struct console sunsab_console = { 931 .name = "ttyS", 932 .write = sunsab_console_write, 933 .device = uart_console_device, 934 .setup = sunsab_console_setup, 935 .flags = CON_PRINTBUFFER, 936 .index = -1, 937 .data = &sunsab_reg, 938}; 939 940static inline struct console *SUNSAB_CONSOLE(void) 941{ 942 int i; 943 944 if (con_is_present()) 945 return NULL; 946 947 for (i = 0; i < num_channels; i++) { 948 int this_minor = sunsab_reg.minor + i; 949 950 if ((this_minor - 64) == (serial_console - 1)) 951 break; 952 } 953 if (i == num_channels) 954 return NULL; 955 956 sunsab_console.index = i; 957 958 return &sunsab_console; 959} 960#else 961#define SUNSAB_CONSOLE() (NULL) 962#define sunsab_console_init() do { } while (0) 963#endif 964 965static int __devinit sunsab_init_one(struct uart_sunsab_port *up, 966 struct of_device *op, 967 unsigned long offset, 968 int line) 969{ 970 up->port.line = line; 971 up->port.dev = &op->dev; 972 973 up->port.mapbase = op->resource[0].start + offset; 974 up->port.membase = of_ioremap(&op->resource[0], offset, 975 sizeof(union sab82532_async_regs), 976 "sab"); 977 if (!up->port.membase) 978 return -ENOMEM; 979 up->regs = (union sab82532_async_regs __iomem *) up->port.membase; 980 981 up->port.irq = op->irqs[0]; 982 983 up->port.fifosize = SAB82532_XMIT_FIFO_SIZE; 984 up->port.iotype = UPIO_MEM; 985 986 writeb(SAB82532_IPC_IC_ACT_LOW, &up->regs->w.ipc); 987 988 up->port.ops = &sunsab_pops; 989 up->port.type = PORT_SUNSAB; 990 up->port.uartclk = SAB_BASE_BAUD; 991 992 up->type = readb(&up->regs->r.vstr) & 0x0f; 993 writeb(~((1 << 1) | (1 << 2) | (1 << 4)), &up->regs->w.pcr); 994 writeb(0xff, &up->regs->w.pim); 995 if ((up->port.line & 0x1) == 0) { 996 up->pvr_dsr_bit = (1 << 0); 997 up->pvr_dtr_bit = (1 << 1); 998 } else { 999 up->pvr_dsr_bit = (1 << 3); 1000 up->pvr_dtr_bit = (1 << 2); 1001 } 1002 up->cached_pvr = (1 << 1) | (1 << 2) | (1 << 4); 1003 writeb(up->cached_pvr, &up->regs->w.pvr); 1004 up->cached_mode = readb(&up->regs->rw.mode); 1005 up->cached_mode |= SAB82532_MODE_FRTS; 1006 writeb(up->cached_mode, &up->regs->rw.mode); 1007 up->cached_mode |= SAB82532_MODE_RTS; 1008 writeb(up->cached_mode, &up->regs->rw.mode); 1009 1010 up->tec_timeout = SAB82532_MAX_TEC_TIMEOUT; 1011 up->cec_timeout = SAB82532_MAX_CEC_TIMEOUT; 1012 1013 if (!(up->port.line & 0x01)) { 1014 int err; 1015 1016 err = request_irq(up->port.irq, sunsab_interrupt, 1017 IRQF_SHARED, "sab", up); 1018 if (err) { 1019 of_iounmap(&op->resource[0], 1020 up->port.membase, 1021 sizeof(union sab82532_async_regs)); 1022 return err; 1023 } 1024 } 1025 1026 return 0; 1027} 1028 1029static int __devinit sab_probe(struct of_device *op, const struct of_device_id *match) 1030{ 1031 static int inst; 1032 struct uart_sunsab_port *up; 1033 int err; 1034 1035 up = &sunsab_ports[inst * 2]; 1036 1037 err = sunsab_init_one(&up[0], op, 1038 0, 1039 (inst * 2) + 0); 1040 if (err) 1041 return err; 1042 1043 err = sunsab_init_one(&up[1], op, 1044 sizeof(union sab82532_async_regs), 1045 (inst * 2) + 1); 1046 if (err) { 1047 of_iounmap(&op->resource[0], 1048 up[0].port.membase, 1049 sizeof(union sab82532_async_regs)); 1050 free_irq(up[0].port.irq, &up[0]); 1051 return err; 1052 } 1053 1054 uart_add_one_port(&sunsab_reg, &up[0].port); 1055 uart_add_one_port(&sunsab_reg, &up[1].port); 1056 1057 dev_set_drvdata(&op->dev, &up[0]); 1058 1059 inst++; 1060 1061 return 0; 1062} 1063 1064static void __devexit sab_remove_one(struct uart_sunsab_port *up) 1065{ 1066 struct of_device *op = to_of_device(up->port.dev); 1067 1068 uart_remove_one_port(&sunsab_reg, &up->port); 1069 if (!(up->port.line & 1)) 1070 free_irq(up->port.irq, up); 1071 of_iounmap(&op->resource[0], 1072 up->port.membase, 1073 sizeof(union sab82532_async_regs)); 1074} 1075 1076static int __devexit sab_remove(struct of_device *op) 1077{ 1078 struct uart_sunsab_port *up = dev_get_drvdata(&op->dev); 1079 1080 sab_remove_one(&up[0]); 1081 sab_remove_one(&up[1]); 1082 1083 dev_set_drvdata(&op->dev, NULL); 1084 1085 return 0; 1086} 1087 1088static struct of_device_id sab_match[] = { 1089 { 1090 .name = "se", 1091 }, 1092 { 1093 .name = "serial", 1094 .compatible = "sab82532", 1095 }, 1096 {}, 1097}; 1098MODULE_DEVICE_TABLE(of, sab_match); 1099 1100static struct of_platform_driver sab_driver = { 1101 .name = "sab", 1102 .match_table = sab_match, 1103 .probe = sab_probe, 1104 .remove = __devexit_p(sab_remove), 1105}; 1106 1107static int __init sunsab_init(void) 1108{ 1109 struct device_node *dp; 1110 int err; 1111 1112 num_channels = 0; 1113 for_each_node_by_name(dp, "se") 1114 num_channels += 2; 1115 for_each_node_by_name(dp, "serial") { 1116 if (of_device_is_compatible(dp, "sab82532")) 1117 num_channels += 2; 1118 } 1119 1120 if (num_channels) { 1121 sunsab_ports = kzalloc(sizeof(struct uart_sunsab_port) * 1122 num_channels, GFP_KERNEL); 1123 if (!sunsab_ports) 1124 return -ENOMEM; 1125 1126 sunsab_reg.minor = sunserial_current_minor; 1127 sunsab_reg.nr = num_channels; 1128 1129 err = uart_register_driver(&sunsab_reg); 1130 if (err) { 1131 kfree(sunsab_ports); 1132 sunsab_ports = NULL; 1133 1134 return err; 1135 } 1136 1137 sunsab_reg.tty_driver->name_base = sunsab_reg.minor - 64; 1138 sunsab_reg.cons = SUNSAB_CONSOLE(); 1139 sunserial_current_minor += num_channels; 1140 } 1141 1142 return of_register_driver(&sab_driver, &of_bus_type); 1143} 1144 1145static void __exit sunsab_exit(void) 1146{ 1147 of_unregister_driver(&sab_driver); 1148 if (num_channels) { 1149 sunserial_current_minor -= num_channels; 1150 uart_unregister_driver(&sunsab_reg); 1151 } 1152 1153 kfree(sunsab_ports); 1154 sunsab_ports = NULL; 1155} 1156 1157module_init(sunsab_init); 1158module_exit(sunsab_exit); 1159 1160MODULE_AUTHOR("Eddie C. Dost and David S. Miller"); 1161MODULE_DESCRIPTION("Sun SAB82532 serial port driver"); 1162MODULE_LICENSE("GPL"); 1163