1/* $Id: sh-sci.h,v 1.1.1.1 2007/08/03 18:53:00 Exp $ 2 * 3 * linux/drivers/serial/sh-sci.h 4 * 5 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO) 6 * Copyright (C) 1999, 2000 Niibe Yutaka 7 * Copyright (C) 2000 Greg Banks 8 * Copyright (C) 2002, 2003 Paul Mundt 9 * Modified to support multiple serial ports. Stuart Menefy (May 2000). 10 * Modified to support SH7300(SH-Mobile) SCIF. Takashi Kusuda (Jun 2003). 11 * Modified to support H8/300 Series Yoshinori Sato (Feb 2004). 12 */ 13#include <linux/serial_core.h> 14#include <asm/io.h> 15 16#if defined(__H8300H__) || defined(__H8300S__) 17#include <asm/gpio.h> 18#if defined(CONFIG_H83007) || defined(CONFIG_H83068) 19#include <asm/regs306x.h> 20#endif 21#if defined(CONFIG_H8S2678) 22#include <asm/regs267x.h> 23#endif 24#endif 25 26#if defined(CONFIG_CPU_SUBTYPE_SH7708) 27# define SCSPTR 0xffffff7c /* 8 bit */ 28# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ 29# define SCI_ONLY 30#elif defined(CONFIG_CPU_SUBTYPE_SH7707) || \ 31 defined(CONFIG_CPU_SUBTYPE_SH7709) || \ 32 defined(CONFIG_CPU_SUBTYPE_SH7706) 33# define SCPCR 0xA4000116 /* 16 bit SCI and SCIF */ 34# define SCPDR 0xA4000136 /* 8 bit SCI and SCIF */ 35# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ 36# define SCI_AND_SCIF 37#elif defined(CONFIG_CPU_SUBTYPE_SH7705) 38# define SCIF0 0xA4400000 39# define SCIF2 0xA4410000 40# define SCSMR_Ir 0xA44A0000 41# define IRDA_SCIF SCIF0 42# define SCPCR 0xA4000116 43# define SCPDR 0xA4000136 44 45/* Set the clock source, 46 * SCIF2 (0xA4410000) -> External clock, SCK pin used as clock input 47 * SCIF0 (0xA4400000) -> Internal clock, SCK pin as serial clock output 48 */ 49# define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0 50# define SCIF_ONLY 51#elif defined(CONFIG_SH_RTS7751R2D) 52# define SCSPTR2 0xFFE80020 /* 16 bit SCIF */ 53# define SCIF_ORER 0x0001 /* overrun error bit */ 54# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 55# define SCIF_ONLY 56#elif defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7751) 57# define SCSPTR1 0xffe0001c /* 8 bit SCI */ 58# define SCSPTR2 0xFFE80020 /* 16 bit SCIF */ 59# define SCIF_ORER 0x0001 /* overrun error bit */ 60# define SCSCR_INIT(port) (((port)->type == PORT_SCI) ? \ 61 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \ 62 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ ) 63# define SCI_AND_SCIF 64#elif defined(CONFIG_CPU_SUBTYPE_SH7760) 65# define SCSPTR0 0xfe600024 /* 16 bit SCIF */ 66# define SCSPTR1 0xfe610024 /* 16 bit SCIF */ 67# define SCSPTR2 0xfe620024 /* 16 bit SCIF */ 68# define SCIF_ORER 0x0001 /* overrun error bit */ 69# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 70# define SCIF_ONLY 71#elif defined(CONFIG_CPU_SUBTYPE_SH7300) 72# define SCPCR 0xA4050116 /* 16 bit SCIF */ 73# define SCPDR 0xA4050136 /* 16 bit SCIF */ 74# define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */ 75# define SCIF_ONLY 76#elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712) 77# define SCSPTR0 0xA4400000 /* 16 bit SCIF */ 78# define SCI_NPORTS 2 79# define SCIF_ORER 0x0001 /* overrun error bit */ 80# define PACR 0xa4050100 81# define PBCR 0xa4050102 82# define SCSCR_INIT(port) 0x3B 83# define SCIF_ONLY 84#elif defined(CONFIG_CPU_SUBTYPE_SH73180) 85# define SCPDR 0xA4050138 /* 16 bit SCIF */ 86# define SCSPTR2 SCPDR 87# define SCIF_ORER 0x0001 /* overrun error bit */ 88# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1 */ 89# define SCIF_ONLY 90#elif defined(CONFIG_CPU_SUBTYPE_SH7343) 91# define SCSPTR0 0xffe00010 /* 16 bit SCIF */ 92# define SCSPTR1 0xffe10010 /* 16 bit SCIF */ 93# define SCSPTR2 0xffe20010 /* 16 bit SCIF */ 94# define SCSPTR3 0xffe30010 /* 16 bit SCIF */ 95# define SCSCR_INIT(port) 0x32 /* TIE=0,RIE=0,TE=1,RE=1,REIE=0,CKE=1 */ 96# define SCIF_ONLY 97#elif defined(CONFIG_CPU_SUBTYPE_SH7722) 98# define SCPDR0 0xA405013E /* 16 bit SCIF0 PSDR */ 99# define SCSPTR0 SCPDR0 100# define SCIF_ORER 0x0001 /* overrun error bit */ 101# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 102# define SCIF_ONLY 103# define PORT_PSCR 0xA405011E 104#elif defined(CONFIG_CPU_SUBTYPE_SH4_202) 105# define SCSPTR2 0xffe80020 /* 16 bit SCIF */ 106# define SCIF_ORER 0x0001 /* overrun error bit */ 107# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 108# define SCIF_ONLY 109#elif defined(CONFIG_CPU_SUBTYPE_ST40STB1) 110# define SCSPTR1 0xffe00020 /* 16 bit SCIF */ 111# define SCSPTR2 0xffe80020 /* 16 bit SCIF */ 112# define SCIF_ORER 0x0001 /* overrun error bit */ 113# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 114# define SCIF_ONLY 115#elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103) 116# include <asm/hardware.h> 117# define SCIF_BASE_ADDR 0x01030000 118# define SCIF_ADDR_SH5 PHYS_PERIPHERAL_BLOCK+SCIF_BASE_ADDR 119# define SCIF_PTR2_OFFS 0x0000020 120# define SCIF_LSR2_OFFS 0x0000024 121# define SCSPTR2 ((port->mapbase)+SCIF_PTR2_OFFS) /* 16 bit SCIF */ 122# define SCLSR2 ((port->mapbase)+SCIF_LSR2_OFFS) /* 16 bit SCIF */ 123# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0, 124 TE=1,RE=1,REIE=1 */ 125# define SCIF_ONLY 126#elif defined(CONFIG_H83007) || defined(CONFIG_H83068) 127# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ 128# define SCI_ONLY 129# define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port) 130#elif defined(CONFIG_H8S2678) 131# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ 132# define SCI_ONLY 133# define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port) 134#elif defined(CONFIG_CPU_SUBTYPE_SH7770) 135# define SCSPTR0 0xff923020 /* 16 bit SCIF */ 136# define SCSPTR1 0xff924020 /* 16 bit SCIF */ 137# define SCSPTR2 0xff925020 /* 16 bit SCIF */ 138# define SCIF_ORER 0x0001 /* overrun error bit */ 139# define SCSCR_INIT(port) 0x3c /* TIE=0,RIE=0,TE=1,RE=1,REIE=1,cke=2 */ 140# define SCIF_ONLY 141#elif defined(CONFIG_CPU_SUBTYPE_SH7780) 142# define SCSPTR0 0xffe00024 /* 16 bit SCIF */ 143# define SCSPTR1 0xffe10024 /* 16 bit SCIF */ 144# define SCIF_ORER 0x0001 /* Overrun error bit */ 145# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 146# define SCIF_ONLY 147#elif defined(CONFIG_CPU_SUBTYPE_SH7785) 148# define SCSPTR0 0xffea0024 /* 16 bit SCIF */ 149# define SCSPTR1 0xffeb0024 /* 16 bit SCIF */ 150# define SCSPTR2 0xffec0024 /* 16 bit SCIF */ 151# define SCSPTR3 0xffed0024 /* 16 bit SCIF */ 152# define SCSPTR4 0xffee0024 /* 16 bit SCIF */ 153# define SCSPTR5 0xffef0024 /* 16 bit SCIF */ 154# define SCIF_OPER 0x0001 /* Overrun error bit */ 155# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 156# define SCIF_ONLY 157#elif defined(CONFIG_CPU_SUBTYPE_SH7206) 158# define SCSPTR0 0xfffe8020 /* 16 bit SCIF */ 159# define SCSPTR1 0xfffe8820 /* 16 bit SCIF */ 160# define SCSPTR2 0xfffe9020 /* 16 bit SCIF */ 161# define SCSPTR3 0xfffe9820 /* 16 bit SCIF */ 162# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 163# define SCIF_ONLY 164#elif defined(CONFIG_CPU_SUBTYPE_SH7619) 165# define SCSPTR0 0xf8400020 /* 16 bit SCIF */ 166# define SCSPTR1 0xf8410020 /* 16 bit SCIF */ 167# define SCSPTR2 0xf8420020 /* 16 bit SCIF */ 168# define SCIF_ORER 0x0001 /* overrun error bit */ 169# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 170# define SCIF_ONLY 171#else 172# error CPU subtype not defined 173#endif 174 175/* SCSCR */ 176#define SCI_CTRL_FLAGS_TIE 0x80 /* all */ 177#define SCI_CTRL_FLAGS_RIE 0x40 /* all */ 178#define SCI_CTRL_FLAGS_TE 0x20 /* all */ 179#define SCI_CTRL_FLAGS_RE 0x10 /* all */ 180#if defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7751) || \ 181 defined(CONFIG_CPU_SUBTYPE_SH7780) || defined(CONFIG_CPU_SUBTYPE_SH7785) 182#define SCI_CTRL_FLAGS_REIE 0x08 /* 7750 SCIF */ 183#else 184#define SCI_CTRL_FLAGS_REIE 0 185#endif 186/* SCI_CTRL_FLAGS_MPIE 0x08 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ 187/* SCI_CTRL_FLAGS_TEIE 0x04 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ 188/* SCI_CTRL_FLAGS_CKE1 0x02 * all */ 189/* SCI_CTRL_FLAGS_CKE0 0x01 * 7707 SCI/SCIF, 7708 SCI, 7709 SCI/SCIF, 7750 SCI */ 190 191/* SCxSR SCI */ 192#define SCI_TDRE 0x80 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ 193#define SCI_RDRF 0x40 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ 194#define SCI_ORER 0x20 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ 195#define SCI_FER 0x10 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ 196#define SCI_PER 0x08 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ 197#define SCI_TEND 0x04 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ 198/* SCI_MPB 0x02 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ 199/* SCI_MPBT 0x01 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ 200 201#define SCI_ERRORS ( SCI_PER | SCI_FER | SCI_ORER) 202 203/* SCxSR SCIF */ 204#define SCIF_ER 0x0080 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ 205#define SCIF_TEND 0x0040 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ 206#define SCIF_TDFE 0x0020 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ 207#define SCIF_BRK 0x0010 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ 208#define SCIF_FER 0x0008 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ 209#define SCIF_PER 0x0004 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ 210#define SCIF_RDF 0x0002 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ 211#define SCIF_DR 0x0001 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ 212 213#if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705) 214#define SCIF_ORER 0x0200 215#define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK | SCIF_ORER) 216#define SCIF_RFDC_MASK 0x007f 217#define SCIF_TXROOM_MAX 64 218#else 219#define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK) 220#define SCIF_RFDC_MASK 0x001f 221#define SCIF_TXROOM_MAX 16 222#endif 223 224#if defined(SCI_ONLY) 225# define SCxSR_TEND(port) SCI_TEND 226# define SCxSR_ERRORS(port) SCI_ERRORS 227# define SCxSR_RDxF(port) SCI_RDRF 228# define SCxSR_TDxE(port) SCI_TDRE 229# define SCxSR_ORER(port) SCI_ORER 230# define SCxSR_FER(port) SCI_FER 231# define SCxSR_PER(port) SCI_PER 232# define SCxSR_BRK(port) 0x00 233# define SCxSR_RDxF_CLEAR(port) 0xbc 234# define SCxSR_ERROR_CLEAR(port) 0xc4 235# define SCxSR_TDxE_CLEAR(port) 0x78 236# define SCxSR_BREAK_CLEAR(port) 0xc4 237#elif defined(SCIF_ONLY) 238# define SCxSR_TEND(port) SCIF_TEND 239# define SCxSR_ERRORS(port) SCIF_ERRORS 240# define SCxSR_RDxF(port) SCIF_RDF 241# define SCxSR_TDxE(port) SCIF_TDFE 242#if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705) 243# define SCxSR_ORER(port) SCIF_ORER 244#else 245# define SCxSR_ORER(port) 0x0000 246#endif 247# define SCxSR_FER(port) SCIF_FER 248# define SCxSR_PER(port) SCIF_PER 249# define SCxSR_BRK(port) SCIF_BRK 250#if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705) 251# define SCxSR_RDxF_CLEAR(port) (sci_in(port,SCxSR)&0xfffc) 252# define SCxSR_ERROR_CLEAR(port) (sci_in(port,SCxSR)&0xfd73) 253# define SCxSR_TDxE_CLEAR(port) (sci_in(port,SCxSR)&0xffdf) 254# define SCxSR_BREAK_CLEAR(port) (sci_in(port,SCxSR)&0xffe3) 255#else 256/* SH7705 can also use this, clearing is same between 7705 and 7709 and 7300 */ 257# define SCxSR_RDxF_CLEAR(port) 0x00fc 258# define SCxSR_ERROR_CLEAR(port) 0x0073 259# define SCxSR_TDxE_CLEAR(port) 0x00df 260# define SCxSR_BREAK_CLEAR(port) 0x00e3 261#endif 262#else 263# define SCxSR_TEND(port) (((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND) 264# define SCxSR_ERRORS(port) (((port)->type == PORT_SCI) ? SCI_ERRORS : SCIF_ERRORS) 265# define SCxSR_RDxF(port) (((port)->type == PORT_SCI) ? SCI_RDRF : SCIF_RDF) 266# define SCxSR_TDxE(port) (((port)->type == PORT_SCI) ? SCI_TDRE : SCIF_TDFE) 267# define SCxSR_ORER(port) (((port)->type == PORT_SCI) ? SCI_ORER : 0x0000) 268# define SCxSR_FER(port) (((port)->type == PORT_SCI) ? SCI_FER : SCIF_FER) 269# define SCxSR_PER(port) (((port)->type == PORT_SCI) ? SCI_PER : SCIF_PER) 270# define SCxSR_BRK(port) (((port)->type == PORT_SCI) ? 0x00 : SCIF_BRK) 271# define SCxSR_RDxF_CLEAR(port) (((port)->type == PORT_SCI) ? 0xbc : 0x00fc) 272# define SCxSR_ERROR_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x0073) 273# define SCxSR_TDxE_CLEAR(port) (((port)->type == PORT_SCI) ? 0x78 : 0x00df) 274# define SCxSR_BREAK_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x00e3) 275#endif 276 277/* SCFCR */ 278#define SCFCR_RFRST 0x0002 279#define SCFCR_TFRST 0x0004 280#define SCFCR_TCRST 0x4000 281#define SCFCR_MCE 0x0008 282 283#define SCI_MAJOR 204 284#define SCI_MINOR_START 8 285 286/* Generic serial flags */ 287#define SCI_RX_THROTTLE 0x0000001 288 289#define SCI_MAGIC 0xbabeface 290 291/* 292 * Events are used to schedule things to happen at timer-interrupt 293 * time, instead of at rs interrupt time. 294 */ 295#define SCI_EVENT_WRITE_WAKEUP 0 296 297#define SCI_IN(size, offset) \ 298 unsigned int addr = port->mapbase + (offset); \ 299 if ((size) == 8) { \ 300 return ctrl_inb(addr); \ 301 } else { \ 302 return ctrl_inw(addr); \ 303 } 304#define SCI_OUT(size, offset, value) \ 305 unsigned int addr = port->mapbase + (offset); \ 306 if ((size) == 8) { \ 307 ctrl_outb(value, addr); \ 308 } else { \ 309 ctrl_outw(value, addr); \ 310 } 311 312#define CPU_SCIx_FNS(name, sci_offset, sci_size, scif_offset, scif_size)\ 313 static inline unsigned int sci_##name##_in(struct uart_port *port) \ 314 { \ 315 if (port->type == PORT_SCI) { \ 316 SCI_IN(sci_size, sci_offset) \ 317 } else { \ 318 SCI_IN(scif_size, scif_offset); \ 319 } \ 320 } \ 321 static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \ 322 { \ 323 if (port->type == PORT_SCI) { \ 324 SCI_OUT(sci_size, sci_offset, value) \ 325 } else { \ 326 SCI_OUT(scif_size, scif_offset, value); \ 327 } \ 328 } 329 330#define CPU_SCIF_FNS(name, scif_offset, scif_size) \ 331 static inline unsigned int sci_##name##_in(struct uart_port *port) \ 332 { \ 333 SCI_IN(scif_size, scif_offset); \ 334 } \ 335 static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \ 336 { \ 337 SCI_OUT(scif_size, scif_offset, value); \ 338 } 339 340#define CPU_SCI_FNS(name, sci_offset, sci_size) \ 341 static inline unsigned int sci_##name##_in(struct uart_port* port) \ 342 { \ 343 SCI_IN(sci_size, sci_offset); \ 344 } \ 345 static inline void sci_##name##_out(struct uart_port* port, unsigned int value) \ 346 { \ 347 SCI_OUT(sci_size, sci_offset, value); \ 348 } 349 350#ifdef CONFIG_CPU_SH3 351#if defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712) 352#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \ 353 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \ 354 h8_sci_offset, h8_sci_size) \ 355 CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size) 356#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \ 357 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) 358#elif defined(CONFIG_CPU_SUBTYPE_SH7300) || \ 359 defined(CONFIG_CPU_SUBTYPE_SH7705) 360#define SCIF_FNS(name, scif_offset, scif_size) \ 361 CPU_SCIF_FNS(name, scif_offset, scif_size) 362#else 363#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \ 364 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \ 365 h8_sci_offset, h8_sci_size) \ 366 CPU_SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh3_scif_offset, sh3_scif_size) 367#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \ 368 CPU_SCIF_FNS(name, sh3_scif_offset, sh3_scif_size) 369#endif 370#elif defined(__H8300H__) || defined(__H8300S__) 371#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \ 372 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \ 373 h8_sci_offset, h8_sci_size) \ 374 CPU_SCI_FNS(name, h8_sci_offset, h8_sci_size) 375#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) 376#else 377#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \ 378 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \ 379 h8_sci_offset, h8_sci_size) \ 380 CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size) 381#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \ 382 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) 383#endif 384 385#if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705) 386 387SCIF_FNS(SCSMR, 0x00, 16) 388SCIF_FNS(SCBRR, 0x04, 8) 389SCIF_FNS(SCSCR, 0x08, 16) 390SCIF_FNS(SCTDSR, 0x0c, 8) 391SCIF_FNS(SCFER, 0x10, 16) 392SCIF_FNS(SCxSR, 0x14, 16) 393SCIF_FNS(SCFCR, 0x18, 16) 394SCIF_FNS(SCFDR, 0x1c, 16) 395SCIF_FNS(SCxTDR, 0x20, 8) 396SCIF_FNS(SCxRDR, 0x24, 8) 397SCIF_FNS(SCLSR, 0x24, 16) 398#else 399/* reg SCI/SH3 SCI/SH4 SCIF/SH3 SCIF/SH4 SCI/H8*/ 400/* name off sz off sz off sz off sz off sz*/ 401SCIx_FNS(SCSMR, 0x00, 8, 0x00, 8, 0x00, 8, 0x00, 16, 0x00, 8) 402SCIx_FNS(SCBRR, 0x02, 8, 0x04, 8, 0x02, 8, 0x04, 8, 0x01, 8) 403SCIx_FNS(SCSCR, 0x04, 8, 0x08, 8, 0x04, 8, 0x08, 16, 0x02, 8) 404SCIx_FNS(SCxTDR, 0x06, 8, 0x0c, 8, 0x06, 8, 0x0C, 8, 0x03, 8) 405SCIx_FNS(SCxSR, 0x08, 8, 0x10, 8, 0x08, 16, 0x10, 16, 0x04, 8) 406SCIx_FNS(SCxRDR, 0x0a, 8, 0x14, 8, 0x0A, 8, 0x14, 8, 0x05, 8) 407SCIF_FNS(SCFCR, 0x0c, 8, 0x18, 16) 408#if defined(CONFIG_CPU_SUBTYPE_SH7760) || defined(CONFIG_CPU_SUBTYPE_SH7780) || \ 409 defined(CONFIG_CPU_SUBTYPE_SH7785) 410SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16) 411SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16) 412SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16) 413SCIF_FNS(SCSPTR, 0, 0, 0x24, 16) 414SCIF_FNS(SCLSR, 0, 0, 0x28, 16) 415#else 416SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16) 417SCIF_FNS(SCSPTR, 0, 0, 0x20, 16) 418SCIF_FNS(SCLSR, 0, 0, 0x24, 16) 419#endif 420#endif 421#define sci_in(port, reg) sci_##reg##_in(port) 422#define sci_out(port, reg, value) sci_##reg##_out(port, value) 423 424/* H8/300 series SCI pins assignment */ 425#if defined(__H8300H__) || defined(__H8300S__) 426static const struct __attribute__((packed)) { 427 int port; /* GPIO port no */ 428 unsigned short rx,tx; /* GPIO bit no */ 429} h8300_sci_pins[] = { 430#if defined(CONFIG_H83007) || defined(CONFIG_H83068) 431 { /* SCI0 */ 432 .port = H8300_GPIO_P9, 433 .rx = H8300_GPIO_B2, 434 .tx = H8300_GPIO_B0, 435 }, 436 { /* SCI1 */ 437 .port = H8300_GPIO_P9, 438 .rx = H8300_GPIO_B3, 439 .tx = H8300_GPIO_B1, 440 }, 441 { /* SCI2 */ 442 .port = H8300_GPIO_PB, 443 .rx = H8300_GPIO_B7, 444 .tx = H8300_GPIO_B6, 445 } 446#elif defined(CONFIG_H8S2678) 447 { /* SCI0 */ 448 .port = H8300_GPIO_P3, 449 .rx = H8300_GPIO_B2, 450 .tx = H8300_GPIO_B0, 451 }, 452 { /* SCI1 */ 453 .port = H8300_GPIO_P3, 454 .rx = H8300_GPIO_B3, 455 .tx = H8300_GPIO_B1, 456 }, 457 { /* SCI2 */ 458 .port = H8300_GPIO_P5, 459 .rx = H8300_GPIO_B1, 460 .tx = H8300_GPIO_B0, 461 } 462#endif 463}; 464#endif 465 466#if defined(CONFIG_CPU_SUBTYPE_SH7708) 467static inline int sci_rxd_in(struct uart_port *port) 468{ 469 if (port->mapbase == 0xfffffe80) 470 return ctrl_inb(SCSPTR)&0x01 ? 1 : 0; /* SCI */ 471 return 1; 472} 473#elif defined(CONFIG_CPU_SUBTYPE_SH7707) || \ 474 defined(CONFIG_CPU_SUBTYPE_SH7709) || \ 475 defined(CONFIG_CPU_SUBTYPE_SH7706) 476static inline int sci_rxd_in(struct uart_port *port) 477{ 478 if (port->mapbase == 0xfffffe80) 479 return ctrl_inb(SCPDR)&0x01 ? 1 : 0; /* SCI */ 480 if (port->mapbase == 0xa4000150) 481 return ctrl_inb(SCPDR)&0x10 ? 1 : 0; /* SCIF */ 482 if (port->mapbase == 0xa4000140) 483 return ctrl_inb(SCPDR)&0x04 ? 1 : 0; /* IRDA */ 484 return 1; 485} 486#elif defined(CONFIG_CPU_SUBTYPE_SH7705) 487static inline int sci_rxd_in(struct uart_port *port) 488{ 489 if (port->mapbase == SCIF0) 490 return ctrl_inb(SCPDR)&0x04 ? 1 : 0; /* IRDA */ 491 if (port->mapbase == SCIF2) 492 return ctrl_inb(SCPDR)&0x10 ? 1 : 0; /* SCIF */ 493 return 1; 494} 495#elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712) 496static inline int sci_rxd_in(struct uart_port *port) 497{ 498 return sci_in(port,SCxSR)&0x0010 ? 1 : 0; 499} 500static inline void set_sh771x_scif_pfc(struct uart_port *port) 501{ 502 if (port->mapbase == 0xA4400000){ 503 ctrl_outw(ctrl_inw(PACR)&0xffc0,PACR); 504 ctrl_outw(ctrl_inw(PBCR)&0x0fff,PBCR); 505 return; 506 } 507 if (port->mapbase == 0xA4410000){ 508 ctrl_outw(ctrl_inw(PBCR)&0xf003,PBCR); 509 return; 510 } 511} 512 513#elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \ 514 defined(CONFIG_CPU_SUBTYPE_SH7751) || \ 515 defined(CONFIG_CPU_SUBTYPE_SH4_202) 516static inline int sci_rxd_in(struct uart_port *port) 517{ 518#ifndef SCIF_ONLY 519 if (port->mapbase == 0xffe00000) 520 return ctrl_inb(SCSPTR1)&0x01 ? 1 : 0; /* SCI */ 521#endif 522#ifndef SCI_ONLY 523 if (port->mapbase == 0xffe80000) 524 return ctrl_inw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */ 525#endif 526 return 1; 527} 528#elif defined(CONFIG_CPU_SUBTYPE_SH7760) 529static inline int sci_rxd_in(struct uart_port *port) 530{ 531 if (port->mapbase == 0xfe600000) 532 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ 533 if (port->mapbase == 0xfe610000) 534 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ 535 if (port->mapbase == 0xfe620000) 536 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */ 537 return 1; 538} 539#elif defined(CONFIG_CPU_SUBTYPE_SH7300) 540static inline int sci_rxd_in(struct uart_port *port) 541{ 542 if (port->mapbase == 0xa4430000) 543 return ctrl_inb(SCPDR)&0x01 ? 1 : 0; /* SCIF0 */ 544 return 1; 545} 546#elif defined(CONFIG_CPU_SUBTYPE_SH73180) 547static inline int sci_rxd_in(struct uart_port *port) 548{ 549 return ctrl_inb(SCPDR)&0x01 ? 1 : 0; /* SCIF0 */ 550} 551#elif defined(CONFIG_CPU_SUBTYPE_SH7343) 552static inline int sci_rxd_in(struct uart_port *port) 553{ 554 if (port->mapbase == 0xffe00000) 555 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ 556 if (port->mapbase == 0xffe10000) 557 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ 558 if (port->mapbase == 0xffe20000) 559 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */ 560 if (port->mapbase == 0xffe30000) 561 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */ 562 return 1; 563} 564#elif defined(CONFIG_CPU_SUBTYPE_SH7722) 565static inline int sci_rxd_in(struct uart_port *port) 566{ 567 if (port->mapbase == 0xffe00000) 568 return ctrl_inb(SCPDR0) & 0x0001 ? 1 : 0; /* SCIF0 */ 569 return 1; 570} 571#elif defined(CONFIG_CPU_SUBTYPE_ST40STB1) 572static inline int sci_rxd_in(struct uart_port *port) 573{ 574 if (port->mapbase == 0xffe00000) 575 return ctrl_inw(SCSPTR1)&0x0001 ? 1 : 0; /* SCIF */ 576 else 577 return ctrl_inw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */ 578 579} 580#elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103) 581static inline int sci_rxd_in(struct uart_port *port) 582{ 583 return sci_in(port, SCSPTR)&0x0001 ? 1 : 0; /* SCIF */ 584} 585#elif defined(__H8300H__) || defined(__H8300S__) 586static inline int sci_rxd_in(struct uart_port *port) 587{ 588 int ch = (port->mapbase - SMR0) >> 3; 589 return (H8300_SCI_DR(ch) & h8300_sci_pins[ch].rx) ? 1 : 0; 590} 591#elif defined(CONFIG_CPU_SUBTYPE_SH7770) 592static inline int sci_rxd_in(struct uart_port *port) 593{ 594 if (port->mapbase == 0xff923000) 595 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ 596 if (port->mapbase == 0xff924000) 597 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ 598 if (port->mapbase == 0xff925000) 599 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */ 600 return 1; 601} 602#elif defined(CONFIG_CPU_SUBTYPE_SH7780) 603static inline int sci_rxd_in(struct uart_port *port) 604{ 605 if (port->mapbase == 0xffe00000) 606 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ 607 if (port->mapbase == 0xffe10000) 608 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ 609 return 1; 610} 611#elif defined(CONFIG_CPU_SUBTYPE_SH7785) 612static inline int sci_rxd_in(struct uart_port *port) 613{ 614 if (port->mapbase == 0xffea0000) 615 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ 616 if (port->mapbase == 0xffeb0000) 617 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ 618 if (port->mapbase == 0xffec0000) 619 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */ 620 if (port->mapbase == 0xffed0000) 621 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */ 622 if (port->mapbase == 0xffee0000) 623 return ctrl_inw(SCSPTR4) & 0x0001 ? 1 : 0; /* SCIF */ 624 if (port->mapbase == 0xffef0000) 625 return ctrl_inw(SCSPTR5) & 0x0001 ? 1 : 0; /* SCIF */ 626 return 1; 627} 628#elif defined(CONFIG_CPU_SUBTYPE_SH7206) 629static inline int sci_rxd_in(struct uart_port *port) 630{ 631 if (port->mapbase == 0xfffe8000) 632 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ 633 if (port->mapbase == 0xfffe8800) 634 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ 635 if (port->mapbase == 0xfffe9000) 636 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */ 637 if (port->mapbase == 0xfffe9800) 638 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */ 639 return 1; 640} 641#elif defined(CONFIG_CPU_SUBTYPE_SH7619) 642static inline int sci_rxd_in(struct uart_port *port) 643{ 644 if (port->mapbase == 0xf8400000) 645 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ 646 if (port->mapbase == 0xf8410000) 647 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ 648 if (port->mapbase == 0xf8420000) 649 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */ 650 return 1; 651} 652#endif 653 654/* 655 * Values for the BitRate Register (SCBRR) 656 * 657 * The values are actually divisors for a frequency which can 658 * be internal to the SH3 (14.7456MHz) or derived from an external 659 * clock source. This driver assumes the internal clock is used; 660 * to support using an external clock source, config options or 661 * possibly command-line options would need to be added. 662 * 663 * Also, to support speeds below 2400 (why?) the lower 2 bits of 664 * the SCSMR register would also need to be set to non-zero values. 665 * 666 * -- Greg Banks 27Feb2000 667 * 668 * Answer: The SCBRR register is only eight bits, and the value in 669 * it gets larger with lower baud rates. At around 2400 (depending on 670 * the peripherial module clock) you run out of bits. However the 671 * lower two bits of SCSMR allow the module clock to be divided down, 672 * scaling the value which is needed in SCBRR. 673 * 674 * -- Stuart Menefy - 23 May 2000 675 * 676 * I meant, why would anyone bother with bitrates below 2400. 677 * 678 * -- Greg Banks - 7Jul2000 679 * 680 * You "speedist"! How will I use my 110bps ASR-33 teletype with paper 681 * tape reader as a console! 682 * 683 * -- Mitch Davis - 15 Jul 2000 684 */ 685 686#if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7780) || \ 687 defined(CONFIG_CPU_SUBTYPE_SH7785) 688#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1) 689#elif defined(CONFIG_CPU_SUBTYPE_SH7705) 690#define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1) 691#elif defined(__H8300H__) || defined(__H8300S__) 692#define SCBRR_VALUE(bps) (((CONFIG_CPU_CLOCK*1000/32)/bps)-1) 693#elif defined(CONFIG_SUPERH64) 694#define SCBRR_VALUE(bps) ((current_cpu_data.module_clock+16*bps)/(32*bps)-1) 695#else /* Generic SH */ 696#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1) 697#endif 698