1/* 2 * Generic driver for the MPSC (UART mode) on Marvell parts (e.g., GT64240, 3 * GT64260, MV64340, MV64360, GT96100, ... ). 4 * 5 * Author: Mark A. Greer <mgreer@mvista.com> 6 * 7 * Based on an old MPSC driver that was in the linuxppc tree. It appears to 8 * have been created by Chris Zankel (formerly of MontaVista) but there 9 * is no proper Copyright so I'm not sure. Apparently, parts were also 10 * taken from PPCBoot (now U-Boot). Also based on drivers/serial/8250.c 11 * by Russell King. 12 * 13 * 2004 (c) MontaVista, Software, Inc. This file is licensed under 14 * the terms of the GNU General Public License version 2. This program 15 * is licensed "as is" without any warranty of any kind, whether express 16 * or implied. 17 */ 18 19 20#if defined(CONFIG_SERIAL_MPSC_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 21#define SUPPORT_SYSRQ 22#endif 23 24#include <linux/module.h> 25#include <linux/moduleparam.h> 26#include <linux/tty.h> 27#include <linux/tty_flip.h> 28#include <linux/ioport.h> 29#include <linux/init.h> 30#include <linux/console.h> 31#include <linux/sysrq.h> 32#include <linux/serial.h> 33#include <linux/serial_core.h> 34#include <linux/delay.h> 35#include <linux/device.h> 36#include <linux/dma-mapping.h> 37#include <linux/mv643xx.h> 38#include <linux/platform_device.h> 39 40#include <asm/io.h> 41#include <asm/irq.h> 42 43#if defined(CONFIG_SERIAL_MPSC_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 44#define SUPPORT_SYSRQ 45#endif 46 47#define MPSC_NUM_CTLRS 2 48 49/* 50 * Descriptors and buffers must be cache line aligned. 51 * Buffers lengths must be multiple of cache line size. 52 * Number of Tx & Rx descriptors must be powers of 2. 53 */ 54#define MPSC_RXR_ENTRIES 32 55#define MPSC_RXRE_SIZE dma_get_cache_alignment() 56#define MPSC_RXR_SIZE (MPSC_RXR_ENTRIES * MPSC_RXRE_SIZE) 57#define MPSC_RXBE_SIZE dma_get_cache_alignment() 58#define MPSC_RXB_SIZE (MPSC_RXR_ENTRIES * MPSC_RXBE_SIZE) 59 60#define MPSC_TXR_ENTRIES 32 61#define MPSC_TXRE_SIZE dma_get_cache_alignment() 62#define MPSC_TXR_SIZE (MPSC_TXR_ENTRIES * MPSC_TXRE_SIZE) 63#define MPSC_TXBE_SIZE dma_get_cache_alignment() 64#define MPSC_TXB_SIZE (MPSC_TXR_ENTRIES * MPSC_TXBE_SIZE) 65 66#define MPSC_DMA_ALLOC_SIZE (MPSC_RXR_SIZE + MPSC_RXB_SIZE + \ 67 MPSC_TXR_SIZE + MPSC_TXB_SIZE + \ 68 dma_get_cache_alignment() /* for alignment */) 69 70/* Rx and Tx Ring entry descriptors -- assume entry size is <= cacheline size */ 71struct mpsc_rx_desc { 72 u16 bufsize; 73 u16 bytecnt; 74 u32 cmdstat; 75 u32 link; 76 u32 buf_ptr; 77} __attribute((packed)); 78 79struct mpsc_tx_desc { 80 u16 bytecnt; 81 u16 shadow; 82 u32 cmdstat; 83 u32 link; 84 u32 buf_ptr; 85} __attribute((packed)); 86 87/* 88 * Some regs that have the erratum that you can't read them are are shared 89 * between the two MPSC controllers. This struct contains those shared regs. 90 */ 91struct mpsc_shared_regs { 92 phys_addr_t mpsc_routing_base_p; 93 phys_addr_t sdma_intr_base_p; 94 95 void __iomem *mpsc_routing_base; 96 void __iomem *sdma_intr_base; 97 98 u32 MPSC_MRR_m; 99 u32 MPSC_RCRR_m; 100 u32 MPSC_TCRR_m; 101 u32 SDMA_INTR_CAUSE_m; 102 u32 SDMA_INTR_MASK_m; 103}; 104 105/* The main driver data structure */ 106struct mpsc_port_info { 107 struct uart_port port; /* Overlay uart_port structure */ 108 109 /* Internal driver state for this ctlr */ 110 u8 ready; 111 u8 rcv_data; 112 tcflag_t c_iflag; /* save termios->c_iflag */ 113 tcflag_t c_cflag; /* save termios->c_cflag */ 114 115 /* Info passed in from platform */ 116 u8 mirror_regs; /* Need to mirror regs? */ 117 u8 cache_mgmt; /* Need manual cache mgmt? */ 118 u8 brg_can_tune; /* BRG has baud tuning? */ 119 u32 brg_clk_src; 120 u16 mpsc_max_idle; 121 int default_baud; 122 int default_bits; 123 int default_parity; 124 int default_flow; 125 126 /* Physical addresses of various blocks of registers (from platform) */ 127 phys_addr_t mpsc_base_p; 128 phys_addr_t sdma_base_p; 129 phys_addr_t brg_base_p; 130 131 /* Virtual addresses of various blocks of registers (from platform) */ 132 void __iomem *mpsc_base; 133 void __iomem *sdma_base; 134 void __iomem *brg_base; 135 136 /* Descriptor ring and buffer allocations */ 137 void *dma_region; 138 dma_addr_t dma_region_p; 139 140 dma_addr_t rxr; /* Rx descriptor ring */ 141 dma_addr_t rxr_p; /* Phys addr of rxr */ 142 u8 *rxb; /* Rx Ring I/O buf */ 143 u8 *rxb_p; /* Phys addr of rxb */ 144 u32 rxr_posn; /* First desc w/ Rx data */ 145 146 dma_addr_t txr; /* Tx descriptor ring */ 147 dma_addr_t txr_p; /* Phys addr of txr */ 148 u8 *txb; /* Tx Ring I/O buf */ 149 u8 *txb_p; /* Phys addr of txb */ 150 int txr_head; /* Where new data goes */ 151 int txr_tail; /* Where sent data comes off */ 152 spinlock_t tx_lock; /* transmit lock */ 153 154 /* Mirrored values of regs we can't read (if 'mirror_regs' set) */ 155 u32 MPSC_MPCR_m; 156 u32 MPSC_CHR_1_m; 157 u32 MPSC_CHR_2_m; 158 u32 MPSC_CHR_10_m; 159 u32 BRG_BCR_m; 160 struct mpsc_shared_regs *shared_regs; 161}; 162 163/* Hooks to platform-specific code */ 164int mpsc_platform_register_driver(void); 165void mpsc_platform_unregister_driver(void); 166 167/* Hooks back in to mpsc common to be called by platform-specific code */ 168struct mpsc_port_info *mpsc_device_probe(int index); 169struct mpsc_port_info *mpsc_device_remove(int index); 170 171/* Main MPSC Configuration Register Offsets */ 172#define MPSC_MMCRL 0x0000 173#define MPSC_MMCRH 0x0004 174#define MPSC_MPCR 0x0008 175#define MPSC_CHR_1 0x000c 176#define MPSC_CHR_2 0x0010 177#define MPSC_CHR_3 0x0014 178#define MPSC_CHR_4 0x0018 179#define MPSC_CHR_5 0x001c 180#define MPSC_CHR_6 0x0020 181#define MPSC_CHR_7 0x0024 182#define MPSC_CHR_8 0x0028 183#define MPSC_CHR_9 0x002c 184#define MPSC_CHR_10 0x0030 185#define MPSC_CHR_11 0x0034 186 187#define MPSC_MPCR_FRZ (1 << 9) 188#define MPSC_MPCR_CL_5 0 189#define MPSC_MPCR_CL_6 1 190#define MPSC_MPCR_CL_7 2 191#define MPSC_MPCR_CL_8 3 192#define MPSC_MPCR_SBL_1 0 193#define MPSC_MPCR_SBL_2 1 194 195#define MPSC_CHR_2_TEV (1<<1) 196#define MPSC_CHR_2_TA (1<<7) 197#define MPSC_CHR_2_TTCS (1<<9) 198#define MPSC_CHR_2_REV (1<<17) 199#define MPSC_CHR_2_RA (1<<23) 200#define MPSC_CHR_2_CRD (1<<25) 201#define MPSC_CHR_2_EH (1<<31) 202#define MPSC_CHR_2_PAR_ODD 0 203#define MPSC_CHR_2_PAR_SPACE 1 204#define MPSC_CHR_2_PAR_EVEN 2 205#define MPSC_CHR_2_PAR_MARK 3 206 207/* MPSC Signal Routing */ 208#define MPSC_MRR 0x0000 209#define MPSC_RCRR 0x0004 210#define MPSC_TCRR 0x0008 211 212/* Serial DMA Controller Interface Registers */ 213#define SDMA_SDC 0x0000 214#define SDMA_SDCM 0x0008 215#define SDMA_RX_DESC 0x0800 216#define SDMA_RX_BUF_PTR 0x0808 217#define SDMA_SCRDP 0x0810 218#define SDMA_TX_DESC 0x0c00 219#define SDMA_SCTDP 0x0c10 220#define SDMA_SFTDP 0x0c14 221 222#define SDMA_DESC_CMDSTAT_PE (1<<0) 223#define SDMA_DESC_CMDSTAT_CDL (1<<1) 224#define SDMA_DESC_CMDSTAT_FR (1<<3) 225#define SDMA_DESC_CMDSTAT_OR (1<<6) 226#define SDMA_DESC_CMDSTAT_BR (1<<9) 227#define SDMA_DESC_CMDSTAT_MI (1<<10) 228#define SDMA_DESC_CMDSTAT_A (1<<11) 229#define SDMA_DESC_CMDSTAT_AM (1<<12) 230#define SDMA_DESC_CMDSTAT_CT (1<<13) 231#define SDMA_DESC_CMDSTAT_C (1<<14) 232#define SDMA_DESC_CMDSTAT_ES (1<<15) 233#define SDMA_DESC_CMDSTAT_L (1<<16) 234#define SDMA_DESC_CMDSTAT_F (1<<17) 235#define SDMA_DESC_CMDSTAT_P (1<<18) 236#define SDMA_DESC_CMDSTAT_EI (1<<23) 237#define SDMA_DESC_CMDSTAT_O (1<<31) 238 239#define SDMA_DESC_DFLT (SDMA_DESC_CMDSTAT_O | \ 240 SDMA_DESC_CMDSTAT_EI) 241 242#define SDMA_SDC_RFT (1<<0) 243#define SDMA_SDC_SFM (1<<1) 244#define SDMA_SDC_BLMR (1<<6) 245#define SDMA_SDC_BLMT (1<<7) 246#define SDMA_SDC_POVR (1<<8) 247#define SDMA_SDC_RIFB (1<<9) 248 249#define SDMA_SDCM_ERD (1<<7) 250#define SDMA_SDCM_AR (1<<15) 251#define SDMA_SDCM_STD (1<<16) 252#define SDMA_SDCM_TXD (1<<23) 253#define SDMA_SDCM_AT (1<<31) 254 255#define SDMA_0_CAUSE_RXBUF (1<<0) 256#define SDMA_0_CAUSE_RXERR (1<<1) 257#define SDMA_0_CAUSE_TXBUF (1<<2) 258#define SDMA_0_CAUSE_TXEND (1<<3) 259#define SDMA_1_CAUSE_RXBUF (1<<8) 260#define SDMA_1_CAUSE_RXERR (1<<9) 261#define SDMA_1_CAUSE_TXBUF (1<<10) 262#define SDMA_1_CAUSE_TXEND (1<<11) 263 264#define SDMA_CAUSE_RX_MASK (SDMA_0_CAUSE_RXBUF | SDMA_0_CAUSE_RXERR | \ 265 SDMA_1_CAUSE_RXBUF | SDMA_1_CAUSE_RXERR) 266#define SDMA_CAUSE_TX_MASK (SDMA_0_CAUSE_TXBUF | SDMA_0_CAUSE_TXEND | \ 267 SDMA_1_CAUSE_TXBUF | SDMA_1_CAUSE_TXEND) 268 269/* SDMA Interrupt registers */ 270#define SDMA_INTR_CAUSE 0x0000 271#define SDMA_INTR_MASK 0x0080 272 273/* Baud Rate Generator Interface Registers */ 274#define BRG_BCR 0x0000 275#define BRG_BTR 0x0004 276 277/* 278 * Define how this driver is known to the outside (we've been assigned a 279 * range on the "Low-density serial ports" major). 280 */ 281#define MPSC_MAJOR 204 282#define MPSC_MINOR_START 44 283#define MPSC_DRIVER_NAME "MPSC" 284#define MPSC_DEV_NAME "ttyMM" 285#define MPSC_VERSION "1.00" 286 287static struct mpsc_port_info mpsc_ports[MPSC_NUM_CTLRS]; 288static struct mpsc_shared_regs mpsc_shared_regs; 289static struct uart_driver mpsc_reg; 290 291static void mpsc_start_rx(struct mpsc_port_info *pi); 292static void mpsc_free_ring_mem(struct mpsc_port_info *pi); 293static void mpsc_release_port(struct uart_port *port); 294/* 295 ****************************************************************************** 296 * 297 * Baud Rate Generator Routines (BRG) 298 * 299 ****************************************************************************** 300 */ 301static void 302mpsc_brg_init(struct mpsc_port_info *pi, u32 clk_src) 303{ 304 u32 v; 305 306 v = (pi->mirror_regs) ? pi->BRG_BCR_m : readl(pi->brg_base + BRG_BCR); 307 v = (v & ~(0xf << 18)) | ((clk_src & 0xf) << 18); 308 309 if (pi->brg_can_tune) 310 v &= ~(1 << 25); 311 312 if (pi->mirror_regs) 313 pi->BRG_BCR_m = v; 314 writel(v, pi->brg_base + BRG_BCR); 315 316 writel(readl(pi->brg_base + BRG_BTR) & 0xffff0000, 317 pi->brg_base + BRG_BTR); 318 return; 319} 320 321static void 322mpsc_brg_enable(struct mpsc_port_info *pi) 323{ 324 u32 v; 325 326 v = (pi->mirror_regs) ? pi->BRG_BCR_m : readl(pi->brg_base + BRG_BCR); 327 v |= (1 << 16); 328 329 if (pi->mirror_regs) 330 pi->BRG_BCR_m = v; 331 writel(v, pi->brg_base + BRG_BCR); 332 return; 333} 334 335static void 336mpsc_brg_disable(struct mpsc_port_info *pi) 337{ 338 u32 v; 339 340 v = (pi->mirror_regs) ? pi->BRG_BCR_m : readl(pi->brg_base + BRG_BCR); 341 v &= ~(1 << 16); 342 343 if (pi->mirror_regs) 344 pi->BRG_BCR_m = v; 345 writel(v, pi->brg_base + BRG_BCR); 346 return; 347} 348 349static inline void 350mpsc_set_baudrate(struct mpsc_port_info *pi, u32 baud) 351{ 352 /* 353 * To set the baud, we adjust the CDV field in the BRG_BCR reg. 354 * From manual: Baud = clk / ((CDV+1)*2) ==> CDV = (clk / (baud*2)) - 1. 355 * However, the input clock is divided by 16 in the MPSC b/c of how 356 * 'MPSC_MMCRH' was set up so we have to divide the 'clk' used in our 357 * calculation by 16 to account for that. So the real calculation 358 * that accounts for the way the mpsc is set up is: 359 * CDV = (clk / (baud*2*16)) - 1 ==> CDV = (clk / (baud << 5)) - 1. 360 */ 361 u32 cdv = (pi->port.uartclk / (baud << 5)) - 1; 362 u32 v; 363 364 mpsc_brg_disable(pi); 365 v = (pi->mirror_regs) ? pi->BRG_BCR_m : readl(pi->brg_base + BRG_BCR); 366 v = (v & 0xffff0000) | (cdv & 0xffff); 367 368 if (pi->mirror_regs) 369 pi->BRG_BCR_m = v; 370 writel(v, pi->brg_base + BRG_BCR); 371 mpsc_brg_enable(pi); 372 373 return; 374} 375 376/* 377 ****************************************************************************** 378 * 379 * Serial DMA Routines (SDMA) 380 * 381 ****************************************************************************** 382 */ 383 384static void 385mpsc_sdma_burstsize(struct mpsc_port_info *pi, u32 burst_size) 386{ 387 u32 v; 388 389 pr_debug("mpsc_sdma_burstsize[%d]: burst_size: %d\n", 390 pi->port.line, burst_size); 391 392 burst_size >>= 3; /* Divide by 8 b/c reg values are 8-byte chunks */ 393 394 if (burst_size < 2) 395 v = 0x0; /* 1 64-bit word */ 396 else if (burst_size < 4) 397 v = 0x1; /* 2 64-bit words */ 398 else if (burst_size < 8) 399 v = 0x2; /* 4 64-bit words */ 400 else 401 v = 0x3; /* 8 64-bit words */ 402 403 writel((readl(pi->sdma_base + SDMA_SDC) & (0x3 << 12)) | (v << 12), 404 pi->sdma_base + SDMA_SDC); 405 return; 406} 407 408static void 409mpsc_sdma_init(struct mpsc_port_info *pi, u32 burst_size) 410{ 411 pr_debug("mpsc_sdma_init[%d]: burst_size: %d\n", pi->port.line, 412 burst_size); 413 414 writel((readl(pi->sdma_base + SDMA_SDC) & 0x3ff) | 0x03f, 415 pi->sdma_base + SDMA_SDC); 416 mpsc_sdma_burstsize(pi, burst_size); 417 return; 418} 419 420static inline u32 421mpsc_sdma_intr_mask(struct mpsc_port_info *pi, u32 mask) 422{ 423 u32 old, v; 424 425 pr_debug("mpsc_sdma_intr_mask[%d]: mask: 0x%x\n", pi->port.line, mask); 426 427 old = v = (pi->mirror_regs) ? pi->shared_regs->SDMA_INTR_MASK_m : 428 readl(pi->shared_regs->sdma_intr_base + SDMA_INTR_MASK); 429 430 mask &= 0xf; 431 if (pi->port.line) 432 mask <<= 8; 433 v &= ~mask; 434 435 if (pi->mirror_regs) 436 pi->shared_regs->SDMA_INTR_MASK_m = v; 437 writel(v, pi->shared_regs->sdma_intr_base + SDMA_INTR_MASK); 438 439 if (pi->port.line) 440 old >>= 8; 441 return old & 0xf; 442} 443 444static inline void 445mpsc_sdma_intr_unmask(struct mpsc_port_info *pi, u32 mask) 446{ 447 u32 v; 448 449 pr_debug("mpsc_sdma_intr_unmask[%d]: mask: 0x%x\n", pi->port.line,mask); 450 451 v = (pi->mirror_regs) ? pi->shared_regs->SDMA_INTR_MASK_m : 452 readl(pi->shared_regs->sdma_intr_base + SDMA_INTR_MASK); 453 454 mask &= 0xf; 455 if (pi->port.line) 456 mask <<= 8; 457 v |= mask; 458 459 if (pi->mirror_regs) 460 pi->shared_regs->SDMA_INTR_MASK_m = v; 461 writel(v, pi->shared_regs->sdma_intr_base + SDMA_INTR_MASK); 462 return; 463} 464 465static inline void 466mpsc_sdma_intr_ack(struct mpsc_port_info *pi) 467{ 468 pr_debug("mpsc_sdma_intr_ack[%d]: Acknowledging IRQ\n", pi->port.line); 469 470 if (pi->mirror_regs) 471 pi->shared_regs->SDMA_INTR_CAUSE_m = 0; 472 writeb(0x00, pi->shared_regs->sdma_intr_base + SDMA_INTR_CAUSE + 473 pi->port.line); 474 return; 475} 476 477static inline void 478mpsc_sdma_set_rx_ring(struct mpsc_port_info *pi, struct mpsc_rx_desc *rxre_p) 479{ 480 pr_debug("mpsc_sdma_set_rx_ring[%d]: rxre_p: 0x%x\n", 481 pi->port.line, (u32) rxre_p); 482 483 writel((u32)rxre_p, pi->sdma_base + SDMA_SCRDP); 484 return; 485} 486 487static inline void 488mpsc_sdma_set_tx_ring(struct mpsc_port_info *pi, struct mpsc_tx_desc *txre_p) 489{ 490 writel((u32)txre_p, pi->sdma_base + SDMA_SFTDP); 491 writel((u32)txre_p, pi->sdma_base + SDMA_SCTDP); 492 return; 493} 494 495static inline void 496mpsc_sdma_cmd(struct mpsc_port_info *pi, u32 val) 497{ 498 u32 v; 499 500 v = readl(pi->sdma_base + SDMA_SDCM); 501 if (val) 502 v |= val; 503 else 504 v = 0; 505 wmb(); 506 writel(v, pi->sdma_base + SDMA_SDCM); 507 wmb(); 508 return; 509} 510 511static inline uint 512mpsc_sdma_tx_active(struct mpsc_port_info *pi) 513{ 514 return readl(pi->sdma_base + SDMA_SDCM) & SDMA_SDCM_TXD; 515} 516 517static inline void 518mpsc_sdma_start_tx(struct mpsc_port_info *pi) 519{ 520 struct mpsc_tx_desc *txre, *txre_p; 521 522 /* If tx isn't running & there's a desc ready to go, start it */ 523 if (!mpsc_sdma_tx_active(pi)) { 524 txre = (struct mpsc_tx_desc *)(pi->txr + 525 (pi->txr_tail * MPSC_TXRE_SIZE)); 526 dma_cache_sync(pi->port.dev, (void *) txre, MPSC_TXRE_SIZE, DMA_FROM_DEVICE); 527#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE) 528 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */ 529 invalidate_dcache_range((ulong)txre, 530 (ulong)txre + MPSC_TXRE_SIZE); 531#endif 532 533 if (be32_to_cpu(txre->cmdstat) & SDMA_DESC_CMDSTAT_O) { 534 txre_p = (struct mpsc_tx_desc *)(pi->txr_p + 535 (pi->txr_tail * 536 MPSC_TXRE_SIZE)); 537 538 mpsc_sdma_set_tx_ring(pi, txre_p); 539 mpsc_sdma_cmd(pi, SDMA_SDCM_STD | SDMA_SDCM_TXD); 540 } 541 } 542 543 return; 544} 545 546static inline void 547mpsc_sdma_stop(struct mpsc_port_info *pi) 548{ 549 pr_debug("mpsc_sdma_stop[%d]: Stopping SDMA\n", pi->port.line); 550 551 /* Abort any SDMA transfers */ 552 mpsc_sdma_cmd(pi, 0); 553 mpsc_sdma_cmd(pi, SDMA_SDCM_AR | SDMA_SDCM_AT); 554 555 /* Clear the SDMA current and first TX and RX pointers */ 556 mpsc_sdma_set_tx_ring(pi, NULL); 557 mpsc_sdma_set_rx_ring(pi, NULL); 558 559 /* Disable interrupts */ 560 mpsc_sdma_intr_mask(pi, 0xf); 561 mpsc_sdma_intr_ack(pi); 562 563 return; 564} 565 566/* 567 ****************************************************************************** 568 * 569 * Multi-Protocol Serial Controller Routines (MPSC) 570 * 571 ****************************************************************************** 572 */ 573 574static void 575mpsc_hw_init(struct mpsc_port_info *pi) 576{ 577 u32 v; 578 579 pr_debug("mpsc_hw_init[%d]: Initializing hardware\n", pi->port.line); 580 581 /* Set up clock routing */ 582 if (pi->mirror_regs) { 583 v = pi->shared_regs->MPSC_MRR_m; 584 v &= ~0x1c7; 585 pi->shared_regs->MPSC_MRR_m = v; 586 writel(v, pi->shared_regs->mpsc_routing_base + MPSC_MRR); 587 588 v = pi->shared_regs->MPSC_RCRR_m; 589 v = (v & ~0xf0f) | 0x100; 590 pi->shared_regs->MPSC_RCRR_m = v; 591 writel(v, pi->shared_regs->mpsc_routing_base + MPSC_RCRR); 592 593 v = pi->shared_regs->MPSC_TCRR_m; 594 v = (v & ~0xf0f) | 0x100; 595 pi->shared_regs->MPSC_TCRR_m = v; 596 writel(v, pi->shared_regs->mpsc_routing_base + MPSC_TCRR); 597 } 598 else { 599 v = readl(pi->shared_regs->mpsc_routing_base + MPSC_MRR); 600 v &= ~0x1c7; 601 writel(v, pi->shared_regs->mpsc_routing_base + MPSC_MRR); 602 603 v = readl(pi->shared_regs->mpsc_routing_base + MPSC_RCRR); 604 v = (v & ~0xf0f) | 0x100; 605 writel(v, pi->shared_regs->mpsc_routing_base + MPSC_RCRR); 606 607 v = readl(pi->shared_regs->mpsc_routing_base + MPSC_TCRR); 608 v = (v & ~0xf0f) | 0x100; 609 writel(v, pi->shared_regs->mpsc_routing_base + MPSC_TCRR); 610 } 611 612 /* Put MPSC in UART mode & enabel Tx/Rx egines */ 613 writel(0x000004c4, pi->mpsc_base + MPSC_MMCRL); 614 615 /* No preamble, 16x divider, low-latency, */ 616 writel(0x04400400, pi->mpsc_base + MPSC_MMCRH); 617 618 if (pi->mirror_regs) { 619 pi->MPSC_CHR_1_m = 0; 620 pi->MPSC_CHR_2_m = 0; 621 } 622 writel(0, pi->mpsc_base + MPSC_CHR_1); 623 writel(0, pi->mpsc_base + MPSC_CHR_2); 624 writel(pi->mpsc_max_idle, pi->mpsc_base + MPSC_CHR_3); 625 writel(0, pi->mpsc_base + MPSC_CHR_4); 626 writel(0, pi->mpsc_base + MPSC_CHR_5); 627 writel(0, pi->mpsc_base + MPSC_CHR_6); 628 writel(0, pi->mpsc_base + MPSC_CHR_7); 629 writel(0, pi->mpsc_base + MPSC_CHR_8); 630 writel(0, pi->mpsc_base + MPSC_CHR_9); 631 writel(0, pi->mpsc_base + MPSC_CHR_10); 632 633 return; 634} 635 636static inline void 637mpsc_enter_hunt(struct mpsc_port_info *pi) 638{ 639 pr_debug("mpsc_enter_hunt[%d]: Hunting...\n", pi->port.line); 640 641 if (pi->mirror_regs) { 642 writel(pi->MPSC_CHR_2_m | MPSC_CHR_2_EH, 643 pi->mpsc_base + MPSC_CHR_2); 644 /* Erratum prevents reading CHR_2 so just delay for a while */ 645 udelay(100); 646 } 647 else { 648 writel(readl(pi->mpsc_base + MPSC_CHR_2) | MPSC_CHR_2_EH, 649 pi->mpsc_base + MPSC_CHR_2); 650 651 while (readl(pi->mpsc_base + MPSC_CHR_2) & MPSC_CHR_2_EH) 652 udelay(10); 653 } 654 655 return; 656} 657 658static inline void 659mpsc_freeze(struct mpsc_port_info *pi) 660{ 661 u32 v; 662 663 pr_debug("mpsc_freeze[%d]: Freezing\n", pi->port.line); 664 665 v = (pi->mirror_regs) ? pi->MPSC_MPCR_m : 666 readl(pi->mpsc_base + MPSC_MPCR); 667 v |= MPSC_MPCR_FRZ; 668 669 if (pi->mirror_regs) 670 pi->MPSC_MPCR_m = v; 671 writel(v, pi->mpsc_base + MPSC_MPCR); 672 return; 673} 674 675static inline void 676mpsc_unfreeze(struct mpsc_port_info *pi) 677{ 678 u32 v; 679 680 v = (pi->mirror_regs) ? pi->MPSC_MPCR_m : 681 readl(pi->mpsc_base + MPSC_MPCR); 682 v &= ~MPSC_MPCR_FRZ; 683 684 if (pi->mirror_regs) 685 pi->MPSC_MPCR_m = v; 686 writel(v, pi->mpsc_base + MPSC_MPCR); 687 688 pr_debug("mpsc_unfreeze[%d]: Unfrozen\n", pi->port.line); 689 return; 690} 691 692static inline void 693mpsc_set_char_length(struct mpsc_port_info *pi, u32 len) 694{ 695 u32 v; 696 697 pr_debug("mpsc_set_char_length[%d]: char len: %d\n", pi->port.line,len); 698 699 v = (pi->mirror_regs) ? pi->MPSC_MPCR_m : 700 readl(pi->mpsc_base + MPSC_MPCR); 701 v = (v & ~(0x3 << 12)) | ((len & 0x3) << 12); 702 703 if (pi->mirror_regs) 704 pi->MPSC_MPCR_m = v; 705 writel(v, pi->mpsc_base + MPSC_MPCR); 706 return; 707} 708 709static inline void 710mpsc_set_stop_bit_length(struct mpsc_port_info *pi, u32 len) 711{ 712 u32 v; 713 714 pr_debug("mpsc_set_stop_bit_length[%d]: stop bits: %d\n", 715 pi->port.line, len); 716 717 v = (pi->mirror_regs) ? pi->MPSC_MPCR_m : 718 readl(pi->mpsc_base + MPSC_MPCR); 719 720 v = (v & ~(1 << 14)) | ((len & 0x1) << 14); 721 722 if (pi->mirror_regs) 723 pi->MPSC_MPCR_m = v; 724 writel(v, pi->mpsc_base + MPSC_MPCR); 725 return; 726} 727 728static inline void 729mpsc_set_parity(struct mpsc_port_info *pi, u32 p) 730{ 731 u32 v; 732 733 pr_debug("mpsc_set_parity[%d]: parity bits: 0x%x\n", pi->port.line, p); 734 735 v = (pi->mirror_regs) ? pi->MPSC_CHR_2_m : 736 readl(pi->mpsc_base + MPSC_CHR_2); 737 738 p &= 0x3; 739 v = (v & ~0xc000c) | (p << 18) | (p << 2); 740 741 if (pi->mirror_regs) 742 pi->MPSC_CHR_2_m = v; 743 writel(v, pi->mpsc_base + MPSC_CHR_2); 744 return; 745} 746 747/* 748 ****************************************************************************** 749 * 750 * Driver Init Routines 751 * 752 ****************************************************************************** 753 */ 754 755static void 756mpsc_init_hw(struct mpsc_port_info *pi) 757{ 758 pr_debug("mpsc_init_hw[%d]: Initializing\n", pi->port.line); 759 760 mpsc_brg_init(pi, pi->brg_clk_src); 761 mpsc_brg_enable(pi); 762 mpsc_sdma_init(pi, dma_get_cache_alignment()); /* burst a cacheline */ 763 mpsc_sdma_stop(pi); 764 mpsc_hw_init(pi); 765 766 return; 767} 768 769static int 770mpsc_alloc_ring_mem(struct mpsc_port_info *pi) 771{ 772 int rc = 0; 773 774 pr_debug("mpsc_alloc_ring_mem[%d]: Allocating ring mem\n", 775 pi->port.line); 776 777 if (!pi->dma_region) { 778 if (!dma_supported(pi->port.dev, 0xffffffff)) { 779 printk(KERN_ERR "MPSC: Inadequate DMA support\n"); 780 rc = -ENXIO; 781 } 782 else if ((pi->dma_region = dma_alloc_noncoherent(pi->port.dev, 783 MPSC_DMA_ALLOC_SIZE, &pi->dma_region_p, GFP_KERNEL)) 784 == NULL) { 785 786 printk(KERN_ERR "MPSC: Can't alloc Desc region\n"); 787 rc = -ENOMEM; 788 } 789 } 790 791 return rc; 792} 793 794static void 795mpsc_free_ring_mem(struct mpsc_port_info *pi) 796{ 797 pr_debug("mpsc_free_ring_mem[%d]: Freeing ring mem\n", pi->port.line); 798 799 if (pi->dma_region) { 800 dma_free_noncoherent(pi->port.dev, MPSC_DMA_ALLOC_SIZE, 801 pi->dma_region, pi->dma_region_p); 802 pi->dma_region = NULL; 803 pi->dma_region_p = (dma_addr_t) NULL; 804 } 805 806 return; 807} 808 809static void 810mpsc_init_rings(struct mpsc_port_info *pi) 811{ 812 struct mpsc_rx_desc *rxre; 813 struct mpsc_tx_desc *txre; 814 dma_addr_t dp, dp_p; 815 u8 *bp, *bp_p; 816 int i; 817 818 pr_debug("mpsc_init_rings[%d]: Initializing rings\n", pi->port.line); 819 820 BUG_ON(pi->dma_region == NULL); 821 822 memset(pi->dma_region, 0, MPSC_DMA_ALLOC_SIZE); 823 824 /* 825 * Descriptors & buffers are multiples of cacheline size and must be 826 * cacheline aligned. 827 */ 828 dp = ALIGN((u32) pi->dma_region, dma_get_cache_alignment()); 829 dp_p = ALIGN((u32) pi->dma_region_p, dma_get_cache_alignment()); 830 831 /* 832 * Partition dma region into rx ring descriptor, rx buffers, 833 * tx ring descriptors, and tx buffers. 834 */ 835 pi->rxr = dp; 836 pi->rxr_p = dp_p; 837 dp += MPSC_RXR_SIZE; 838 dp_p += MPSC_RXR_SIZE; 839 840 pi->rxb = (u8 *) dp; 841 pi->rxb_p = (u8 *) dp_p; 842 dp += MPSC_RXB_SIZE; 843 dp_p += MPSC_RXB_SIZE; 844 845 pi->rxr_posn = 0; 846 847 pi->txr = dp; 848 pi->txr_p = dp_p; 849 dp += MPSC_TXR_SIZE; 850 dp_p += MPSC_TXR_SIZE; 851 852 pi->txb = (u8 *) dp; 853 pi->txb_p = (u8 *) dp_p; 854 855 pi->txr_head = 0; 856 pi->txr_tail = 0; 857 858 /* Init rx ring descriptors */ 859 dp = pi->rxr; 860 dp_p = pi->rxr_p; 861 bp = pi->rxb; 862 bp_p = pi->rxb_p; 863 864 for (i = 0; i < MPSC_RXR_ENTRIES; i++) { 865 rxre = (struct mpsc_rx_desc *)dp; 866 867 rxre->bufsize = cpu_to_be16(MPSC_RXBE_SIZE); 868 rxre->bytecnt = cpu_to_be16(0); 869 rxre->cmdstat = cpu_to_be32(SDMA_DESC_CMDSTAT_O | 870 SDMA_DESC_CMDSTAT_EI | 871 SDMA_DESC_CMDSTAT_F | 872 SDMA_DESC_CMDSTAT_L); 873 rxre->link = cpu_to_be32(dp_p + MPSC_RXRE_SIZE); 874 rxre->buf_ptr = cpu_to_be32(bp_p); 875 876 dp += MPSC_RXRE_SIZE; 877 dp_p += MPSC_RXRE_SIZE; 878 bp += MPSC_RXBE_SIZE; 879 bp_p += MPSC_RXBE_SIZE; 880 } 881 rxre->link = cpu_to_be32(pi->rxr_p); /* Wrap last back to first */ 882 883 /* Init tx ring descriptors */ 884 dp = pi->txr; 885 dp_p = pi->txr_p; 886 bp = pi->txb; 887 bp_p = pi->txb_p; 888 889 for (i = 0; i < MPSC_TXR_ENTRIES; i++) { 890 txre = (struct mpsc_tx_desc *)dp; 891 892 txre->link = cpu_to_be32(dp_p + MPSC_TXRE_SIZE); 893 txre->buf_ptr = cpu_to_be32(bp_p); 894 895 dp += MPSC_TXRE_SIZE; 896 dp_p += MPSC_TXRE_SIZE; 897 bp += MPSC_TXBE_SIZE; 898 bp_p += MPSC_TXBE_SIZE; 899 } 900 txre->link = cpu_to_be32(pi->txr_p); /* Wrap last back to first */ 901 902 dma_cache_sync(pi->port.dev, (void *) pi->dma_region, MPSC_DMA_ALLOC_SIZE, 903 DMA_BIDIRECTIONAL); 904#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE) 905 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */ 906 flush_dcache_range((ulong)pi->dma_region, 907 (ulong)pi->dma_region + MPSC_DMA_ALLOC_SIZE); 908#endif 909 910 return; 911} 912 913static void 914mpsc_uninit_rings(struct mpsc_port_info *pi) 915{ 916 pr_debug("mpsc_uninit_rings[%d]: Uninitializing rings\n",pi->port.line); 917 918 BUG_ON(pi->dma_region == NULL); 919 920 pi->rxr = 0; 921 pi->rxr_p = 0; 922 pi->rxb = NULL; 923 pi->rxb_p = NULL; 924 pi->rxr_posn = 0; 925 926 pi->txr = 0; 927 pi->txr_p = 0; 928 pi->txb = NULL; 929 pi->txb_p = NULL; 930 pi->txr_head = 0; 931 pi->txr_tail = 0; 932 933 return; 934} 935 936static int 937mpsc_make_ready(struct mpsc_port_info *pi) 938{ 939 int rc; 940 941 pr_debug("mpsc_make_ready[%d]: Making cltr ready\n", pi->port.line); 942 943 if (!pi->ready) { 944 mpsc_init_hw(pi); 945 if ((rc = mpsc_alloc_ring_mem(pi))) 946 return rc; 947 mpsc_init_rings(pi); 948 pi->ready = 1; 949 } 950 951 return 0; 952} 953 954/* 955 ****************************************************************************** 956 * 957 * Interrupt Handling Routines 958 * 959 ****************************************************************************** 960 */ 961 962static inline int 963mpsc_rx_intr(struct mpsc_port_info *pi) 964{ 965 struct mpsc_rx_desc *rxre; 966 struct tty_struct *tty = pi->port.info->tty; 967 u32 cmdstat, bytes_in, i; 968 int rc = 0; 969 u8 *bp; 970 char flag = TTY_NORMAL; 971 972 pr_debug("mpsc_rx_intr[%d]: Handling Rx intr\n", pi->port.line); 973 974 rxre = (struct mpsc_rx_desc *)(pi->rxr + (pi->rxr_posn*MPSC_RXRE_SIZE)); 975 976 dma_cache_sync(pi->port.dev, (void *)rxre, MPSC_RXRE_SIZE, DMA_FROM_DEVICE); 977#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE) 978 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */ 979 invalidate_dcache_range((ulong)rxre, 980 (ulong)rxre + MPSC_RXRE_SIZE); 981#endif 982 983 /* 984 * Loop through Rx descriptors handling ones that have been completed. 985 */ 986 while (!((cmdstat = be32_to_cpu(rxre->cmdstat)) & SDMA_DESC_CMDSTAT_O)){ 987 bytes_in = be16_to_cpu(rxre->bytecnt); 988 989 /* Following use of tty struct directly is deprecated */ 990 if (unlikely(tty_buffer_request_room(tty, bytes_in) < bytes_in)) { 991 if (tty->low_latency) 992 tty_flip_buffer_push(tty); 993 /* 994 * If this failed then we will throw away the bytes 995 * but must do so to clear interrupts. 996 */ 997 } 998 999 bp = pi->rxb + (pi->rxr_posn * MPSC_RXBE_SIZE); 1000 dma_cache_sync(pi->port.dev, (void *) bp, MPSC_RXBE_SIZE, DMA_FROM_DEVICE); 1001#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE) 1002 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */ 1003 invalidate_dcache_range((ulong)bp, 1004 (ulong)bp + MPSC_RXBE_SIZE); 1005#endif 1006 1007 /* 1008 * Other than for parity error, the manual provides little 1009 * info on what data will be in a frame flagged by any of 1010 * these errors. For parity error, it is the last byte in 1011 * the buffer that had the error. As for the rest, I guess 1012 * we'll assume there is no data in the buffer. 1013 * If there is...it gets lost. 1014 */ 1015 if (unlikely(cmdstat & (SDMA_DESC_CMDSTAT_BR | 1016 SDMA_DESC_CMDSTAT_FR | SDMA_DESC_CMDSTAT_OR))) { 1017 1018 pi->port.icount.rx++; 1019 1020 if (cmdstat & SDMA_DESC_CMDSTAT_BR) { /* Break */ 1021 pi->port.icount.brk++; 1022 1023 if (uart_handle_break(&pi->port)) 1024 goto next_frame; 1025 } 1026 else if (cmdstat & SDMA_DESC_CMDSTAT_FR)/* Framing */ 1027 pi->port.icount.frame++; 1028 else if (cmdstat & SDMA_DESC_CMDSTAT_OR) /* Overrun */ 1029 pi->port.icount.overrun++; 1030 1031 cmdstat &= pi->port.read_status_mask; 1032 1033 if (cmdstat & SDMA_DESC_CMDSTAT_BR) 1034 flag = TTY_BREAK; 1035 else if (cmdstat & SDMA_DESC_CMDSTAT_FR) 1036 flag = TTY_FRAME; 1037 else if (cmdstat & SDMA_DESC_CMDSTAT_OR) 1038 flag = TTY_OVERRUN; 1039 else if (cmdstat & SDMA_DESC_CMDSTAT_PE) 1040 flag = TTY_PARITY; 1041 } 1042 1043 if (uart_handle_sysrq_char(&pi->port, *bp)) { 1044 bp++; 1045 bytes_in--; 1046 goto next_frame; 1047 } 1048 1049 if ((unlikely(cmdstat & (SDMA_DESC_CMDSTAT_BR | 1050 SDMA_DESC_CMDSTAT_FR | SDMA_DESC_CMDSTAT_OR))) && 1051 !(cmdstat & pi->port.ignore_status_mask)) 1052 1053 tty_insert_flip_char(tty, *bp, flag); 1054 else { 1055 for (i=0; i<bytes_in; i++) 1056 tty_insert_flip_char(tty, *bp++, TTY_NORMAL); 1057 1058 pi->port.icount.rx += bytes_in; 1059 } 1060 1061next_frame: 1062 rxre->bytecnt = cpu_to_be16(0); 1063 wmb(); 1064 rxre->cmdstat = cpu_to_be32(SDMA_DESC_CMDSTAT_O | 1065 SDMA_DESC_CMDSTAT_EI | 1066 SDMA_DESC_CMDSTAT_F | 1067 SDMA_DESC_CMDSTAT_L); 1068 wmb(); 1069 dma_cache_sync(pi->port.dev, (void *)rxre, MPSC_RXRE_SIZE, DMA_BIDIRECTIONAL); 1070#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE) 1071 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */ 1072 flush_dcache_range((ulong)rxre, 1073 (ulong)rxre + MPSC_RXRE_SIZE); 1074#endif 1075 1076 /* Advance to next descriptor */ 1077 pi->rxr_posn = (pi->rxr_posn + 1) & (MPSC_RXR_ENTRIES - 1); 1078 rxre = (struct mpsc_rx_desc *)(pi->rxr + 1079 (pi->rxr_posn * MPSC_RXRE_SIZE)); 1080 dma_cache_sync(pi->port.dev, (void *)rxre, MPSC_RXRE_SIZE, DMA_FROM_DEVICE); 1081#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE) 1082 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */ 1083 invalidate_dcache_range((ulong)rxre, 1084 (ulong)rxre + MPSC_RXRE_SIZE); 1085#endif 1086 1087 rc = 1; 1088 } 1089 1090 /* Restart rx engine, if its stopped */ 1091 if ((readl(pi->sdma_base + SDMA_SDCM) & SDMA_SDCM_ERD) == 0) 1092 mpsc_start_rx(pi); 1093 1094 tty_flip_buffer_push(tty); 1095 return rc; 1096} 1097 1098static inline void 1099mpsc_setup_tx_desc(struct mpsc_port_info *pi, u32 count, u32 intr) 1100{ 1101 struct mpsc_tx_desc *txre; 1102 1103 txre = (struct mpsc_tx_desc *)(pi->txr + 1104 (pi->txr_head * MPSC_TXRE_SIZE)); 1105 1106 txre->bytecnt = cpu_to_be16(count); 1107 txre->shadow = txre->bytecnt; 1108 wmb(); /* ensure cmdstat is last field updated */ 1109 txre->cmdstat = cpu_to_be32(SDMA_DESC_CMDSTAT_O | SDMA_DESC_CMDSTAT_F | 1110 SDMA_DESC_CMDSTAT_L | ((intr) ? 1111 SDMA_DESC_CMDSTAT_EI 1112 : 0)); 1113 wmb(); 1114 dma_cache_sync(pi->port.dev, (void *) txre, MPSC_TXRE_SIZE, DMA_BIDIRECTIONAL); 1115#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE) 1116 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */ 1117 flush_dcache_range((ulong)txre, 1118 (ulong)txre + MPSC_TXRE_SIZE); 1119#endif 1120 1121 return; 1122} 1123 1124static inline void 1125mpsc_copy_tx_data(struct mpsc_port_info *pi) 1126{ 1127 struct circ_buf *xmit = &pi->port.info->xmit; 1128 u8 *bp; 1129 u32 i; 1130 1131 /* Make sure the desc ring isn't full */ 1132 while (CIRC_CNT(pi->txr_head, pi->txr_tail, MPSC_TXR_ENTRIES) < 1133 (MPSC_TXR_ENTRIES - 1)) { 1134 if (pi->port.x_char) { 1135 /* 1136 * Ideally, we should use the TCS field in 1137 * CHR_1 to put the x_char out immediately but 1138 * errata prevents us from being able to read 1139 * CHR_2 to know that its safe to write to 1140 * CHR_1. Instead, just put it in-band with 1141 * all the other Tx data. 1142 */ 1143 bp = pi->txb + (pi->txr_head * MPSC_TXBE_SIZE); 1144 *bp = pi->port.x_char; 1145 pi->port.x_char = 0; 1146 i = 1; 1147 } 1148 else if (!uart_circ_empty(xmit) && !uart_tx_stopped(&pi->port)){ 1149 i = min((u32) MPSC_TXBE_SIZE, 1150 (u32) uart_circ_chars_pending(xmit)); 1151 i = min(i, (u32) CIRC_CNT_TO_END(xmit->head, xmit->tail, 1152 UART_XMIT_SIZE)); 1153 bp = pi->txb + (pi->txr_head * MPSC_TXBE_SIZE); 1154 memcpy(bp, &xmit->buf[xmit->tail], i); 1155 xmit->tail = (xmit->tail + i) & (UART_XMIT_SIZE - 1); 1156 1157 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 1158 uart_write_wakeup(&pi->port); 1159 } 1160 else /* All tx data copied into ring bufs */ 1161 return; 1162 1163 dma_cache_sync(pi->port.dev, (void *) bp, MPSC_TXBE_SIZE, DMA_BIDIRECTIONAL); 1164#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE) 1165 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */ 1166 flush_dcache_range((ulong)bp, 1167 (ulong)bp + MPSC_TXBE_SIZE); 1168#endif 1169 mpsc_setup_tx_desc(pi, i, 1); 1170 1171 /* Advance to next descriptor */ 1172 pi->txr_head = (pi->txr_head + 1) & (MPSC_TXR_ENTRIES - 1); 1173 } 1174 1175 return; 1176} 1177 1178static inline int 1179mpsc_tx_intr(struct mpsc_port_info *pi) 1180{ 1181 struct mpsc_tx_desc *txre; 1182 int rc = 0; 1183 unsigned long iflags; 1184 1185 spin_lock_irqsave(&pi->tx_lock, iflags); 1186 1187 if (!mpsc_sdma_tx_active(pi)) { 1188 txre = (struct mpsc_tx_desc *)(pi->txr + 1189 (pi->txr_tail * MPSC_TXRE_SIZE)); 1190 1191 dma_cache_sync(pi->port.dev, (void *) txre, MPSC_TXRE_SIZE, DMA_FROM_DEVICE); 1192#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE) 1193 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */ 1194 invalidate_dcache_range((ulong)txre, 1195 (ulong)txre + MPSC_TXRE_SIZE); 1196#endif 1197 1198 while (!(be32_to_cpu(txre->cmdstat) & SDMA_DESC_CMDSTAT_O)) { 1199 rc = 1; 1200 pi->port.icount.tx += be16_to_cpu(txre->bytecnt); 1201 pi->txr_tail = (pi->txr_tail+1) & (MPSC_TXR_ENTRIES-1); 1202 1203 /* If no more data to tx, fall out of loop */ 1204 if (pi->txr_head == pi->txr_tail) 1205 break; 1206 1207 txre = (struct mpsc_tx_desc *)(pi->txr + 1208 (pi->txr_tail * MPSC_TXRE_SIZE)); 1209 dma_cache_sync(pi->port.dev, (void *) txre, MPSC_TXRE_SIZE, 1210 DMA_FROM_DEVICE); 1211#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE) 1212 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */ 1213 invalidate_dcache_range((ulong)txre, 1214 (ulong)txre + MPSC_TXRE_SIZE); 1215#endif 1216 } 1217 1218 mpsc_copy_tx_data(pi); 1219 mpsc_sdma_start_tx(pi); /* start next desc if ready */ 1220 } 1221 1222 spin_unlock_irqrestore(&pi->tx_lock, iflags); 1223 return rc; 1224} 1225 1226/* 1227 * This is the driver's interrupt handler. To avoid a race, we first clear 1228 * the interrupt, then handle any completed Rx/Tx descriptors. When done 1229 * handling those descriptors, we restart the Rx/Tx engines if they're stopped. 1230 */ 1231static irqreturn_t 1232mpsc_sdma_intr(int irq, void *dev_id) 1233{ 1234 struct mpsc_port_info *pi = dev_id; 1235 ulong iflags; 1236 int rc = IRQ_NONE; 1237 1238 pr_debug("mpsc_sdma_intr[%d]: SDMA Interrupt Received\n",pi->port.line); 1239 1240 spin_lock_irqsave(&pi->port.lock, iflags); 1241 mpsc_sdma_intr_ack(pi); 1242 if (mpsc_rx_intr(pi)) 1243 rc = IRQ_HANDLED; 1244 if (mpsc_tx_intr(pi)) 1245 rc = IRQ_HANDLED; 1246 spin_unlock_irqrestore(&pi->port.lock, iflags); 1247 1248 pr_debug("mpsc_sdma_intr[%d]: SDMA Interrupt Handled\n", pi->port.line); 1249 return rc; 1250} 1251 1252/* 1253 ****************************************************************************** 1254 * 1255 * serial_core.c Interface routines 1256 * 1257 ****************************************************************************** 1258 */ 1259static uint 1260mpsc_tx_empty(struct uart_port *port) 1261{ 1262 struct mpsc_port_info *pi = (struct mpsc_port_info *)port; 1263 ulong iflags; 1264 uint rc; 1265 1266 spin_lock_irqsave(&pi->port.lock, iflags); 1267 rc = mpsc_sdma_tx_active(pi) ? 0 : TIOCSER_TEMT; 1268 spin_unlock_irqrestore(&pi->port.lock, iflags); 1269 1270 return rc; 1271} 1272 1273static void 1274mpsc_set_mctrl(struct uart_port *port, uint mctrl) 1275{ 1276 /* Have no way to set modem control lines AFAICT */ 1277 return; 1278} 1279 1280static uint 1281mpsc_get_mctrl(struct uart_port *port) 1282{ 1283 struct mpsc_port_info *pi = (struct mpsc_port_info *)port; 1284 u32 mflags, status; 1285 1286 status = (pi->mirror_regs) ? pi->MPSC_CHR_10_m : 1287 readl(pi->mpsc_base + MPSC_CHR_10); 1288 1289 mflags = 0; 1290 if (status & 0x1) 1291 mflags |= TIOCM_CTS; 1292 if (status & 0x2) 1293 mflags |= TIOCM_CAR; 1294 1295 return mflags | TIOCM_DSR; /* No way to tell if DSR asserted */ 1296} 1297 1298static void 1299mpsc_stop_tx(struct uart_port *port) 1300{ 1301 struct mpsc_port_info *pi = (struct mpsc_port_info *)port; 1302 1303 pr_debug("mpsc_stop_tx[%d]\n", port->line); 1304 1305 mpsc_freeze(pi); 1306 return; 1307} 1308 1309static void 1310mpsc_start_tx(struct uart_port *port) 1311{ 1312 struct mpsc_port_info *pi = (struct mpsc_port_info *)port; 1313 unsigned long iflags; 1314 1315 spin_lock_irqsave(&pi->tx_lock, iflags); 1316 1317 mpsc_unfreeze(pi); 1318 mpsc_copy_tx_data(pi); 1319 mpsc_sdma_start_tx(pi); 1320 1321 spin_unlock_irqrestore(&pi->tx_lock, iflags); 1322 1323 pr_debug("mpsc_start_tx[%d]\n", port->line); 1324 return; 1325} 1326 1327static void 1328mpsc_start_rx(struct mpsc_port_info *pi) 1329{ 1330 pr_debug("mpsc_start_rx[%d]: Starting...\n", pi->port.line); 1331 1332 /* Issue a Receive Abort to clear any receive errors */ 1333 writel(MPSC_CHR_2_RA, pi->mpsc_base + MPSC_CHR_2); 1334 if (pi->rcv_data) { 1335 mpsc_enter_hunt(pi); 1336 mpsc_sdma_cmd(pi, SDMA_SDCM_ERD); 1337 } 1338 return; 1339} 1340 1341static void 1342mpsc_stop_rx(struct uart_port *port) 1343{ 1344 struct mpsc_port_info *pi = (struct mpsc_port_info *)port; 1345 1346 pr_debug("mpsc_stop_rx[%d]: Stopping...\n", port->line); 1347 1348 mpsc_sdma_cmd(pi, SDMA_SDCM_AR); 1349 return; 1350} 1351 1352static void 1353mpsc_enable_ms(struct uart_port *port) 1354{ 1355 return; /* Not supported */ 1356} 1357 1358static void 1359mpsc_break_ctl(struct uart_port *port, int ctl) 1360{ 1361 struct mpsc_port_info *pi = (struct mpsc_port_info *)port; 1362 ulong flags; 1363 u32 v; 1364 1365 v = ctl ? 0x00ff0000 : 0; 1366 1367 spin_lock_irqsave(&pi->port.lock, flags); 1368 if (pi->mirror_regs) 1369 pi->MPSC_CHR_1_m = v; 1370 writel(v, pi->mpsc_base + MPSC_CHR_1); 1371 spin_unlock_irqrestore(&pi->port.lock, flags); 1372 1373 return; 1374} 1375 1376static int 1377mpsc_startup(struct uart_port *port) 1378{ 1379 struct mpsc_port_info *pi = (struct mpsc_port_info *)port; 1380 u32 flag = 0; 1381 int rc; 1382 1383 pr_debug("mpsc_startup[%d]: Starting up MPSC, irq: %d\n", 1384 port->line, pi->port.irq); 1385 1386 if ((rc = mpsc_make_ready(pi)) == 0) { 1387 /* Setup IRQ handler */ 1388 mpsc_sdma_intr_ack(pi); 1389 1390 /* If irq's are shared, need to set flag */ 1391 if (mpsc_ports[0].port.irq == mpsc_ports[1].port.irq) 1392 flag = IRQF_SHARED; 1393 1394 if (request_irq(pi->port.irq, mpsc_sdma_intr, flag, 1395 "mpsc-sdma", pi)) 1396 printk(KERN_ERR "MPSC: Can't get SDMA IRQ %d\n", 1397 pi->port.irq); 1398 1399 mpsc_sdma_intr_unmask(pi, 0xf); 1400 mpsc_sdma_set_rx_ring(pi, (struct mpsc_rx_desc *)(pi->rxr_p + 1401 (pi->rxr_posn * MPSC_RXRE_SIZE))); 1402 } 1403 1404 return rc; 1405} 1406 1407static void 1408mpsc_shutdown(struct uart_port *port) 1409{ 1410 struct mpsc_port_info *pi = (struct mpsc_port_info *)port; 1411 1412 pr_debug("mpsc_shutdown[%d]: Shutting down MPSC\n", port->line); 1413 1414 mpsc_sdma_stop(pi); 1415 free_irq(pi->port.irq, pi); 1416 return; 1417} 1418 1419static void 1420mpsc_set_termios(struct uart_port *port, struct ktermios *termios, 1421 struct ktermios *old) 1422{ 1423 struct mpsc_port_info *pi = (struct mpsc_port_info *)port; 1424 u32 baud; 1425 ulong flags; 1426 u32 chr_bits, stop_bits, par; 1427 1428 pi->c_iflag = termios->c_iflag; 1429 pi->c_cflag = termios->c_cflag; 1430 1431 switch (termios->c_cflag & CSIZE) { 1432 case CS5: 1433 chr_bits = MPSC_MPCR_CL_5; 1434 break; 1435 case CS6: 1436 chr_bits = MPSC_MPCR_CL_6; 1437 break; 1438 case CS7: 1439 chr_bits = MPSC_MPCR_CL_7; 1440 break; 1441 case CS8: 1442 default: 1443 chr_bits = MPSC_MPCR_CL_8; 1444 break; 1445 } 1446 1447 if (termios->c_cflag & CSTOPB) 1448 stop_bits = MPSC_MPCR_SBL_2; 1449 else 1450 stop_bits = MPSC_MPCR_SBL_1; 1451 1452 par = MPSC_CHR_2_PAR_EVEN; 1453 if (termios->c_cflag & PARENB) 1454 if (termios->c_cflag & PARODD) 1455 par = MPSC_CHR_2_PAR_ODD; 1456#ifdef CMSPAR 1457 if (termios->c_cflag & CMSPAR) { 1458 if (termios->c_cflag & PARODD) 1459 par = MPSC_CHR_2_PAR_MARK; 1460 else 1461 par = MPSC_CHR_2_PAR_SPACE; 1462 } 1463#endif 1464 1465 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk); 1466 1467 spin_lock_irqsave(&pi->port.lock, flags); 1468 1469 uart_update_timeout(port, termios->c_cflag, baud); 1470 1471 mpsc_set_char_length(pi, chr_bits); 1472 mpsc_set_stop_bit_length(pi, stop_bits); 1473 mpsc_set_parity(pi, par); 1474 mpsc_set_baudrate(pi, baud); 1475 1476 /* Characters/events to read */ 1477 pi->rcv_data = 1; 1478 pi->port.read_status_mask = SDMA_DESC_CMDSTAT_OR; 1479 1480 if (termios->c_iflag & INPCK) 1481 pi->port.read_status_mask |= SDMA_DESC_CMDSTAT_PE | 1482 SDMA_DESC_CMDSTAT_FR; 1483 1484 if (termios->c_iflag & (BRKINT | PARMRK)) 1485 pi->port.read_status_mask |= SDMA_DESC_CMDSTAT_BR; 1486 1487 /* Characters/events to ignore */ 1488 pi->port.ignore_status_mask = 0; 1489 1490 if (termios->c_iflag & IGNPAR) 1491 pi->port.ignore_status_mask |= SDMA_DESC_CMDSTAT_PE | 1492 SDMA_DESC_CMDSTAT_FR; 1493 1494 if (termios->c_iflag & IGNBRK) { 1495 pi->port.ignore_status_mask |= SDMA_DESC_CMDSTAT_BR; 1496 1497 if (termios->c_iflag & IGNPAR) 1498 pi->port.ignore_status_mask |= SDMA_DESC_CMDSTAT_OR; 1499 } 1500 1501 /* Ignore all chars if CREAD not set */ 1502 if (!(termios->c_cflag & CREAD)) 1503 pi->rcv_data = 0; 1504 else 1505 mpsc_start_rx(pi); 1506 1507 spin_unlock_irqrestore(&pi->port.lock, flags); 1508 return; 1509} 1510 1511static const char * 1512mpsc_type(struct uart_port *port) 1513{ 1514 pr_debug("mpsc_type[%d]: port type: %s\n", port->line,MPSC_DRIVER_NAME); 1515 return MPSC_DRIVER_NAME; 1516} 1517 1518static int 1519mpsc_request_port(struct uart_port *port) 1520{ 1521 /* Should make chip/platform specific call */ 1522 return 0; 1523} 1524 1525static void 1526mpsc_release_port(struct uart_port *port) 1527{ 1528 struct mpsc_port_info *pi = (struct mpsc_port_info *)port; 1529 1530 if (pi->ready) { 1531 mpsc_uninit_rings(pi); 1532 mpsc_free_ring_mem(pi); 1533 pi->ready = 0; 1534 } 1535 1536 return; 1537} 1538 1539static void 1540mpsc_config_port(struct uart_port *port, int flags) 1541{ 1542 return; 1543} 1544 1545static int 1546mpsc_verify_port(struct uart_port *port, struct serial_struct *ser) 1547{ 1548 struct mpsc_port_info *pi = (struct mpsc_port_info *)port; 1549 int rc = 0; 1550 1551 pr_debug("mpsc_verify_port[%d]: Verifying port data\n", pi->port.line); 1552 1553 if (ser->type != PORT_UNKNOWN && ser->type != PORT_MPSC) 1554 rc = -EINVAL; 1555 else if (pi->port.irq != ser->irq) 1556 rc = -EINVAL; 1557 else if (ser->io_type != SERIAL_IO_MEM) 1558 rc = -EINVAL; 1559 else if (pi->port.uartclk / 16 != ser->baud_base) /* Not sure */ 1560 rc = -EINVAL; 1561 else if ((void *)pi->port.mapbase != ser->iomem_base) 1562 rc = -EINVAL; 1563 else if (pi->port.iobase != ser->port) 1564 rc = -EINVAL; 1565 else if (ser->hub6 != 0) 1566 rc = -EINVAL; 1567 1568 return rc; 1569} 1570 1571static struct uart_ops mpsc_pops = { 1572 .tx_empty = mpsc_tx_empty, 1573 .set_mctrl = mpsc_set_mctrl, 1574 .get_mctrl = mpsc_get_mctrl, 1575 .stop_tx = mpsc_stop_tx, 1576 .start_tx = mpsc_start_tx, 1577 .stop_rx = mpsc_stop_rx, 1578 .enable_ms = mpsc_enable_ms, 1579 .break_ctl = mpsc_break_ctl, 1580 .startup = mpsc_startup, 1581 .shutdown = mpsc_shutdown, 1582 .set_termios = mpsc_set_termios, 1583 .type = mpsc_type, 1584 .release_port = mpsc_release_port, 1585 .request_port = mpsc_request_port, 1586 .config_port = mpsc_config_port, 1587 .verify_port = mpsc_verify_port, 1588}; 1589 1590/* 1591 ****************************************************************************** 1592 * 1593 * Console Interface Routines 1594 * 1595 ****************************************************************************** 1596 */ 1597 1598#ifdef CONFIG_SERIAL_MPSC_CONSOLE 1599static void 1600mpsc_console_write(struct console *co, const char *s, uint count) 1601{ 1602 struct mpsc_port_info *pi = &mpsc_ports[co->index]; 1603 u8 *bp, *dp, add_cr = 0; 1604 int i; 1605 unsigned long iflags; 1606 1607 spin_lock_irqsave(&pi->tx_lock, iflags); 1608 1609 while (pi->txr_head != pi->txr_tail) { 1610 while (mpsc_sdma_tx_active(pi)) 1611 udelay(100); 1612 mpsc_sdma_intr_ack(pi); 1613 mpsc_tx_intr(pi); 1614 } 1615 1616 while (mpsc_sdma_tx_active(pi)) 1617 udelay(100); 1618 1619 while (count > 0) { 1620 bp = dp = pi->txb + (pi->txr_head * MPSC_TXBE_SIZE); 1621 1622 for (i = 0; i < MPSC_TXBE_SIZE; i++) { 1623 if (count == 0) 1624 break; 1625 1626 if (add_cr) { 1627 *(dp++) = '\r'; 1628 add_cr = 0; 1629 } 1630 else { 1631 *(dp++) = *s; 1632 1633 if (*(s++) == '\n') { /* add '\r' after '\n' */ 1634 add_cr = 1; 1635 count++; 1636 } 1637 } 1638 1639 count--; 1640 } 1641 1642 dma_cache_sync(pi->port.dev, (void *) bp, MPSC_TXBE_SIZE, DMA_BIDIRECTIONAL); 1643#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE) 1644 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */ 1645 flush_dcache_range((ulong)bp, 1646 (ulong)bp + MPSC_TXBE_SIZE); 1647#endif 1648 mpsc_setup_tx_desc(pi, i, 0); 1649 pi->txr_head = (pi->txr_head + 1) & (MPSC_TXR_ENTRIES - 1); 1650 mpsc_sdma_start_tx(pi); 1651 1652 while (mpsc_sdma_tx_active(pi)) 1653 udelay(100); 1654 1655 pi->txr_tail = (pi->txr_tail + 1) & (MPSC_TXR_ENTRIES - 1); 1656 } 1657 1658 spin_unlock_irqrestore(&pi->tx_lock, iflags); 1659 return; 1660} 1661 1662static int __init 1663mpsc_console_setup(struct console *co, char *options) 1664{ 1665 struct mpsc_port_info *pi; 1666 int baud, bits, parity, flow; 1667 1668 pr_debug("mpsc_console_setup[%d]: options: %s\n", co->index, options); 1669 1670 if (co->index >= MPSC_NUM_CTLRS) 1671 co->index = 0; 1672 1673 pi = &mpsc_ports[co->index]; 1674 1675 baud = pi->default_baud; 1676 bits = pi->default_bits; 1677 parity = pi->default_parity; 1678 flow = pi->default_flow; 1679 1680 if (!pi->port.ops) 1681 return -ENODEV; 1682 1683 spin_lock_init(&pi->port.lock); /* Temporary fix--copied from 8250.c */ 1684 1685 if (options) 1686 uart_parse_options(options, &baud, &parity, &bits, &flow); 1687 1688 return uart_set_options(&pi->port, co, baud, parity, bits, flow); 1689} 1690 1691static struct console mpsc_console = { 1692 .name = MPSC_DEV_NAME, 1693 .write = mpsc_console_write, 1694 .device = uart_console_device, 1695 .setup = mpsc_console_setup, 1696 .flags = CON_PRINTBUFFER, 1697 .index = -1, 1698 .data = &mpsc_reg, 1699}; 1700 1701static int __init 1702mpsc_late_console_init(void) 1703{ 1704 pr_debug("mpsc_late_console_init: Enter\n"); 1705 1706 if (!(mpsc_console.flags & CON_ENABLED)) 1707 register_console(&mpsc_console); 1708 return 0; 1709} 1710 1711late_initcall(mpsc_late_console_init); 1712 1713#define MPSC_CONSOLE &mpsc_console 1714#else 1715#define MPSC_CONSOLE NULL 1716#endif 1717/* 1718 ****************************************************************************** 1719 * 1720 * Dummy Platform Driver to extract & map shared register regions 1721 * 1722 ****************************************************************************** 1723 */ 1724static void 1725mpsc_resource_err(char *s) 1726{ 1727 printk(KERN_WARNING "MPSC: Platform device resource error in %s\n", s); 1728 return; 1729} 1730 1731static int 1732mpsc_shared_map_regs(struct platform_device *pd) 1733{ 1734 struct resource *r; 1735 1736 if ((r = platform_get_resource(pd, IORESOURCE_MEM, 1737 MPSC_ROUTING_BASE_ORDER)) && request_mem_region(r->start, 1738 MPSC_ROUTING_REG_BLOCK_SIZE, "mpsc_routing_regs")) { 1739 1740 mpsc_shared_regs.mpsc_routing_base = ioremap(r->start, 1741 MPSC_ROUTING_REG_BLOCK_SIZE); 1742 mpsc_shared_regs.mpsc_routing_base_p = r->start; 1743 } 1744 else { 1745 mpsc_resource_err("MPSC routing base"); 1746 return -ENOMEM; 1747 } 1748 1749 if ((r = platform_get_resource(pd, IORESOURCE_MEM, 1750 MPSC_SDMA_INTR_BASE_ORDER)) && request_mem_region(r->start, 1751 MPSC_SDMA_INTR_REG_BLOCK_SIZE, "sdma_intr_regs")) { 1752 1753 mpsc_shared_regs.sdma_intr_base = ioremap(r->start, 1754 MPSC_SDMA_INTR_REG_BLOCK_SIZE); 1755 mpsc_shared_regs.sdma_intr_base_p = r->start; 1756 } 1757 else { 1758 iounmap(mpsc_shared_regs.mpsc_routing_base); 1759 release_mem_region(mpsc_shared_regs.mpsc_routing_base_p, 1760 MPSC_ROUTING_REG_BLOCK_SIZE); 1761 mpsc_resource_err("SDMA intr base"); 1762 return -ENOMEM; 1763 } 1764 1765 return 0; 1766} 1767 1768static void 1769mpsc_shared_unmap_regs(void) 1770{ 1771 if (!mpsc_shared_regs.mpsc_routing_base) { 1772 iounmap(mpsc_shared_regs.mpsc_routing_base); 1773 release_mem_region(mpsc_shared_regs.mpsc_routing_base_p, 1774 MPSC_ROUTING_REG_BLOCK_SIZE); 1775 } 1776 if (!mpsc_shared_regs.sdma_intr_base) { 1777 iounmap(mpsc_shared_regs.sdma_intr_base); 1778 release_mem_region(mpsc_shared_regs.sdma_intr_base_p, 1779 MPSC_SDMA_INTR_REG_BLOCK_SIZE); 1780 } 1781 1782 mpsc_shared_regs.mpsc_routing_base = NULL; 1783 mpsc_shared_regs.sdma_intr_base = NULL; 1784 1785 mpsc_shared_regs.mpsc_routing_base_p = 0; 1786 mpsc_shared_regs.sdma_intr_base_p = 0; 1787 1788 return; 1789} 1790 1791static int 1792mpsc_shared_drv_probe(struct platform_device *dev) 1793{ 1794 struct mpsc_shared_pdata *pdata; 1795 int rc = -ENODEV; 1796 1797 if (dev->id == 0) { 1798 if (!(rc = mpsc_shared_map_regs(dev))) { 1799 pdata = (struct mpsc_shared_pdata *)dev->dev.platform_data; 1800 1801 mpsc_shared_regs.MPSC_MRR_m = pdata->mrr_val; 1802 mpsc_shared_regs.MPSC_RCRR_m= pdata->rcrr_val; 1803 mpsc_shared_regs.MPSC_TCRR_m= pdata->tcrr_val; 1804 mpsc_shared_regs.SDMA_INTR_CAUSE_m = 1805 pdata->intr_cause_val; 1806 mpsc_shared_regs.SDMA_INTR_MASK_m = 1807 pdata->intr_mask_val; 1808 1809 rc = 0; 1810 } 1811 } 1812 1813 return rc; 1814} 1815 1816static int 1817mpsc_shared_drv_remove(struct platform_device *dev) 1818{ 1819 int rc = -ENODEV; 1820 1821 if (dev->id == 0) { 1822 mpsc_shared_unmap_regs(); 1823 mpsc_shared_regs.MPSC_MRR_m = 0; 1824 mpsc_shared_regs.MPSC_RCRR_m = 0; 1825 mpsc_shared_regs.MPSC_TCRR_m = 0; 1826 mpsc_shared_regs.SDMA_INTR_CAUSE_m = 0; 1827 mpsc_shared_regs.SDMA_INTR_MASK_m = 0; 1828 rc = 0; 1829 } 1830 1831 return rc; 1832} 1833 1834static struct platform_driver mpsc_shared_driver = { 1835 .probe = mpsc_shared_drv_probe, 1836 .remove = mpsc_shared_drv_remove, 1837 .driver = { 1838 .name = MPSC_SHARED_NAME, 1839 }, 1840}; 1841 1842/* 1843 ****************************************************************************** 1844 * 1845 * Driver Interface Routines 1846 * 1847 ****************************************************************************** 1848 */ 1849static struct uart_driver mpsc_reg = { 1850 .owner = THIS_MODULE, 1851 .driver_name = MPSC_DRIVER_NAME, 1852 .dev_name = MPSC_DEV_NAME, 1853 .major = MPSC_MAJOR, 1854 .minor = MPSC_MINOR_START, 1855 .nr = MPSC_NUM_CTLRS, 1856 .cons = MPSC_CONSOLE, 1857}; 1858 1859static int 1860mpsc_drv_map_regs(struct mpsc_port_info *pi, struct platform_device *pd) 1861{ 1862 struct resource *r; 1863 1864 if ((r = platform_get_resource(pd, IORESOURCE_MEM, MPSC_BASE_ORDER)) && 1865 request_mem_region(r->start, MPSC_REG_BLOCK_SIZE, "mpsc_regs")){ 1866 1867 pi->mpsc_base = ioremap(r->start, MPSC_REG_BLOCK_SIZE); 1868 pi->mpsc_base_p = r->start; 1869 } 1870 else { 1871 mpsc_resource_err("MPSC base"); 1872 return -ENOMEM; 1873 } 1874 1875 if ((r = platform_get_resource(pd, IORESOURCE_MEM, 1876 MPSC_SDMA_BASE_ORDER)) && request_mem_region(r->start, 1877 MPSC_SDMA_REG_BLOCK_SIZE, "sdma_regs")) { 1878 1879 pi->sdma_base = ioremap(r->start,MPSC_SDMA_REG_BLOCK_SIZE); 1880 pi->sdma_base_p = r->start; 1881 } 1882 else { 1883 mpsc_resource_err("SDMA base"); 1884 if (pi->mpsc_base) { 1885 iounmap(pi->mpsc_base); 1886 pi->mpsc_base = NULL; 1887 } 1888 return -ENOMEM; 1889 } 1890 1891 if ((r = platform_get_resource(pd,IORESOURCE_MEM,MPSC_BRG_BASE_ORDER)) 1892 && request_mem_region(r->start, MPSC_BRG_REG_BLOCK_SIZE, 1893 "brg_regs")) { 1894 1895 pi->brg_base = ioremap(r->start, MPSC_BRG_REG_BLOCK_SIZE); 1896 pi->brg_base_p = r->start; 1897 } 1898 else { 1899 mpsc_resource_err("BRG base"); 1900 if (pi->mpsc_base) { 1901 iounmap(pi->mpsc_base); 1902 pi->mpsc_base = NULL; 1903 } 1904 if (pi->sdma_base) { 1905 iounmap(pi->sdma_base); 1906 pi->sdma_base = NULL; 1907 } 1908 return -ENOMEM; 1909 } 1910 1911 return 0; 1912} 1913 1914static void 1915mpsc_drv_unmap_regs(struct mpsc_port_info *pi) 1916{ 1917 if (!pi->mpsc_base) { 1918 iounmap(pi->mpsc_base); 1919 release_mem_region(pi->mpsc_base_p, MPSC_REG_BLOCK_SIZE); 1920 } 1921 if (!pi->sdma_base) { 1922 iounmap(pi->sdma_base); 1923 release_mem_region(pi->sdma_base_p, MPSC_SDMA_REG_BLOCK_SIZE); 1924 } 1925 if (!pi->brg_base) { 1926 iounmap(pi->brg_base); 1927 release_mem_region(pi->brg_base_p, MPSC_BRG_REG_BLOCK_SIZE); 1928 } 1929 1930 pi->mpsc_base = NULL; 1931 pi->sdma_base = NULL; 1932 pi->brg_base = NULL; 1933 1934 pi->mpsc_base_p = 0; 1935 pi->sdma_base_p = 0; 1936 pi->brg_base_p = 0; 1937 1938 return; 1939} 1940 1941static void 1942mpsc_drv_get_platform_data(struct mpsc_port_info *pi, 1943 struct platform_device *pd, int num) 1944{ 1945 struct mpsc_pdata *pdata; 1946 1947 pdata = (struct mpsc_pdata *)pd->dev.platform_data; 1948 1949 pi->port.uartclk = pdata->brg_clk_freq; 1950 pi->port.iotype = UPIO_MEM; 1951 pi->port.line = num; 1952 pi->port.type = PORT_MPSC; 1953 pi->port.fifosize = MPSC_TXBE_SIZE; 1954 pi->port.membase = pi->mpsc_base; 1955 pi->port.mapbase = (ulong)pi->mpsc_base; 1956 pi->port.ops = &mpsc_pops; 1957 1958 pi->mirror_regs = pdata->mirror_regs; 1959 pi->cache_mgmt = pdata->cache_mgmt; 1960 pi->brg_can_tune = pdata->brg_can_tune; 1961 pi->brg_clk_src = pdata->brg_clk_src; 1962 pi->mpsc_max_idle = pdata->max_idle; 1963 pi->default_baud = pdata->default_baud; 1964 pi->default_bits = pdata->default_bits; 1965 pi->default_parity = pdata->default_parity; 1966 pi->default_flow = pdata->default_flow; 1967 1968 /* Initial values of mirrored regs */ 1969 pi->MPSC_CHR_1_m = pdata->chr_1_val; 1970 pi->MPSC_CHR_2_m = pdata->chr_2_val; 1971 pi->MPSC_CHR_10_m = pdata->chr_10_val; 1972 pi->MPSC_MPCR_m = pdata->mpcr_val; 1973 pi->BRG_BCR_m = pdata->bcr_val; 1974 1975 pi->shared_regs = &mpsc_shared_regs; 1976 1977 pi->port.irq = platform_get_irq(pd, 0); 1978 1979 return; 1980} 1981 1982static int 1983mpsc_drv_probe(struct platform_device *dev) 1984{ 1985 struct mpsc_port_info *pi; 1986 int rc = -ENODEV; 1987 1988 pr_debug("mpsc_drv_probe: Adding MPSC %d\n", dev->id); 1989 1990 if (dev->id < MPSC_NUM_CTLRS) { 1991 pi = &mpsc_ports[dev->id]; 1992 1993 if (!(rc = mpsc_drv_map_regs(pi, dev))) { 1994 mpsc_drv_get_platform_data(pi, dev, dev->id); 1995 1996 if (!(rc = mpsc_make_ready(pi))) { 1997 spin_lock_init(&pi->tx_lock); 1998 if (!(rc = uart_add_one_port(&mpsc_reg, 1999 &pi->port))) 2000 rc = 0; 2001 else { 2002 mpsc_release_port( 2003 (struct uart_port *)pi); 2004 mpsc_drv_unmap_regs(pi); 2005 } 2006 } 2007 else 2008 mpsc_drv_unmap_regs(pi); 2009 } 2010 } 2011 2012 return rc; 2013} 2014 2015static int 2016mpsc_drv_remove(struct platform_device *dev) 2017{ 2018 pr_debug("mpsc_drv_exit: Removing MPSC %d\n", dev->id); 2019 2020 if (dev->id < MPSC_NUM_CTLRS) { 2021 uart_remove_one_port(&mpsc_reg, &mpsc_ports[dev->id].port); 2022 mpsc_release_port((struct uart_port *)&mpsc_ports[dev->id].port); 2023 mpsc_drv_unmap_regs(&mpsc_ports[dev->id]); 2024 return 0; 2025 } 2026 else 2027 return -ENODEV; 2028} 2029 2030static struct platform_driver mpsc_driver = { 2031 .probe = mpsc_drv_probe, 2032 .remove = mpsc_drv_remove, 2033 .driver = { 2034 .name = MPSC_CTLR_NAME, 2035 }, 2036}; 2037 2038static int __init 2039mpsc_drv_init(void) 2040{ 2041 int rc; 2042 2043 printk(KERN_INFO "Serial: MPSC driver $Revision: 1.1.1.1 $\n"); 2044 2045 memset(mpsc_ports, 0, sizeof(mpsc_ports)); 2046 memset(&mpsc_shared_regs, 0, sizeof(mpsc_shared_regs)); 2047 2048 if (!(rc = uart_register_driver(&mpsc_reg))) { 2049 if (!(rc = platform_driver_register(&mpsc_shared_driver))) { 2050 if ((rc = platform_driver_register(&mpsc_driver))) { 2051 platform_driver_unregister(&mpsc_shared_driver); 2052 uart_unregister_driver(&mpsc_reg); 2053 } 2054 } 2055 else 2056 uart_unregister_driver(&mpsc_reg); 2057 } 2058 2059 return rc; 2060 2061} 2062 2063static void __exit 2064mpsc_drv_exit(void) 2065{ 2066 platform_driver_unregister(&mpsc_driver); 2067 platform_driver_unregister(&mpsc_shared_driver); 2068 uart_unregister_driver(&mpsc_reg); 2069 memset(mpsc_ports, 0, sizeof(mpsc_ports)); 2070 memset(&mpsc_shared_regs, 0, sizeof(mpsc_shared_regs)); 2071 return; 2072} 2073 2074module_init(mpsc_drv_init); 2075module_exit(mpsc_drv_exit); 2076 2077MODULE_AUTHOR("Mark A. Greer <mgreer@mvista.com>"); 2078MODULE_DESCRIPTION("Generic Marvell MPSC serial/UART driver $Revision: 1.1.1.1 $"); 2079MODULE_VERSION(MPSC_VERSION); 2080MODULE_LICENSE("GPL"); 2081MODULE_ALIAS_CHARDEV_MAJOR(MPSC_MAJOR); 2082