1/* 2 * Driver for Zilog serial chips found on SGI workstations and 3 * servers. This driver could actually be made more generic. 4 * 5 * This is based on the drivers/serial/sunzilog.c code as of 2.6.0-test7 and the 6 * old drivers/sgi/char/sgiserial.c code which itself is based of the original 7 * drivers/sbus/char/zs.c code. A lot of code has been simply moved over 8 * directly from there but much has been rewritten. Credits therefore go out 9 * to David S. Miller, Eddie C. Dost, Pete Zaitcev, Ted Ts'o and Alex Buell 10 * for their work there. 11 * 12 * Copyright (C) 2002 Ralf Baechle (ralf@linux-mips.org) 13 * Copyright (C) 2002 David S. Miller (davem@redhat.com) 14 */ 15#include <linux/module.h> 16#include <linux/kernel.h> 17#include <linux/errno.h> 18#include <linux/delay.h> 19#include <linux/tty.h> 20#include <linux/tty_flip.h> 21#include <linux/major.h> 22#include <linux/string.h> 23#include <linux/ptrace.h> 24#include <linux/ioport.h> 25#include <linux/slab.h> 26#include <linux/circ_buf.h> 27#include <linux/serial.h> 28#include <linux/sysrq.h> 29#include <linux/console.h> 30#include <linux/spinlock.h> 31#include <linux/init.h> 32 33#include <asm/io.h> 34#include <asm/irq.h> 35#include <asm/sgialib.h> 36#include <asm/sgi/ioc.h> 37#include <asm/sgi/hpc3.h> 38#include <asm/sgi/ip22.h> 39 40#if defined(CONFIG_SERIAL_IP22_ZILOG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 41#define SUPPORT_SYSRQ 42#endif 43 44#include <linux/serial_core.h> 45 46#include "ip22zilog.h" 47 48void ip22_do_break(void); 49 50/* 51 * On IP22 we need to delay after register accesses but we do not need to 52 * flush writes. 53 */ 54#define ZSDELAY() udelay(5) 55#define ZSDELAY_LONG() udelay(20) 56#define ZS_WSYNC(channel) do { } while (0) 57 58#define NUM_IP22ZILOG 1 59#define NUM_CHANNELS (NUM_IP22ZILOG * 2) 60 61#define ZS_CLOCK 3672000 /* Zilog input clock rate. */ 62#define ZS_CLOCK_DIVISOR 16 /* Divisor this driver uses. */ 63 64/* 65 * We wrap our port structure around the generic uart_port. 66 */ 67struct uart_ip22zilog_port { 68 struct uart_port port; 69 70 /* IRQ servicing chain. */ 71 struct uart_ip22zilog_port *next; 72 73 /* Current values of Zilog write registers. */ 74 unsigned char curregs[NUM_ZSREGS]; 75 76 unsigned int flags; 77#define IP22ZILOG_FLAG_IS_CONS 0x00000004 78#define IP22ZILOG_FLAG_IS_KGDB 0x00000008 79#define IP22ZILOG_FLAG_MODEM_STATUS 0x00000010 80#define IP22ZILOG_FLAG_IS_CHANNEL_A 0x00000020 81#define IP22ZILOG_FLAG_REGS_HELD 0x00000040 82#define IP22ZILOG_FLAG_TX_STOPPED 0x00000080 83#define IP22ZILOG_FLAG_TX_ACTIVE 0x00000100 84 85 unsigned int cflag; 86 87 /* L1-A keyboard break state. */ 88 int kbd_id; 89 int l1_down; 90 91 unsigned char parity_mask; 92 unsigned char prev_status; 93}; 94 95#define ZILOG_CHANNEL_FROM_PORT(PORT) ((struct zilog_channel *)((PORT)->membase)) 96#define UART_ZILOG(PORT) ((struct uart_ip22zilog_port *)(PORT)) 97#define IP22ZILOG_GET_CURR_REG(PORT, REGNUM) \ 98 (UART_ZILOG(PORT)->curregs[REGNUM]) 99#define IP22ZILOG_SET_CURR_REG(PORT, REGNUM, REGVAL) \ 100 ((UART_ZILOG(PORT)->curregs[REGNUM]) = (REGVAL)) 101#define ZS_IS_CONS(UP) ((UP)->flags & IP22ZILOG_FLAG_IS_CONS) 102#define ZS_IS_KGDB(UP) ((UP)->flags & IP22ZILOG_FLAG_IS_KGDB) 103#define ZS_WANTS_MODEM_STATUS(UP) ((UP)->flags & IP22ZILOG_FLAG_MODEM_STATUS) 104#define ZS_IS_CHANNEL_A(UP) ((UP)->flags & IP22ZILOG_FLAG_IS_CHANNEL_A) 105#define ZS_REGS_HELD(UP) ((UP)->flags & IP22ZILOG_FLAG_REGS_HELD) 106#define ZS_TX_STOPPED(UP) ((UP)->flags & IP22ZILOG_FLAG_TX_STOPPED) 107#define ZS_TX_ACTIVE(UP) ((UP)->flags & IP22ZILOG_FLAG_TX_ACTIVE) 108 109/* Reading and writing Zilog8530 registers. The delays are to make this 110 * driver work on the IP22 which needs a settling delay after each chip 111 * register access, other machines handle this in hardware via auxiliary 112 * flip-flops which implement the settle time we do in software. 113 * 114 * The port lock must be held and local IRQs must be disabled 115 * when {read,write}_zsreg is invoked. 116 */ 117static unsigned char read_zsreg(struct zilog_channel *channel, 118 unsigned char reg) 119{ 120 unsigned char retval; 121 122 writeb(reg, &channel->control); 123 ZSDELAY(); 124 retval = readb(&channel->control); 125 ZSDELAY(); 126 127 return retval; 128} 129 130static void write_zsreg(struct zilog_channel *channel, 131 unsigned char reg, unsigned char value) 132{ 133 writeb(reg, &channel->control); 134 ZSDELAY(); 135 writeb(value, &channel->control); 136 ZSDELAY(); 137} 138 139static void ip22zilog_clear_fifo(struct zilog_channel *channel) 140{ 141 int i; 142 143 for (i = 0; i < 32; i++) { 144 unsigned char regval; 145 146 regval = readb(&channel->control); 147 ZSDELAY(); 148 if (regval & Rx_CH_AV) 149 break; 150 151 regval = read_zsreg(channel, R1); 152 readb(&channel->data); 153 ZSDELAY(); 154 155 if (regval & (PAR_ERR | Rx_OVR | CRC_ERR)) { 156 writeb(ERR_RES, &channel->control); 157 ZSDELAY(); 158 ZS_WSYNC(channel); 159 } 160 } 161} 162 163/* This function must only be called when the TX is not busy. The UART 164 * port lock must be held and local interrupts disabled. 165 */ 166static void __load_zsregs(struct zilog_channel *channel, unsigned char *regs) 167{ 168 int i; 169 170 /* Let pending transmits finish. */ 171 for (i = 0; i < 1000; i++) { 172 unsigned char stat = read_zsreg(channel, R1); 173 if (stat & ALL_SNT) 174 break; 175 udelay(100); 176 } 177 178 writeb(ERR_RES, &channel->control); 179 ZSDELAY(); 180 ZS_WSYNC(channel); 181 182 ip22zilog_clear_fifo(channel); 183 184 /* Disable all interrupts. */ 185 write_zsreg(channel, R1, 186 regs[R1] & ~(RxINT_MASK | TxINT_ENAB | EXT_INT_ENAB)); 187 188 /* Set parity, sync config, stop bits, and clock divisor. */ 189 write_zsreg(channel, R4, regs[R4]); 190 191 /* Set misc. TX/RX control bits. */ 192 write_zsreg(channel, R10, regs[R10]); 193 194 /* Set TX/RX controls sans the enable bits. */ 195 write_zsreg(channel, R3, regs[R3] & ~RxENAB); 196 write_zsreg(channel, R5, regs[R5] & ~TxENAB); 197 198 /* Synchronous mode config. */ 199 write_zsreg(channel, R6, regs[R6]); 200 write_zsreg(channel, R7, regs[R7]); 201 202 /* Don't mess with the interrupt vector (R2, unused by us) and 203 * master interrupt control (R9). We make sure this is setup 204 * properly at probe time then never touch it again. 205 */ 206 207 /* Disable baud generator. */ 208 write_zsreg(channel, R14, regs[R14] & ~BRENAB); 209 210 /* Clock mode control. */ 211 write_zsreg(channel, R11, regs[R11]); 212 213 /* Lower and upper byte of baud rate generator divisor. */ 214 write_zsreg(channel, R12, regs[R12]); 215 write_zsreg(channel, R13, regs[R13]); 216 217 /* Now rewrite R14, with BRENAB (if set). */ 218 write_zsreg(channel, R14, regs[R14]); 219 220 /* External status interrupt control. */ 221 write_zsreg(channel, R15, regs[R15]); 222 223 /* Reset external status interrupts. */ 224 write_zsreg(channel, R0, RES_EXT_INT); 225 write_zsreg(channel, R0, RES_EXT_INT); 226 227 /* Rewrite R3/R5, this time without enables masked. */ 228 write_zsreg(channel, R3, regs[R3]); 229 write_zsreg(channel, R5, regs[R5]); 230 231 /* Rewrite R1, this time without IRQ enabled masked. */ 232 write_zsreg(channel, R1, regs[R1]); 233} 234 235/* Reprogram the Zilog channel HW registers with the copies found in the 236 * software state struct. If the transmitter is busy, we defer this update 237 * until the next TX complete interrupt. Else, we do it right now. 238 * 239 * The UART port lock must be held and local interrupts disabled. 240 */ 241static void ip22zilog_maybe_update_regs(struct uart_ip22zilog_port *up, 242 struct zilog_channel *channel) 243{ 244 if (!ZS_REGS_HELD(up)) { 245 if (ZS_TX_ACTIVE(up)) { 246 up->flags |= IP22ZILOG_FLAG_REGS_HELD; 247 } else { 248 __load_zsregs(channel, up->curregs); 249 } 250 } 251} 252 253static void ip22zilog_receive_chars(struct uart_ip22zilog_port *up, 254 struct zilog_channel *channel) 255{ 256 struct tty_struct *tty = up->port.info->tty; 257 258 while (1) { 259 unsigned char ch, r1, flag; 260 261 r1 = read_zsreg(channel, R1); 262 if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR)) { 263 writeb(ERR_RES, &channel->control); 264 ZSDELAY(); 265 ZS_WSYNC(channel); 266 } 267 268 ch = readb(&channel->control); 269 ZSDELAY(); 270 271 /* This funny hack depends upon BRK_ABRT not interfering 272 * with the other bits we care about in R1. 273 */ 274 if (ch & BRK_ABRT) 275 r1 |= BRK_ABRT; 276 277 ch = readb(&channel->data); 278 ZSDELAY(); 279 280 ch &= up->parity_mask; 281 282 if (ZS_IS_CONS(up) && (r1 & BRK_ABRT)) { 283 /* Wait for BREAK to deassert to avoid potentially 284 * confusing the PROM. 285 */ 286 while (1) { 287 ch = readb(&channel->control); 288 ZSDELAY(); 289 if (!(ch & BRK_ABRT)) 290 break; 291 } 292 ip22_do_break(); 293 return; 294 } 295 296 /* A real serial line, record the character and status. */ 297 flag = TTY_NORMAL; 298 up->port.icount.rx++; 299 if (r1 & (BRK_ABRT | PAR_ERR | Rx_OVR | CRC_ERR)) { 300 if (r1 & BRK_ABRT) { 301 r1 &= ~(PAR_ERR | CRC_ERR); 302 up->port.icount.brk++; 303 if (uart_handle_break(&up->port)) 304 goto next_char; 305 } 306 else if (r1 & PAR_ERR) 307 up->port.icount.parity++; 308 else if (r1 & CRC_ERR) 309 up->port.icount.frame++; 310 if (r1 & Rx_OVR) 311 up->port.icount.overrun++; 312 r1 &= up->port.read_status_mask; 313 if (r1 & BRK_ABRT) 314 flag = TTY_BREAK; 315 else if (r1 & PAR_ERR) 316 flag = TTY_PARITY; 317 else if (r1 & CRC_ERR) 318 flag = TTY_FRAME; 319 } 320 if (uart_handle_sysrq_char(&up->port, ch)) 321 goto next_char; 322 323 if (up->port.ignore_status_mask == 0xff || 324 (r1 & up->port.ignore_status_mask) == 0) 325 tty_insert_flip_char(tty, ch, flag); 326 327 if (r1 & Rx_OVR) 328 tty_insert_flip_char(tty, 0, TTY_OVERRUN); 329 next_char: 330 ch = readb(&channel->control); 331 ZSDELAY(); 332 if (!(ch & Rx_CH_AV)) 333 break; 334 } 335 336 tty_flip_buffer_push(tty); 337} 338 339static void ip22zilog_status_handle(struct uart_ip22zilog_port *up, 340 struct zilog_channel *channel) 341{ 342 unsigned char status; 343 344 status = readb(&channel->control); 345 ZSDELAY(); 346 347 writeb(RES_EXT_INT, &channel->control); 348 ZSDELAY(); 349 ZS_WSYNC(channel); 350 351 if (ZS_WANTS_MODEM_STATUS(up)) { 352 if (status & SYNC) 353 up->port.icount.dsr++; 354 355 /* The Zilog just gives us an interrupt when DCD/CTS/etc. change. 356 * But it does not tell us which bit has changed, we have to keep 357 * track of this ourselves. 358 */ 359 if ((status & DCD) ^ up->prev_status) 360 uart_handle_dcd_change(&up->port, 361 (status & DCD)); 362 if ((status & CTS) ^ up->prev_status) 363 uart_handle_cts_change(&up->port, 364 (status & CTS)); 365 366 wake_up_interruptible(&up->port.info->delta_msr_wait); 367 } 368 369 up->prev_status = status; 370} 371 372static void ip22zilog_transmit_chars(struct uart_ip22zilog_port *up, 373 struct zilog_channel *channel) 374{ 375 struct circ_buf *xmit; 376 377 if (ZS_IS_CONS(up)) { 378 unsigned char status = readb(&channel->control); 379 ZSDELAY(); 380 381 /* TX still busy? Just wait for the next TX done interrupt. 382 * 383 * It can occur because of how we do serial console writes. It would 384 * be nice to transmit console writes just like we normally would for 385 * a TTY line. (ie. buffered and TX interrupt driven). That is not 386 * easy because console writes cannot sleep. One solution might be 387 * to poll on enough port->xmit space becomming free. -DaveM 388 */ 389 if (!(status & Tx_BUF_EMP)) 390 return; 391 } 392 393 up->flags &= ~IP22ZILOG_FLAG_TX_ACTIVE; 394 395 if (ZS_REGS_HELD(up)) { 396 __load_zsregs(channel, up->curregs); 397 up->flags &= ~IP22ZILOG_FLAG_REGS_HELD; 398 } 399 400 if (ZS_TX_STOPPED(up)) { 401 up->flags &= ~IP22ZILOG_FLAG_TX_STOPPED; 402 goto ack_tx_int; 403 } 404 405 if (up->port.x_char) { 406 up->flags |= IP22ZILOG_FLAG_TX_ACTIVE; 407 writeb(up->port.x_char, &channel->data); 408 ZSDELAY(); 409 ZS_WSYNC(channel); 410 411 up->port.icount.tx++; 412 up->port.x_char = 0; 413 return; 414 } 415 416 if (up->port.info == NULL) 417 goto ack_tx_int; 418 xmit = &up->port.info->xmit; 419 if (uart_circ_empty(xmit)) 420 goto ack_tx_int; 421 if (uart_tx_stopped(&up->port)) 422 goto ack_tx_int; 423 424 up->flags |= IP22ZILOG_FLAG_TX_ACTIVE; 425 writeb(xmit->buf[xmit->tail], &channel->data); 426 ZSDELAY(); 427 ZS_WSYNC(channel); 428 429 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 430 up->port.icount.tx++; 431 432 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 433 uart_write_wakeup(&up->port); 434 435 return; 436 437ack_tx_int: 438 writeb(RES_Tx_P, &channel->control); 439 ZSDELAY(); 440 ZS_WSYNC(channel); 441} 442 443static irqreturn_t ip22zilog_interrupt(int irq, void *dev_id) 444{ 445 struct uart_ip22zilog_port *up = dev_id; 446 447 while (up) { 448 struct zilog_channel *channel 449 = ZILOG_CHANNEL_FROM_PORT(&up->port); 450 unsigned char r3; 451 452 spin_lock(&up->port.lock); 453 r3 = read_zsreg(channel, R3); 454 455 /* Channel A */ 456 if (r3 & (CHAEXT | CHATxIP | CHARxIP)) { 457 writeb(RES_H_IUS, &channel->control); 458 ZSDELAY(); 459 ZS_WSYNC(channel); 460 461 if (r3 & CHARxIP) 462 ip22zilog_receive_chars(up, channel); 463 if (r3 & CHAEXT) 464 ip22zilog_status_handle(up, channel); 465 if (r3 & CHATxIP) 466 ip22zilog_transmit_chars(up, channel); 467 } 468 spin_unlock(&up->port.lock); 469 470 /* Channel B */ 471 up = up->next; 472 channel = ZILOG_CHANNEL_FROM_PORT(&up->port); 473 474 spin_lock(&up->port.lock); 475 if (r3 & (CHBEXT | CHBTxIP | CHBRxIP)) { 476 writeb(RES_H_IUS, &channel->control); 477 ZSDELAY(); 478 ZS_WSYNC(channel); 479 480 if (r3 & CHBRxIP) 481 ip22zilog_receive_chars(up, channel); 482 if (r3 & CHBEXT) 483 ip22zilog_status_handle(up, channel); 484 if (r3 & CHBTxIP) 485 ip22zilog_transmit_chars(up, channel); 486 } 487 spin_unlock(&up->port.lock); 488 489 up = up->next; 490 } 491 492 return IRQ_HANDLED; 493} 494 495/* A convenient way to quickly get R0 status. The caller must _not_ hold the 496 * port lock, it is acquired here. 497 */ 498static __inline__ unsigned char ip22zilog_read_channel_status(struct uart_port *port) 499{ 500 struct zilog_channel *channel; 501 unsigned char status; 502 503 channel = ZILOG_CHANNEL_FROM_PORT(port); 504 status = readb(&channel->control); 505 ZSDELAY(); 506 507 return status; 508} 509 510/* The port lock is not held. */ 511static unsigned int ip22zilog_tx_empty(struct uart_port *port) 512{ 513 unsigned long flags; 514 unsigned char status; 515 unsigned int ret; 516 517 spin_lock_irqsave(&port->lock, flags); 518 519 status = ip22zilog_read_channel_status(port); 520 521 spin_unlock_irqrestore(&port->lock, flags); 522 523 if (status & Tx_BUF_EMP) 524 ret = TIOCSER_TEMT; 525 else 526 ret = 0; 527 528 return ret; 529} 530 531/* The port lock is held and interrupts are disabled. */ 532static unsigned int ip22zilog_get_mctrl(struct uart_port *port) 533{ 534 unsigned char status; 535 unsigned int ret; 536 537 status = ip22zilog_read_channel_status(port); 538 539 ret = 0; 540 if (status & DCD) 541 ret |= TIOCM_CAR; 542 if (status & SYNC) 543 ret |= TIOCM_DSR; 544 if (status & CTS) 545 ret |= TIOCM_CTS; 546 547 return ret; 548} 549 550/* The port lock is held and interrupts are disabled. */ 551static void ip22zilog_set_mctrl(struct uart_port *port, unsigned int mctrl) 552{ 553 struct uart_ip22zilog_port *up = (struct uart_ip22zilog_port *) port; 554 struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(port); 555 unsigned char set_bits, clear_bits; 556 557 set_bits = clear_bits = 0; 558 559 if (mctrl & TIOCM_RTS) 560 set_bits |= RTS; 561 else 562 clear_bits |= RTS; 563 if (mctrl & TIOCM_DTR) 564 set_bits |= DTR; 565 else 566 clear_bits |= DTR; 567 568 /* NOTE: Not subject to 'transmitter active' rule. */ 569 up->curregs[R5] |= set_bits; 570 up->curregs[R5] &= ~clear_bits; 571 write_zsreg(channel, R5, up->curregs[R5]); 572} 573 574/* The port lock is held and interrupts are disabled. */ 575static void ip22zilog_stop_tx(struct uart_port *port) 576{ 577 struct uart_ip22zilog_port *up = (struct uart_ip22zilog_port *) port; 578 579 up->flags |= IP22ZILOG_FLAG_TX_STOPPED; 580} 581 582/* The port lock is held and interrupts are disabled. */ 583static void ip22zilog_start_tx(struct uart_port *port) 584{ 585 struct uart_ip22zilog_port *up = (struct uart_ip22zilog_port *) port; 586 struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(port); 587 unsigned char status; 588 589 up->flags |= IP22ZILOG_FLAG_TX_ACTIVE; 590 up->flags &= ~IP22ZILOG_FLAG_TX_STOPPED; 591 592 status = readb(&channel->control); 593 ZSDELAY(); 594 595 /* TX busy? Just wait for the TX done interrupt. */ 596 if (!(status & Tx_BUF_EMP)) 597 return; 598 599 /* Send the first character to jump-start the TX done 600 * IRQ sending engine. 601 */ 602 if (port->x_char) { 603 writeb(port->x_char, &channel->data); 604 ZSDELAY(); 605 ZS_WSYNC(channel); 606 607 port->icount.tx++; 608 port->x_char = 0; 609 } else { 610 struct circ_buf *xmit = &port->info->xmit; 611 612 writeb(xmit->buf[xmit->tail], &channel->data); 613 ZSDELAY(); 614 ZS_WSYNC(channel); 615 616 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 617 port->icount.tx++; 618 619 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 620 uart_write_wakeup(&up->port); 621 } 622} 623 624/* The port lock is held and interrupts are disabled. */ 625static void ip22zilog_stop_rx(struct uart_port *port) 626{ 627 struct uart_ip22zilog_port *up = UART_ZILOG(port); 628 struct zilog_channel *channel; 629 630 if (ZS_IS_CONS(up)) 631 return; 632 633 channel = ZILOG_CHANNEL_FROM_PORT(port); 634 635 /* Disable all RX interrupts. */ 636 up->curregs[R1] &= ~RxINT_MASK; 637 ip22zilog_maybe_update_regs(up, channel); 638} 639 640/* The port lock is held. */ 641static void ip22zilog_enable_ms(struct uart_port *port) 642{ 643 struct uart_ip22zilog_port *up = (struct uart_ip22zilog_port *) port; 644 struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(port); 645 unsigned char new_reg; 646 647 new_reg = up->curregs[R15] | (DCDIE | SYNCIE | CTSIE); 648 if (new_reg != up->curregs[R15]) { 649 up->curregs[R15] = new_reg; 650 651 /* NOTE: Not subject to 'transmitter active' rule. */ 652 write_zsreg(channel, R15, up->curregs[R15]); 653 } 654} 655 656/* The port lock is not held. */ 657static void ip22zilog_break_ctl(struct uart_port *port, int break_state) 658{ 659 struct uart_ip22zilog_port *up = (struct uart_ip22zilog_port *) port; 660 struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(port); 661 unsigned char set_bits, clear_bits, new_reg; 662 unsigned long flags; 663 664 set_bits = clear_bits = 0; 665 666 if (break_state) 667 set_bits |= SND_BRK; 668 else 669 clear_bits |= SND_BRK; 670 671 spin_lock_irqsave(&port->lock, flags); 672 673 new_reg = (up->curregs[R5] | set_bits) & ~clear_bits; 674 if (new_reg != up->curregs[R5]) { 675 up->curregs[R5] = new_reg; 676 677 /* NOTE: Not subject to 'transmitter active' rule. */ 678 write_zsreg(channel, R5, up->curregs[R5]); 679 } 680 681 spin_unlock_irqrestore(&port->lock, flags); 682} 683 684static void __ip22zilog_startup(struct uart_ip22zilog_port *up) 685{ 686 struct zilog_channel *channel; 687 688 channel = ZILOG_CHANNEL_FROM_PORT(&up->port); 689 up->prev_status = readb(&channel->control); 690 691 /* Enable receiver and transmitter. */ 692 up->curregs[R3] |= RxENAB; 693 up->curregs[R5] |= TxENAB; 694 695 up->curregs[R1] |= EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB; 696 ip22zilog_maybe_update_regs(up, channel); 697} 698 699static int ip22zilog_startup(struct uart_port *port) 700{ 701 struct uart_ip22zilog_port *up = UART_ZILOG(port); 702 unsigned long flags; 703 704 if (ZS_IS_CONS(up)) 705 return 0; 706 707 spin_lock_irqsave(&port->lock, flags); 708 __ip22zilog_startup(up); 709 spin_unlock_irqrestore(&port->lock, flags); 710 return 0; 711} 712 713/* 714 * The test for ZS_IS_CONS is explained by the following e-mail: 715 ***** 716 * From: Russell King <rmk@arm.linux.org.uk> 717 * Date: Sun, 8 Dec 2002 10:18:38 +0000 718 * 719 * On Sun, Dec 08, 2002 at 02:43:36AM -0500, Pete Zaitcev wrote: 720 * > I boot my 2.5 boxes using "console=ttyS0,9600" argument, 721 * > and I noticed that something is not right with reference 722 * > counting in this case. It seems that when the console 723 * > is open by kernel initially, this is not accounted 724 * > as an open, and uart_startup is not called. 725 * 726 * That is correct. We are unable to call uart_startup when the serial 727 * console is initialised because it may need to allocate memory (as 728 * request_irq does) and the memory allocators may not have been 729 * initialised. 730 * 731 * 1. initialise the port into a state where it can send characters in the 732 * console write method. 733 * 734 * 2. don't do the actual hardware shutdown in your shutdown() method (but 735 * do the normal software shutdown - ie, free irqs etc) 736 ***** 737 */ 738static void ip22zilog_shutdown(struct uart_port *port) 739{ 740 struct uart_ip22zilog_port *up = UART_ZILOG(port); 741 struct zilog_channel *channel; 742 unsigned long flags; 743 744 if (ZS_IS_CONS(up)) 745 return; 746 747 spin_lock_irqsave(&port->lock, flags); 748 749 channel = ZILOG_CHANNEL_FROM_PORT(port); 750 751 /* Disable receiver and transmitter. */ 752 up->curregs[R3] &= ~RxENAB; 753 up->curregs[R5] &= ~TxENAB; 754 755 /* Disable all interrupts and BRK assertion. */ 756 up->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK); 757 up->curregs[R5] &= ~SND_BRK; 758 ip22zilog_maybe_update_regs(up, channel); 759 760 spin_unlock_irqrestore(&port->lock, flags); 761} 762 763/* Shared by TTY driver and serial console setup. The port lock is held 764 * and local interrupts are disabled. 765 */ 766static void 767ip22zilog_convert_to_zs(struct uart_ip22zilog_port *up, unsigned int cflag, 768 unsigned int iflag, int brg) 769{ 770 771 up->curregs[R10] = NRZ; 772 up->curregs[R11] = TCBR | RCBR; 773 774 /* Program BAUD and clock source. */ 775 up->curregs[R4] &= ~XCLK_MASK; 776 up->curregs[R4] |= X16CLK; 777 up->curregs[R12] = brg & 0xff; 778 up->curregs[R13] = (brg >> 8) & 0xff; 779 up->curregs[R14] = BRENAB; 780 781 /* Character size, stop bits, and parity. */ 782 up->curregs[3] &= ~RxN_MASK; 783 up->curregs[5] &= ~TxN_MASK; 784 switch (cflag & CSIZE) { 785 case CS5: 786 up->curregs[3] |= Rx5; 787 up->curregs[5] |= Tx5; 788 up->parity_mask = 0x1f; 789 break; 790 case CS6: 791 up->curregs[3] |= Rx6; 792 up->curregs[5] |= Tx6; 793 up->parity_mask = 0x3f; 794 break; 795 case CS7: 796 up->curregs[3] |= Rx7; 797 up->curregs[5] |= Tx7; 798 up->parity_mask = 0x7f; 799 break; 800 case CS8: 801 default: 802 up->curregs[3] |= Rx8; 803 up->curregs[5] |= Tx8; 804 up->parity_mask = 0xff; 805 break; 806 }; 807 up->curregs[4] &= ~0x0c; 808 if (cflag & CSTOPB) 809 up->curregs[4] |= SB2; 810 else 811 up->curregs[4] |= SB1; 812 if (cflag & PARENB) 813 up->curregs[4] |= PAR_ENAB; 814 else 815 up->curregs[4] &= ~PAR_ENAB; 816 if (!(cflag & PARODD)) 817 up->curregs[4] |= PAR_EVEN; 818 else 819 up->curregs[4] &= ~PAR_EVEN; 820 821 up->port.read_status_mask = Rx_OVR; 822 if (iflag & INPCK) 823 up->port.read_status_mask |= CRC_ERR | PAR_ERR; 824 if (iflag & (BRKINT | PARMRK)) 825 up->port.read_status_mask |= BRK_ABRT; 826 827 up->port.ignore_status_mask = 0; 828 if (iflag & IGNPAR) 829 up->port.ignore_status_mask |= CRC_ERR | PAR_ERR; 830 if (iflag & IGNBRK) { 831 up->port.ignore_status_mask |= BRK_ABRT; 832 if (iflag & IGNPAR) 833 up->port.ignore_status_mask |= Rx_OVR; 834 } 835 836 if ((cflag & CREAD) == 0) 837 up->port.ignore_status_mask = 0xff; 838} 839 840/* The port lock is not held. */ 841static void 842ip22zilog_set_termios(struct uart_port *port, struct ktermios *termios, 843 struct ktermios *old) 844{ 845 struct uart_ip22zilog_port *up = (struct uart_ip22zilog_port *) port; 846 unsigned long flags; 847 int baud, brg; 848 849 baud = uart_get_baud_rate(port, termios, old, 1200, 76800); 850 851 spin_lock_irqsave(&up->port.lock, flags); 852 853 brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR); 854 855 ip22zilog_convert_to_zs(up, termios->c_cflag, termios->c_iflag, brg); 856 857 if (UART_ENABLE_MS(&up->port, termios->c_cflag)) 858 up->flags |= IP22ZILOG_FLAG_MODEM_STATUS; 859 else 860 up->flags &= ~IP22ZILOG_FLAG_MODEM_STATUS; 861 862 up->cflag = termios->c_cflag; 863 864 ip22zilog_maybe_update_regs(up, ZILOG_CHANNEL_FROM_PORT(port)); 865 uart_update_timeout(port, termios->c_cflag, baud); 866 867 spin_unlock_irqrestore(&up->port.lock, flags); 868} 869 870static const char *ip22zilog_type(struct uart_port *port) 871{ 872 return "IP22-Zilog"; 873} 874 875/* We do not request/release mappings of the registers here, this 876 * happens at early serial probe time. 877 */ 878static void ip22zilog_release_port(struct uart_port *port) 879{ 880} 881 882static int ip22zilog_request_port(struct uart_port *port) 883{ 884 return 0; 885} 886 887/* These do not need to do anything interesting either. */ 888static void ip22zilog_config_port(struct uart_port *port, int flags) 889{ 890} 891 892/* We do not support letting the user mess with the divisor, IRQ, etc. */ 893static int ip22zilog_verify_port(struct uart_port *port, struct serial_struct *ser) 894{ 895 return -EINVAL; 896} 897 898static struct uart_ops ip22zilog_pops = { 899 .tx_empty = ip22zilog_tx_empty, 900 .set_mctrl = ip22zilog_set_mctrl, 901 .get_mctrl = ip22zilog_get_mctrl, 902 .stop_tx = ip22zilog_stop_tx, 903 .start_tx = ip22zilog_start_tx, 904 .stop_rx = ip22zilog_stop_rx, 905 .enable_ms = ip22zilog_enable_ms, 906 .break_ctl = ip22zilog_break_ctl, 907 .startup = ip22zilog_startup, 908 .shutdown = ip22zilog_shutdown, 909 .set_termios = ip22zilog_set_termios, 910 .type = ip22zilog_type, 911 .release_port = ip22zilog_release_port, 912 .request_port = ip22zilog_request_port, 913 .config_port = ip22zilog_config_port, 914 .verify_port = ip22zilog_verify_port, 915}; 916 917static struct uart_ip22zilog_port *ip22zilog_port_table; 918static struct zilog_layout **ip22zilog_chip_regs; 919 920static struct uart_ip22zilog_port *ip22zilog_irq_chain; 921static int zilog_irq = -1; 922 923static void * __init alloc_one_table(unsigned long size) 924{ 925 return kzalloc(size, GFP_KERNEL); 926} 927 928static void __init ip22zilog_alloc_tables(void) 929{ 930 ip22zilog_port_table = (struct uart_ip22zilog_port *) 931 alloc_one_table(NUM_CHANNELS * sizeof(struct uart_ip22zilog_port)); 932 ip22zilog_chip_regs = (struct zilog_layout **) 933 alloc_one_table(NUM_IP22ZILOG * sizeof(struct zilog_layout *)); 934 935 if (ip22zilog_port_table == NULL || ip22zilog_chip_regs == NULL) { 936 panic("IP22-Zilog: Cannot allocate IP22-Zilog tables."); 937 } 938} 939 940/* Get the address of the registers for IP22-Zilog instance CHIP. */ 941static struct zilog_layout * __init get_zs(int chip) 942{ 943 unsigned long base; 944 945 if (chip < 0 || chip >= NUM_IP22ZILOG) { 946 panic("IP22-Zilog: Illegal chip number %d in get_zs.", chip); 947 } 948 949 /* Not probe-able, hard code it. */ 950 base = (unsigned long) &sgioc->uart; 951 952 zilog_irq = SGI_SERIAL_IRQ; 953 request_mem_region(base, 8, "IP22-Zilog"); 954 955 return (struct zilog_layout *) base; 956} 957 958#define ZS_PUT_CHAR_MAX_DELAY 2000 /* 10 ms */ 959 960#ifdef CONFIG_SERIAL_IP22_ZILOG_CONSOLE 961static void ip22zilog_put_char(struct uart_port *port, int ch) 962{ 963 struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(port); 964 int loops = ZS_PUT_CHAR_MAX_DELAY; 965 966 /* This is a timed polling loop so do not switch the explicit 967 * udelay with ZSDELAY as that is a NOP on some platforms. -DaveM 968 */ 969 do { 970 unsigned char val = readb(&channel->control); 971 if (val & Tx_BUF_EMP) { 972 ZSDELAY(); 973 break; 974 } 975 udelay(5); 976 } while (--loops); 977 978 writeb(ch, &channel->data); 979 ZSDELAY(); 980 ZS_WSYNC(channel); 981} 982 983static void 984ip22zilog_console_write(struct console *con, const char *s, unsigned int count) 985{ 986 struct uart_ip22zilog_port *up = &ip22zilog_port_table[con->index]; 987 unsigned long flags; 988 989 spin_lock_irqsave(&up->port.lock, flags); 990 uart_console_write(&up->port, s, count, ip22zilog_put_char); 991 udelay(2); 992 spin_unlock_irqrestore(&up->port.lock, flags); 993} 994 995void 996ip22serial_console_termios(struct console *con, char *options) 997{ 998 int baud = 9600, bits = 8, cflag; 999 int parity = 'n'; 1000 int flow = 'n'; 1001 1002 if (options) 1003 uart_parse_options(options, &baud, &parity, &bits, &flow); 1004 1005 cflag = CREAD | HUPCL | CLOCAL; 1006 1007 switch (baud) { 1008 case 150: cflag |= B150; break; 1009 case 300: cflag |= B300; break; 1010 case 600: cflag |= B600; break; 1011 case 1200: cflag |= B1200; break; 1012 case 2400: cflag |= B2400; break; 1013 case 4800: cflag |= B4800; break; 1014 case 9600: cflag |= B9600; break; 1015 case 19200: cflag |= B19200; break; 1016 case 38400: cflag |= B38400; break; 1017 default: baud = 9600; cflag |= B9600; break; 1018 } 1019 1020 con->cflag = cflag | CS8; /* 8N1 */ 1021 1022 uart_update_timeout(&ip22zilog_port_table[con->index].port, cflag, baud); 1023} 1024 1025static int __init ip22zilog_console_setup(struct console *con, char *options) 1026{ 1027 struct uart_ip22zilog_port *up = &ip22zilog_port_table[con->index]; 1028 unsigned long flags; 1029 int baud, brg; 1030 1031 printk("Console: ttyS%d (IP22-Zilog)\n", con->index); 1032 1033 /* Get firmware console settings. */ 1034 ip22serial_console_termios(con, options); 1035 1036 /* Firmware console speed is limited to 150-->38400 baud so 1037 * this hackish cflag thing is OK. 1038 */ 1039 switch (con->cflag & CBAUD) { 1040 case B150: baud = 150; break; 1041 case B300: baud = 300; break; 1042 case B600: baud = 600; break; 1043 case B1200: baud = 1200; break; 1044 case B2400: baud = 2400; break; 1045 case B4800: baud = 4800; break; 1046 default: case B9600: baud = 9600; break; 1047 case B19200: baud = 19200; break; 1048 case B38400: baud = 38400; break; 1049 }; 1050 1051 brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR); 1052 1053 spin_lock_irqsave(&up->port.lock, flags); 1054 1055 up->curregs[R15] = BRKIE; 1056 ip22zilog_convert_to_zs(up, con->cflag, 0, brg); 1057 1058 __ip22zilog_startup(up); 1059 1060 spin_unlock_irqrestore(&up->port.lock, flags); 1061 1062 return 0; 1063} 1064 1065static struct uart_driver ip22zilog_reg; 1066 1067static struct console ip22zilog_console = { 1068 .name = "ttyS", 1069 .write = ip22zilog_console_write, 1070 .device = uart_console_device, 1071 .setup = ip22zilog_console_setup, 1072 .flags = CON_PRINTBUFFER, 1073 .index = -1, 1074 .data = &ip22zilog_reg, 1075}; 1076#endif /* CONFIG_SERIAL_IP22_ZILOG_CONSOLE */ 1077 1078static struct uart_driver ip22zilog_reg = { 1079 .owner = THIS_MODULE, 1080 .driver_name = "serial", 1081 .dev_name = "ttyS", 1082 .major = TTY_MAJOR, 1083 .minor = 64, 1084 .nr = NUM_CHANNELS, 1085#ifdef CONFIG_SERIAL_IP22_ZILOG_CONSOLE 1086 .cons = &ip22zilog_console, 1087#endif 1088}; 1089 1090static void __init ip22zilog_prepare(void) 1091{ 1092 struct uart_ip22zilog_port *up; 1093 struct zilog_layout *rp; 1094 int channel, chip; 1095 1096 /* 1097 * Temporary fix. 1098 */ 1099 for (channel = 0; channel < NUM_CHANNELS; channel++) 1100 spin_lock_init(&ip22zilog_port_table[channel].port.lock); 1101 1102 ip22zilog_irq_chain = &ip22zilog_port_table[NUM_CHANNELS - 1]; 1103 up = &ip22zilog_port_table[0]; 1104 for (channel = NUM_CHANNELS - 1 ; channel > 0; channel--) 1105 up[channel].next = &up[channel - 1]; 1106 up[channel].next = NULL; 1107 1108 for (chip = 0; chip < NUM_IP22ZILOG; chip++) { 1109 if (!ip22zilog_chip_regs[chip]) { 1110 ip22zilog_chip_regs[chip] = rp = get_zs(chip); 1111 1112 up[(chip * 2) + 0].port.membase = (char *) &rp->channelB; 1113 up[(chip * 2) + 1].port.membase = (char *) &rp->channelA; 1114 1115 /* In theory mapbase is the physical address ... */ 1116 up[(chip * 2) + 0].port.mapbase = 1117 (unsigned long) ioremap((unsigned long) &rp->channelB, 8); 1118 up[(chip * 2) + 1].port.mapbase = 1119 (unsigned long) ioremap((unsigned long) &rp->channelA, 8); 1120 } 1121 1122 /* Channel A */ 1123 up[(chip * 2) + 0].port.iotype = UPIO_MEM; 1124 up[(chip * 2) + 0].port.irq = zilog_irq; 1125 up[(chip * 2) + 0].port.uartclk = ZS_CLOCK; 1126 up[(chip * 2) + 0].port.fifosize = 1; 1127 up[(chip * 2) + 0].port.ops = &ip22zilog_pops; 1128 up[(chip * 2) + 0].port.type = PORT_IP22ZILOG; 1129 up[(chip * 2) + 0].port.flags = 0; 1130 up[(chip * 2) + 0].port.line = (chip * 2) + 0; 1131 up[(chip * 2) + 0].flags = 0; 1132 1133 /* Channel B */ 1134 up[(chip * 2) + 1].port.iotype = UPIO_MEM; 1135 up[(chip * 2) + 1].port.irq = zilog_irq; 1136 up[(chip * 2) + 1].port.uartclk = ZS_CLOCK; 1137 up[(chip * 2) + 1].port.fifosize = 1; 1138 up[(chip * 2) + 1].port.ops = &ip22zilog_pops; 1139 up[(chip * 2) + 1].port.type = PORT_IP22ZILOG; 1140 up[(chip * 2) + 1].port.line = (chip * 2) + 1; 1141 up[(chip * 2) + 1].flags |= IP22ZILOG_FLAG_IS_CHANNEL_A; 1142 } 1143} 1144 1145static void __init ip22zilog_init_hw(void) 1146{ 1147 int i; 1148 1149 for (i = 0; i < NUM_CHANNELS; i++) { 1150 struct uart_ip22zilog_port *up = &ip22zilog_port_table[i]; 1151 struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(&up->port); 1152 unsigned long flags; 1153 int baud, brg; 1154 1155 spin_lock_irqsave(&up->port.lock, flags); 1156 1157 if (ZS_IS_CHANNEL_A(up)) { 1158 write_zsreg(channel, R9, FHWRES); 1159 ZSDELAY_LONG(); 1160 (void) read_zsreg(channel, R0); 1161 } 1162 1163 /* Normal serial TTY. */ 1164 up->parity_mask = 0xff; 1165 up->curregs[R1] = EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB; 1166 up->curregs[R4] = PAR_EVEN | X16CLK | SB1; 1167 up->curregs[R3] = RxENAB | Rx8; 1168 up->curregs[R5] = TxENAB | Tx8; 1169 up->curregs[R9] = NV | MIE; 1170 up->curregs[R10] = NRZ; 1171 up->curregs[R11] = TCBR | RCBR; 1172 baud = 9600; 1173 brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR); 1174 up->curregs[R12] = (brg & 0xff); 1175 up->curregs[R13] = (brg >> 8) & 0xff; 1176 up->curregs[R14] = BRENAB; 1177 __load_zsregs(channel, up->curregs); 1178 /* set master interrupt enable */ 1179 write_zsreg(channel, R9, up->curregs[R9]); 1180 1181 spin_unlock_irqrestore(&up->port.lock, flags); 1182 } 1183} 1184 1185static int __init ip22zilog_ports_init(void) 1186{ 1187 int ret; 1188 1189 printk(KERN_INFO "Serial: IP22 Zilog driver (%d chips).\n", NUM_IP22ZILOG); 1190 1191 ip22zilog_prepare(); 1192 1193 if (request_irq(zilog_irq, ip22zilog_interrupt, 0, 1194 "IP22-Zilog", ip22zilog_irq_chain)) { 1195 panic("IP22-Zilog: Unable to register zs interrupt handler.\n"); 1196 } 1197 1198 ip22zilog_init_hw(); 1199 1200 ret = uart_register_driver(&ip22zilog_reg); 1201 if (ret == 0) { 1202 int i; 1203 1204 for (i = 0; i < NUM_CHANNELS; i++) { 1205 struct uart_ip22zilog_port *up = &ip22zilog_port_table[i]; 1206 1207 uart_add_one_port(&ip22zilog_reg, &up->port); 1208 } 1209 } 1210 1211 return ret; 1212} 1213 1214static int __init ip22zilog_init(void) 1215{ 1216 /* IP22 Zilog setup is hard coded, no probing to do. */ 1217 ip22zilog_alloc_tables(); 1218 ip22zilog_ports_init(); 1219 1220 return 0; 1221} 1222 1223static void __exit ip22zilog_exit(void) 1224{ 1225 int i; 1226 struct uart_ip22zilog_port *up; 1227 1228 for (i = 0; i < NUM_CHANNELS; i++) { 1229 up = &ip22zilog_port_table[i]; 1230 1231 uart_remove_one_port(&ip22zilog_reg, &up->port); 1232 } 1233 1234 /* Free IO mem */ 1235 up = &ip22zilog_port_table[0]; 1236 for (i = 0; i < NUM_IP22ZILOG; i++) { 1237 if (up[(i * 2) + 0].port.mapbase) { 1238 iounmap((void*)up[(i * 2) + 0].port.mapbase); 1239 up[(i * 2) + 0].port.mapbase = 0; 1240 } 1241 if (up[(i * 2) + 1].port.mapbase) { 1242 iounmap((void*)up[(i * 2) + 1].port.mapbase); 1243 up[(i * 2) + 1].port.mapbase = 0; 1244 } 1245 } 1246 1247 uart_unregister_driver(&ip22zilog_reg); 1248} 1249 1250module_init(ip22zilog_init); 1251module_exit(ip22zilog_exit); 1252 1253/* David wrote it but I'm to blame for the bugs ... */ 1254MODULE_AUTHOR("Ralf Baechle <ralf@linux-mips.org>"); 1255MODULE_DESCRIPTION("SGI Zilog serial port driver"); 1256MODULE_LICENSE("GPL"); 1257