1/* 2 * QLogic Fibre Channel HBA Driver 3 * Copyright (c) 2003-2005 QLogic Corporation 4 * 5 * See LICENSE.qla2xxx for copyright and licensing details. 6 */ 7/* 8 * Driver debug definitions. 9 */ 10/* #define QL_DEBUG_LEVEL_1 */ /* Output register accesses to COM1 */ 11/* #define QL_DEBUG_LEVEL_2 */ /* Output error msgs to COM1 */ 12/* #define QL_DEBUG_LEVEL_3 */ /* Output function trace msgs to COM1 */ 13/* #define QL_DEBUG_LEVEL_4 */ /* Output NVRAM trace msgs to COM1 */ 14/* #define QL_DEBUG_LEVEL_5 */ /* Output ring trace msgs to COM1 */ 15/* #define QL_DEBUG_LEVEL_6 */ /* Output WATCHDOG timer trace to COM1 */ 16/* #define QL_DEBUG_LEVEL_7 */ /* Output RISC load trace msgs to COM1 */ 17/* #define QL_DEBUG_LEVEL_8 */ /* Output ring saturation msgs to COM1 */ 18/* #define QL_DEBUG_LEVEL_9 */ /* Output IOCTL trace msgs */ 19/* #define QL_DEBUG_LEVEL_10 */ /* Output IOCTL error msgs */ 20/* #define QL_DEBUG_LEVEL_11 */ /* Output Mbx Cmd trace msgs */ 21/* #define QL_DEBUG_LEVEL_12 */ /* Output IP trace msgs */ 22/* #define QL_DEBUG_LEVEL_13 */ /* Output fdmi function trace msgs */ 23/* #define QL_DEBUG_LEVEL_14 */ /* Output RSCN trace msgs */ 24/* 25 * Local Macro Definitions. 26 */ 27#if defined(QL_DEBUG_LEVEL_1) || defined(QL_DEBUG_LEVEL_2) || \ 28 defined(QL_DEBUG_LEVEL_3) || defined(QL_DEBUG_LEVEL_4) || defined(QL_DEBUG_LEVEL_5) || \ 29 defined(QL_DEBUG_LEVEL_6) || defined(QL_DEBUG_LEVEL_7) || defined(QL_DEBUG_LEVEL_8) || \ 30 defined(QL_DEBUG_LEVEL_9) || defined(QL_DEBUG_LEVEL_10) || defined(QL_DEBUG_LEVEL_11) \ 31 || defined(QL_DEBUG_LEVEL_12) || defined(QL_DEBUG_LEVEL_13) || \ 32 defined(QL_DEBUG_LEVEL_14) 33 #define QL_DEBUG_ROUTINES 34#endif 35 36/* 37* Macros use for debugging the driver. 38*/ 39 40#define DEBUG(x) do { if (ql2xextended_error_logging) { x; } } while (0) 41 42#if defined(QL_DEBUG_LEVEL_1) 43#define DEBUG1(x) do {x;} while (0) 44#else 45#define DEBUG1(x) do {} while (0) 46#endif 47 48#define DEBUG2(x) do { if (ql2xextended_error_logging) { x; } } while (0) 49#define DEBUG2_3(x) do { if (ql2xextended_error_logging) { x; } } while (0) 50#define DEBUG2_3_11(x) do { if (ql2xextended_error_logging) { x; } } while (0) 51#define DEBUG2_9_10(x) do { if (ql2xextended_error_logging) { x; } } while (0) 52#define DEBUG2_11(x) do { if (ql2xextended_error_logging) { x; } } while (0) 53#define DEBUG2_13(x) do { if (ql2xextended_error_logging) { x; } } while (0) 54 55#if defined(QL_DEBUG_LEVEL_3) 56#define DEBUG3(x) do {x;} while (0) 57#define DEBUG3_11(x) do {x;} while (0) 58#else 59#define DEBUG3(x) do {} while (0) 60#endif 61 62#if defined(QL_DEBUG_LEVEL_4) 63#define DEBUG4(x) do {x;} while (0) 64#else 65#define DEBUG4(x) do {} while (0) 66#endif 67 68#if defined(QL_DEBUG_LEVEL_5) 69#define DEBUG5(x) do {x;} while (0) 70#else 71#define DEBUG5(x) do {} while (0) 72#endif 73 74#if defined(QL_DEBUG_LEVEL_7) 75#define DEBUG7(x) do {x;} while (0) 76#else 77#define DEBUG7(x) do {} while (0) 78#endif 79 80#if defined(QL_DEBUG_LEVEL_9) 81#define DEBUG9(x) do {x;} while (0) 82#define DEBUG9_10(x) do {x;} while (0) 83#else 84#define DEBUG9(x) do {} while (0) 85#endif 86 87#if defined(QL_DEBUG_LEVEL_10) 88#define DEBUG10(x) do {x;} while (0) 89#define DEBUG9_10(x) do {x;} while (0) 90#else 91#define DEBUG10(x) do {} while (0) 92 #if !defined(DEBUG9_10) 93 #define DEBUG9_10(x) do {} while (0) 94 #endif 95#endif 96 97#if defined(QL_DEBUG_LEVEL_11) 98#define DEBUG11(x) do{x;} while(0) 99#if !defined(DEBUG3_11) 100#define DEBUG3_11(x) do{x;} while(0) 101#endif 102#else 103#define DEBUG11(x) do{} while(0) 104 #if !defined(QL_DEBUG_LEVEL_3) 105 #define DEBUG3_11(x) do{} while(0) 106 #endif 107#endif 108 109#if defined(QL_DEBUG_LEVEL_12) 110#define DEBUG12(x) do {x;} while (0) 111#else 112#define DEBUG12(x) do {} while (0) 113#endif 114 115#if defined(QL_DEBUG_LEVEL_13) 116#define DEBUG13(x) do {x;} while (0) 117#else 118#define DEBUG13(x) do {} while (0) 119#endif 120 121#if defined(QL_DEBUG_LEVEL_14) 122#define DEBUG14(x) do {x;} while (0) 123#else 124#define DEBUG14(x) do {} while (0) 125#endif 126 127/* 128 * Firmware Dump structure definition 129 */ 130 131struct qla2300_fw_dump { 132 uint16_t hccr; 133 uint16_t pbiu_reg[8]; 134 uint16_t risc_host_reg[8]; 135 uint16_t mailbox_reg[32]; 136 uint16_t resp_dma_reg[32]; 137 uint16_t dma_reg[48]; 138 uint16_t risc_hdw_reg[16]; 139 uint16_t risc_gp0_reg[16]; 140 uint16_t risc_gp1_reg[16]; 141 uint16_t risc_gp2_reg[16]; 142 uint16_t risc_gp3_reg[16]; 143 uint16_t risc_gp4_reg[16]; 144 uint16_t risc_gp5_reg[16]; 145 uint16_t risc_gp6_reg[16]; 146 uint16_t risc_gp7_reg[16]; 147 uint16_t frame_buf_hdw_reg[64]; 148 uint16_t fpm_b0_reg[64]; 149 uint16_t fpm_b1_reg[64]; 150 uint16_t risc_ram[0xf800]; 151 uint16_t stack_ram[0x1000]; 152 uint16_t data_ram[1]; 153}; 154 155struct qla2100_fw_dump { 156 uint16_t hccr; 157 uint16_t pbiu_reg[8]; 158 uint16_t mailbox_reg[32]; 159 uint16_t dma_reg[48]; 160 uint16_t risc_hdw_reg[16]; 161 uint16_t risc_gp0_reg[16]; 162 uint16_t risc_gp1_reg[16]; 163 uint16_t risc_gp2_reg[16]; 164 uint16_t risc_gp3_reg[16]; 165 uint16_t risc_gp4_reg[16]; 166 uint16_t risc_gp5_reg[16]; 167 uint16_t risc_gp6_reg[16]; 168 uint16_t risc_gp7_reg[16]; 169 uint16_t frame_buf_hdw_reg[16]; 170 uint16_t fpm_b0_reg[64]; 171 uint16_t fpm_b1_reg[64]; 172 uint16_t risc_ram[0xf000]; 173}; 174 175struct qla24xx_fw_dump { 176 uint32_t host_status; 177 uint32_t host_reg[32]; 178 uint32_t shadow_reg[7]; 179 uint16_t mailbox_reg[32]; 180 uint32_t xseq_gp_reg[128]; 181 uint32_t xseq_0_reg[16]; 182 uint32_t xseq_1_reg[16]; 183 uint32_t rseq_gp_reg[128]; 184 uint32_t rseq_0_reg[16]; 185 uint32_t rseq_1_reg[16]; 186 uint32_t rseq_2_reg[16]; 187 uint32_t cmd_dma_reg[16]; 188 uint32_t req0_dma_reg[15]; 189 uint32_t resp0_dma_reg[15]; 190 uint32_t req1_dma_reg[15]; 191 uint32_t xmt0_dma_reg[32]; 192 uint32_t xmt1_dma_reg[32]; 193 uint32_t xmt2_dma_reg[32]; 194 uint32_t xmt3_dma_reg[32]; 195 uint32_t xmt4_dma_reg[32]; 196 uint32_t xmt_data_dma_reg[16]; 197 uint32_t rcvt0_data_dma_reg[32]; 198 uint32_t rcvt1_data_dma_reg[32]; 199 uint32_t risc_gp_reg[128]; 200 uint32_t lmc_reg[112]; 201 uint32_t fpm_hdw_reg[192]; 202 uint32_t fb_hdw_reg[176]; 203 uint32_t code_ram[0x2000]; 204 uint32_t ext_mem[1]; 205}; 206 207#define EFT_NUM_BUFFERS 4 208#define EFT_BYTES_PER_BUFFER 0x4000 209#define EFT_SIZE ((EFT_BYTES_PER_BUFFER) * (EFT_NUM_BUFFERS)) 210 211struct qla2xxx_fw_dump { 212 uint8_t signature[4]; 213 uint32_t version; 214 215 uint32_t fw_major_version; 216 uint32_t fw_minor_version; 217 uint32_t fw_subminor_version; 218 uint32_t fw_attributes; 219 220 uint32_t vendor; 221 uint32_t device; 222 uint32_t subsystem_vendor; 223 uint32_t subsystem_device; 224 225 uint32_t fixed_size; 226 uint32_t mem_size; 227 uint32_t req_q_size; 228 uint32_t rsp_q_size; 229 230 uint32_t eft_size; 231 uint32_t eft_addr_l; 232 uint32_t eft_addr_h; 233 234 uint32_t header_size; 235 236 union { 237 struct qla2100_fw_dump isp21; 238 struct qla2300_fw_dump isp23; 239 struct qla24xx_fw_dump isp24; 240 } isp; 241}; 242