1/* fastlane.c: Driver for Phase5's Fastlane SCSI Controller. 2 * 3 * Copyright (C) 1996 Jesper Skov (jskov@cygnus.co.uk) 4 * 5 * This driver is based on the CyberStorm driver, hence the occasional 6 * reference to CyberStorm. 7 * 8 * Betatesting & crucial adjustments by 9 * Patrik Rak (prak3264@ss1000.ms.mff.cuni.cz) 10 * 11 */ 12 13/* TODO: 14 * 15 * o According to the doc from laire, it is required to reset the DMA when 16 * the transfer is done. ATM we reset DMA just before every new 17 * dma_init_(read|write). 18 * 19 * 1) Figure out how to make a cleaner merge with the sparc driver with regard 20 * to the caches and the Sparc MMU mapping. 21 * 2) Make as few routines required outside the generic driver. A lot of the 22 * routines in this file used to be inline! 23 */ 24 25#include <linux/module.h> 26 27#include <linux/init.h> 28#include <linux/kernel.h> 29#include <linux/delay.h> 30#include <linux/types.h> 31#include <linux/string.h> 32#include <linux/slab.h> 33#include <linux/blkdev.h> 34#include <linux/proc_fs.h> 35#include <linux/stat.h> 36#include <linux/interrupt.h> 37 38#include "scsi.h" 39#include <scsi/scsi_host.h> 40#include "NCR53C9x.h" 41 42#include <linux/zorro.h> 43#include <asm/irq.h> 44 45#include <asm/amigaints.h> 46#include <asm/amigahw.h> 47 48#include <asm/pgtable.h> 49 50/* Such day has just come... */ 51 52/* The controller registers can be found in the Z2 config area at these 53 * offsets: 54 */ 55#define FASTLANE_ESP_ADDR 0x1000001 56#define FASTLANE_DMA_ADDR 0x1000041 57 58 59/* The Fastlane DMA interface */ 60struct fastlane_dma_registers { 61 volatile unsigned char cond_reg; /* DMA status (ro) [0x0000] */ 62#define ctrl_reg cond_reg /* DMA control (wo) [0x0000] */ 63 unsigned char dmapad1[0x3f]; 64 volatile unsigned char clear_strobe; /* DMA clear (wo) [0x0040] */ 65}; 66 67 68/* DMA status bits */ 69#define FASTLANE_DMA_MINT 0x80 70#define FASTLANE_DMA_IACT 0x40 71#define FASTLANE_DMA_CREQ 0x20 72 73/* DMA control bits */ 74#define FASTLANE_DMA_FCODE 0xa0 75#define FASTLANE_DMA_MASK 0xf3 76#define FASTLANE_DMA_LED 0x10 /* HD led control 1 = on */ 77#define FASTLANE_DMA_WRITE 0x08 /* 1 = write */ 78#define FASTLANE_DMA_ENABLE 0x04 /* Enable DMA */ 79#define FASTLANE_DMA_EDI 0x02 /* Enable DMA IRQ ? */ 80#define FASTLANE_DMA_ESI 0x01 /* Enable SCSI IRQ */ 81 82static int dma_bytes_sent(struct NCR_ESP *esp, int fifo_count); 83static int dma_can_transfer(struct NCR_ESP *esp, Scsi_Cmnd *sp); 84static void dma_dump_state(struct NCR_ESP *esp); 85static void dma_init_read(struct NCR_ESP *esp, __u32 addr, int length); 86static void dma_init_write(struct NCR_ESP *esp, __u32 vaddr, int length); 87static void dma_ints_off(struct NCR_ESP *esp); 88static void dma_ints_on(struct NCR_ESP *esp); 89static int dma_irq_p(struct NCR_ESP *esp); 90static void dma_irq_exit(struct NCR_ESP *esp); 91static void dma_led_off(struct NCR_ESP *esp); 92static void dma_led_on(struct NCR_ESP *esp); 93static int dma_ports_p(struct NCR_ESP *esp); 94static void dma_setup(struct NCR_ESP *esp, __u32 addr, int count, int write); 95 96static unsigned char ctrl_data = 0; /* Keep backup of the stuff written 97 * to ctrl_reg. Always write a copy 98 * to this register when writing to 99 * the hardware register! 100 */ 101 102static volatile unsigned char cmd_buffer[16]; 103 /* This is where all commands are put 104 * before they are transferred to the ESP chip 105 * via PIO. 106 */ 107 108static inline void dma_clear(struct NCR_ESP *esp) 109{ 110 struct fastlane_dma_registers *dregs = 111 (struct fastlane_dma_registers *) (esp->dregs); 112 unsigned long *t; 113 114 ctrl_data = (ctrl_data & FASTLANE_DMA_MASK); 115 dregs->ctrl_reg = ctrl_data; 116 117 t = (unsigned long *)(esp->edev); 118 119 dregs->clear_strobe = 0; 120 *t = 0 ; 121} 122 123/***************************************************************** Detection */ 124int __init fastlane_esp_detect(struct scsi_host_template *tpnt) 125{ 126 struct NCR_ESP *esp; 127 struct zorro_dev *z = NULL; 128 unsigned long address; 129 130 if ((z = zorro_find_device(ZORRO_PROD_PHASE5_BLIZZARD_1230_II_FASTLANE_Z3_CYBERSCSI_CYBERSTORM060, z))) { 131 unsigned long board = z->resource.start; 132 if (request_mem_region(board+FASTLANE_ESP_ADDR, 133 sizeof(struct ESP_regs), "NCR53C9x")) { 134 /* Check if this is really a fastlane controller. The problem 135 * is that also the cyberstorm and blizzard controllers use 136 * this ID value. Fortunately only Fastlane maps in Z3 space 137 */ 138 if (board < 0x1000000) { 139 goto err_release; 140 } 141 esp = esp_allocate(tpnt, (void *)board + FASTLANE_ESP_ADDR, 0); 142 143 /* Do command transfer with programmed I/O */ 144 esp->do_pio_cmds = 1; 145 146 /* Required functions */ 147 esp->dma_bytes_sent = &dma_bytes_sent; 148 esp->dma_can_transfer = &dma_can_transfer; 149 esp->dma_dump_state = &dma_dump_state; 150 esp->dma_init_read = &dma_init_read; 151 esp->dma_init_write = &dma_init_write; 152 esp->dma_ints_off = &dma_ints_off; 153 esp->dma_ints_on = &dma_ints_on; 154 esp->dma_irq_p = &dma_irq_p; 155 esp->dma_ports_p = &dma_ports_p; 156 esp->dma_setup = &dma_setup; 157 158 /* Optional functions */ 159 esp->dma_barrier = 0; 160 esp->dma_drain = 0; 161 esp->dma_invalidate = 0; 162 esp->dma_irq_entry = 0; 163 esp->dma_irq_exit = &dma_irq_exit; 164 esp->dma_led_on = &dma_led_on; 165 esp->dma_led_off = &dma_led_off; 166 esp->dma_poll = 0; 167 esp->dma_reset = 0; 168 169 /* Initialize the portBits (enable IRQs) */ 170 ctrl_data = (FASTLANE_DMA_FCODE | 171#ifndef NODMAIRQ 172 FASTLANE_DMA_EDI | 173#endif 174 FASTLANE_DMA_ESI); 175 176 177 /* SCSI chip clock */ 178 esp->cfreq = 40000000; 179 180 181 /* Map the physical address space into virtual kernel space */ 182 address = (unsigned long) 183 z_ioremap(board, z->resource.end-board+1); 184 185 if(!address){ 186 printk("Could not remap Fastlane controller memory!"); 187 goto err_unregister; 188 } 189 190 191 /* The DMA registers on the Fastlane are mapped 192 * relative to the device (i.e. in the same Zorro 193 * I/O block). 194 */ 195 esp->dregs = (void *)(address + FASTLANE_DMA_ADDR); 196 197 /* ESP register base */ 198 esp->eregs = (struct ESP_regs *)(address + FASTLANE_ESP_ADDR); 199 200 /* Board base */ 201 esp->edev = (void *) address; 202 203 /* Set the command buffer */ 204 esp->esp_command = cmd_buffer; 205 esp->esp_command_dvma = virt_to_bus((void *)cmd_buffer); 206 207 esp->irq = IRQ_AMIGA_PORTS; 208 esp->slot = board+FASTLANE_ESP_ADDR; 209 if (request_irq(IRQ_AMIGA_PORTS, esp_intr, IRQF_SHARED, 210 "Fastlane SCSI", esp->ehost)) { 211 printk(KERN_WARNING "Fastlane: Could not get IRQ%d, aborting.\n", IRQ_AMIGA_PORTS); 212 goto err_unmap; 213 } 214 215 /* Controller ID */ 216 esp->scsi_id = 7; 217 218 /* We don't have a differential SCSI-bus. */ 219 esp->diff = 0; 220 221 dma_clear(esp); 222 esp_initialize(esp); 223 224 printk("ESP: Total of %d ESP hosts found, %d actually in use.\n", nesps, esps_in_use); 225 esps_running = esps_in_use; 226 return esps_in_use; 227 } 228 } 229 return 0; 230 231 err_unmap: 232 z_iounmap((void *)address); 233 err_unregister: 234 scsi_unregister (esp->ehost); 235 err_release: 236 release_mem_region(z->resource.start+FASTLANE_ESP_ADDR, 237 sizeof(struct ESP_regs)); 238 return 0; 239} 240 241 242/************************************************************* DMA Functions */ 243static int dma_bytes_sent(struct NCR_ESP *esp, int fifo_count) 244{ 245 return fifo_count; 246} 247 248static int dma_can_transfer(struct NCR_ESP *esp, Scsi_Cmnd *sp) 249{ 250 unsigned long sz = sp->SCp.this_residual; 251 if(sz > 0xfffc) 252 sz = 0xfffc; 253 return sz; 254} 255 256static void dma_dump_state(struct NCR_ESP *esp) 257{ 258 ESPLOG(("esp%d: dma -- cond_reg<%02x>\n", 259 esp->esp_id, ((struct fastlane_dma_registers *) 260 (esp->dregs))->cond_reg)); 261 ESPLOG(("intreq:<%04x>, intena:<%04x>\n", 262 amiga_custom.intreqr, amiga_custom.intenar)); 263} 264 265static void dma_init_read(struct NCR_ESP *esp, __u32 addr, int length) 266{ 267 struct fastlane_dma_registers *dregs = 268 (struct fastlane_dma_registers *) (esp->dregs); 269 unsigned long *t; 270 271 cache_clear(addr, length); 272 273 dma_clear(esp); 274 275 t = (unsigned long *)((addr & 0x00ffffff) + esp->edev); 276 277 dregs->clear_strobe = 0; 278 *t = addr; 279 280 ctrl_data = (ctrl_data & FASTLANE_DMA_MASK) | FASTLANE_DMA_ENABLE; 281 dregs->ctrl_reg = ctrl_data; 282} 283 284static void dma_init_write(struct NCR_ESP *esp, __u32 addr, int length) 285{ 286 struct fastlane_dma_registers *dregs = 287 (struct fastlane_dma_registers *) (esp->dregs); 288 unsigned long *t; 289 290 cache_push(addr, length); 291 292 dma_clear(esp); 293 294 t = (unsigned long *)((addr & 0x00ffffff) + (esp->edev)); 295 296 dregs->clear_strobe = 0; 297 *t = addr; 298 299 ctrl_data = ((ctrl_data & FASTLANE_DMA_MASK) | 300 FASTLANE_DMA_ENABLE | 301 FASTLANE_DMA_WRITE); 302 dregs->ctrl_reg = ctrl_data; 303} 304 305 306static void dma_ints_off(struct NCR_ESP *esp) 307{ 308 disable_irq(esp->irq); 309} 310 311static void dma_ints_on(struct NCR_ESP *esp) 312{ 313 enable_irq(esp->irq); 314} 315 316static void dma_irq_exit(struct NCR_ESP *esp) 317{ 318 struct fastlane_dma_registers *dregs = 319 (struct fastlane_dma_registers *) (esp->dregs); 320 321 dregs->ctrl_reg = ctrl_data & ~(FASTLANE_DMA_EDI|FASTLANE_DMA_ESI); 322#ifdef __mc68000__ 323 nop(); 324#endif 325 dregs->ctrl_reg = ctrl_data; 326} 327 328static int dma_irq_p(struct NCR_ESP *esp) 329{ 330 struct fastlane_dma_registers *dregs = 331 (struct fastlane_dma_registers *) (esp->dregs); 332 unsigned char dma_status; 333 334 dma_status = dregs->cond_reg; 335 336 if(dma_status & FASTLANE_DMA_IACT) 337 return 0; /* not our IRQ */ 338 339 /* Return non-zero if ESP requested IRQ */ 340 return ( 341#ifndef NODMAIRQ 342 (dma_status & FASTLANE_DMA_CREQ) && 343#endif 344 (!(dma_status & FASTLANE_DMA_MINT)) && 345 (esp_read(((struct ESP_regs *) (esp->eregs))->esp_status) & ESP_STAT_INTR)); 346} 347 348static void dma_led_off(struct NCR_ESP *esp) 349{ 350 ctrl_data &= ~FASTLANE_DMA_LED; 351 ((struct fastlane_dma_registers *)(esp->dregs))->ctrl_reg = ctrl_data; 352} 353 354static void dma_led_on(struct NCR_ESP *esp) 355{ 356 ctrl_data |= FASTLANE_DMA_LED; 357 ((struct fastlane_dma_registers *)(esp->dregs))->ctrl_reg = ctrl_data; 358} 359 360static int dma_ports_p(struct NCR_ESP *esp) 361{ 362 return ((amiga_custom.intenar) & IF_PORTS); 363} 364 365static void dma_setup(struct NCR_ESP *esp, __u32 addr, int count, int write) 366{ 367 /* On the Sparc, DMA_ST_WRITE means "move data from device to memory" 368 * so when (write) is true, it actually means READ! 369 */ 370 if(write){ 371 dma_init_read(esp, addr, count); 372 } else { 373 dma_init_write(esp, addr, count); 374 } 375} 376 377#define HOSTS_C 378 379int fastlane_esp_release(struct Scsi_Host *instance) 380{ 381#ifdef MODULE 382 unsigned long address = (unsigned long)((struct NCR_ESP *)instance->hostdata)->edev; 383 esp_deallocate((struct NCR_ESP *)instance->hostdata); 384 esp_release(); 385 release_mem_region(address, sizeof(struct ESP_regs)); 386 free_irq(IRQ_AMIGA_PORTS, esp_intr); 387#endif 388 return 1; 389} 390 391 392static struct scsi_host_template driver_template = { 393 .proc_name = "esp-fastlane", 394 .proc_info = esp_proc_info, 395 .name = "Fastlane SCSI", 396 .detect = fastlane_esp_detect, 397 .slave_alloc = esp_slave_alloc, 398 .slave_destroy = esp_slave_destroy, 399 .release = fastlane_esp_release, 400 .queuecommand = esp_queue, 401 .eh_abort_handler = esp_abort, 402 .eh_bus_reset_handler = esp_reset, 403 .can_queue = 7, 404 .this_id = 7, 405 .sg_tablesize = SG_ALL, 406 .cmd_per_lun = 1, 407 .use_clustering = ENABLE_CLUSTERING 408}; 409 410#include "scsi_module.c" 411 412MODULE_LICENSE("GPL"); 413