1/* 2 * Core definitions and data structures shareable across OS platforms. 3 * 4 * Copyright (c) 1994-2002 Justin T. Gibbs. 5 * Copyright (c) 2000-2002 Adaptec Inc. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions, and the following disclaimer, 13 * without modification. 14 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 15 * substantially similar to the "NO WARRANTY" disclaimer below 16 * ("Disclaimer") and any redistribution must be conditioned upon 17 * including a substantially similar Disclaimer requirement for further 18 * binary redistribution. 19 * 3. Neither the names of the above-listed copyright holders nor the names 20 * of any contributors may be used to endorse or promote products derived 21 * from this software without specific prior written permission. 22 * 23 * Alternatively, this software may be distributed under the terms of the 24 * GNU General Public License ("GPL") version 2 as published by the Free 25 * Software Foundation. 26 * 27 * NO WARRANTY 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 37 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 38 * POSSIBILITY OF SUCH DAMAGES. 39 * 40 * $Id: aic79xx.h,v 1.1.1.1 2007/08/03 18:52:57 Exp $ 41 * 42 * $FreeBSD$ 43 */ 44 45#ifndef _AIC79XX_H_ 46#define _AIC79XX_H_ 47 48/* Register Definitions */ 49#include "aic79xx_reg.h" 50 51/************************* Forward Declarations *******************************/ 52struct ahd_platform_data; 53struct scb_platform_data; 54 55/****************************** Useful Macros *********************************/ 56#ifndef TRUE 57#define TRUE 1 58#endif 59#ifndef FALSE 60#define FALSE 0 61#endif 62 63#define ALL_CHANNELS '\0' 64#define ALL_TARGETS_MASK 0xFFFF 65#define INITIATOR_WILDCARD (~0) 66#define SCB_LIST_NULL 0xFF00 67#define SCB_LIST_NULL_LE (ahd_htole16(SCB_LIST_NULL)) 68#define QOUTFIFO_ENTRY_VALID 0x80 69#define SCBID_IS_NULL(scbid) (((scbid) & 0xFF00 ) == SCB_LIST_NULL) 70 71#define SCSIID_TARGET(ahd, scsiid) \ 72 (((scsiid) & TID) >> TID_SHIFT) 73#define SCSIID_OUR_ID(scsiid) \ 74 ((scsiid) & OID) 75#define SCSIID_CHANNEL(ahd, scsiid) ('A') 76#define SCB_IS_SCSIBUS_B(ahd, scb) (0) 77#define SCB_GET_OUR_ID(scb) \ 78 SCSIID_OUR_ID((scb)->hscb->scsiid) 79#define SCB_GET_TARGET(ahd, scb) \ 80 SCSIID_TARGET((ahd), (scb)->hscb->scsiid) 81#define SCB_GET_CHANNEL(ahd, scb) \ 82 SCSIID_CHANNEL(ahd, (scb)->hscb->scsiid) 83#define SCB_GET_LUN(scb) \ 84 ((scb)->hscb->lun) 85#define SCB_GET_TARGET_OFFSET(ahd, scb) \ 86 SCB_GET_TARGET(ahd, scb) 87#define SCB_GET_TARGET_MASK(ahd, scb) \ 88 (0x01 << (SCB_GET_TARGET_OFFSET(ahd, scb))) 89#ifdef AHD_DEBUG 90#define SCB_IS_SILENT(scb) \ 91 ((ahd_debug & AHD_SHOW_MASKED_ERRORS) == 0 \ 92 && (((scb)->flags & SCB_SILENT) != 0)) 93#else 94#define SCB_IS_SILENT(scb) \ 95 (((scb)->flags & SCB_SILENT) != 0) 96#endif 97/* 98 * TCLs have the following format: TTTTLLLLLLLL 99 */ 100#define TCL_TARGET_OFFSET(tcl) \ 101 ((((tcl) >> 4) & TID) >> 4) 102#define TCL_LUN(tcl) \ 103 (tcl & (AHD_NUM_LUNS - 1)) 104#define BUILD_TCL(scsiid, lun) \ 105 ((lun) | (((scsiid) & TID) << 4)) 106#define BUILD_TCL_RAW(target, channel, lun) \ 107 ((lun) | ((target) << 8)) 108 109#define SCB_GET_TAG(scb) \ 110 ahd_le16toh(scb->hscb->tag) 111 112#ifndef AHD_TARGET_MODE 113#undef AHD_TMODE_ENABLE 114#define AHD_TMODE_ENABLE 0 115#endif 116 117#define AHD_BUILD_COL_IDX(target, lun) \ 118 (((lun) << 4) | target) 119 120#define AHD_GET_SCB_COL_IDX(ahd, scb) \ 121 ((SCB_GET_LUN(scb) << 4) | SCB_GET_TARGET(ahd, scb)) 122 123#define AHD_SET_SCB_COL_IDX(scb, col_idx) \ 124do { \ 125 (scb)->hscb->scsiid = ((col_idx) << TID_SHIFT) & TID; \ 126 (scb)->hscb->lun = ((col_idx) >> 4) & (AHD_NUM_LUNS_NONPKT-1); \ 127} while (0) 128 129#define AHD_COPY_SCB_COL_IDX(dst, src) \ 130do { \ 131 dst->hscb->scsiid = src->hscb->scsiid; \ 132 dst->hscb->lun = src->hscb->lun; \ 133} while (0) 134 135#define AHD_NEVER_COL_IDX 0xFFFF 136 137/**************************** Driver Constants ********************************/ 138/* 139 * The maximum number of supported targets. 140 */ 141#define AHD_NUM_TARGETS 16 142 143/* 144 * The maximum number of supported luns. 145 * The identify message only supports 64 luns in non-packetized transfers. 146 * You can have 2^64 luns when information unit transfers are enabled, 147 * but until we see a need to support that many, we support 256. 148 */ 149#define AHD_NUM_LUNS_NONPKT 64 150#define AHD_NUM_LUNS 256 151 152/* 153 * The maximum transfer per S/G segment. 154 */ 155#define AHD_MAXTRANSFER_SIZE 0x00ffffff /* limited by 24bit counter */ 156 157/* 158 * The maximum amount of SCB storage in hardware on a controller. 159 * This value represents an upper bound. Due to software design, 160 * we may not be able to use this number. 161 */ 162#define AHD_SCB_MAX 512 163 164/* 165 * The maximum number of concurrent transactions supported per driver instance. 166 * Sequencer Control Blocks (SCBs) store per-transaction information. 167 */ 168#define AHD_MAX_QUEUE AHD_SCB_MAX 169 170/* 171 * Define the size of our QIN and QOUT FIFOs. They must be a power of 2 172 * in size and accommodate as many transactions as can be queued concurrently. 173 */ 174#define AHD_QIN_SIZE AHD_MAX_QUEUE 175#define AHD_QOUT_SIZE AHD_MAX_QUEUE 176 177#define AHD_QIN_WRAP(x) ((x) & (AHD_QIN_SIZE-1)) 178/* 179 * The maximum amount of SCB storage we allocate in host memory. 180 */ 181#define AHD_SCB_MAX_ALLOC AHD_MAX_QUEUE 182 183/* 184 * Ring Buffer of incoming target commands. 185 * We allocate 256 to simplify the logic in the sequencer 186 * by using the natural wrap point of an 8bit counter. 187 */ 188#define AHD_TMODE_CMDS 256 189 190/* Reset line assertion time in us */ 191#define AHD_BUSRESET_DELAY 25 192 193/******************* Chip Characteristics/Operating Settings *****************/ 194/* 195 * Chip Type 196 * The chip order is from least sophisticated to most sophisticated. 197 */ 198typedef enum { 199 AHD_NONE = 0x0000, 200 AHD_CHIPID_MASK = 0x00FF, 201 AHD_AIC7901 = 0x0001, 202 AHD_AIC7902 = 0x0002, 203 AHD_AIC7901A = 0x0003, 204 AHD_PCI = 0x0100, /* Bus type PCI */ 205 AHD_PCIX = 0x0200, /* Bus type PCIX */ 206 AHD_BUS_MASK = 0x0F00 207} ahd_chip; 208 209/* 210 * Features available in each chip type. 211 */ 212typedef enum { 213 AHD_FENONE = 0x00000, 214 AHD_WIDE = 0x00001,/* Wide Channel */ 215 AHD_AIC79XXB_SLOWCRC = 0x00002,/* SLOWCRC bit should be set */ 216 AHD_MULTI_FUNC = 0x00100,/* Multi-Function/Channel Device */ 217 AHD_TARGETMODE = 0x01000,/* Has tested target mode support */ 218 AHD_MULTIROLE = 0x02000,/* Space for two roles at a time */ 219 AHD_RTI = 0x04000,/* Retained Training Support */ 220 AHD_NEW_IOCELL_OPTS = 0x08000,/* More Signal knobs in the IOCELL */ 221 AHD_NEW_DFCNTRL_OPTS = 0x10000,/* SCSIENWRDIS bit */ 222 AHD_FAST_CDB_DELIVERY = 0x20000,/* CDB acks released to Output Sync */ 223 AHD_REMOVABLE = 0x00000,/* Hot-Swap supported - None so far*/ 224 AHD_AIC7901_FE = AHD_FENONE, 225 AHD_AIC7901A_FE = AHD_FENONE, 226 AHD_AIC7902_FE = AHD_MULTI_FUNC 227} ahd_feature; 228 229typedef enum { 230 AHD_BUGNONE = 0x0000, 231 /* 232 * Rev A hardware fails to update LAST/CURR/NEXTSCB 233 * correctly in certain packetized selection cases. 234 */ 235 AHD_SENT_SCB_UPDATE_BUG = 0x0001, 236 /* The wrong SCB is accessed to check the abort pending bit. */ 237 AHD_ABORT_LQI_BUG = 0x0002, 238 /* Packetized bitbucket crosses packet boundaries. */ 239 AHD_PKT_BITBUCKET_BUG = 0x0004, 240 /* The selection timer runs twice as long as its setting. */ 241 AHD_LONG_SETIMO_BUG = 0x0008, 242 /* The Non-LQ CRC error status is delayed until phase change. */ 243 AHD_NLQICRC_DELAYED_BUG = 0x0010, 244 /* The chip must be reset for all outgoing bus resets. */ 245 AHD_SCSIRST_BUG = 0x0020, 246 /* Some PCIX fields must be saved and restored across chip reset. */ 247 AHD_PCIX_CHIPRST_BUG = 0x0040, 248 /* MMAPIO is not functional in PCI-X mode. */ 249 AHD_PCIX_MMAPIO_BUG = 0x0080, 250 /* Reads to SCBRAM fail to reset the discard timer. */ 251 AHD_PCIX_SCBRAM_RD_BUG = 0x0100, 252 /* Bug workarounds that can be disabled on non-PCIX busses. */ 253 AHD_PCIX_BUG_MASK = AHD_PCIX_CHIPRST_BUG 254 | AHD_PCIX_MMAPIO_BUG 255 | AHD_PCIX_SCBRAM_RD_BUG, 256 /* 257 * LQOSTOP0 status set even for forced selections with ATN 258 * to perform non-packetized message delivery. 259 */ 260 AHD_LQO_ATNO_BUG = 0x0200, 261 /* FIFO auto-flush does not always trigger. */ 262 AHD_AUTOFLUSH_BUG = 0x0400, 263 /* The CLRLQO registers are not self-clearing. */ 264 AHD_CLRLQO_AUTOCLR_BUG = 0x0800, 265 /* The PACKETIZED status bit refers to the previous connection. */ 266 AHD_PKTIZED_STATUS_BUG = 0x1000, 267 /* "Short Luns" are not placed into outgoing LQ packets correctly. */ 268 AHD_PKT_LUN_BUG = 0x2000, 269 /* 270 * Only the FIFO allocated to the non-packetized connection may 271 * be in use during a non-packetzied connection. 272 */ 273 AHD_NONPACKFIFO_BUG = 0x4000, 274 /* 275 * Writing to a DFF SCBPTR register may fail if concurent with 276 * a hardware write to the other DFF SCBPTR register. This is 277 * not currently a concern in our sequencer since all chips with 278 * this bug have the AHD_NONPACKFIFO_BUG and all writes of concern 279 * occur in non-packetized connections. 280 */ 281 AHD_MDFF_WSCBPTR_BUG = 0x8000, 282 /* SGHADDR updates are slow. */ 283 AHD_REG_SLOW_SETTLE_BUG = 0x10000, 284 /* 285 * Changing the MODE_PTR coincident with an interrupt that 286 * switches to a different mode will cause the interrupt to 287 * be in the mode written outside of interrupt context. 288 */ 289 AHD_SET_MODE_BUG = 0x20000, 290 /* Non-packetized busfree revision does not work. */ 291 AHD_BUSFREEREV_BUG = 0x40000, 292 /* 293 * Paced transfers are indicated with a non-standard PPR 294 * option bit in the neg table, 160MHz is indicated by 295 * sync factor 0x7, and the offset if off by a factor of 2. 296 */ 297 AHD_PACED_NEGTABLE_BUG = 0x80000, 298 /* LQOOVERRUN false positives. */ 299 AHD_LQOOVERRUN_BUG = 0x100000, 300 /* 301 * Controller write to INTSTAT will lose to a host 302 * write to CLRINT. 303 */ 304 AHD_INTCOLLISION_BUG = 0x200000, 305 /* 306 * The GEM318 violates the SCSI spec by not waiting 307 * the mandated bus settle delay between phase changes 308 * in some situations. Some aic79xx chip revs. are more 309 * strict in this regard and will treat REQ assertions 310 * that fall within the bus settle delay window as 311 * glitches. This flag tells the firmware to tolerate 312 * early REQ assertions. 313 */ 314 AHD_EARLY_REQ_BUG = 0x400000, 315 /* 316 * The LED does not stay on long enough in packetized modes. 317 */ 318 AHD_FAINT_LED_BUG = 0x800000 319} ahd_bug; 320 321/* 322 * Configuration specific settings. 323 * The driver determines these settings by probing the 324 * chip/controller's configuration. 325 */ 326typedef enum { 327 AHD_FNONE = 0x00000, 328 AHD_BOOT_CHANNEL = 0x00001,/* We were set as the boot channel. */ 329 AHD_USEDEFAULTS = 0x00004,/* 330 * For cards without an seeprom 331 * or a BIOS to initialize the chip's 332 * SRAM, we use the default target 333 * settings. 334 */ 335 AHD_SEQUENCER_DEBUG = 0x00008, 336 AHD_RESET_BUS_A = 0x00010, 337 AHD_EXTENDED_TRANS_A = 0x00020, 338 AHD_TERM_ENB_A = 0x00040, 339 AHD_SPCHK_ENB_A = 0x00080, 340 AHD_STPWLEVEL_A = 0x00100, 341 AHD_INITIATORROLE = 0x00200,/* 342 * Allow initiator operations on 343 * this controller. 344 */ 345 AHD_TARGETROLE = 0x00400,/* 346 * Allow target operations on this 347 * controller. 348 */ 349 AHD_RESOURCE_SHORTAGE = 0x00800, 350 AHD_TQINFIFO_BLOCKED = 0x01000,/* Blocked waiting for ATIOs */ 351 AHD_INT50_SPEEDFLEX = 0x02000,/* 352 * Internal 50pin connector 353 * sits behind an aic3860 354 */ 355 AHD_BIOS_ENABLED = 0x04000, 356 AHD_ALL_INTERRUPTS = 0x08000, 357 AHD_39BIT_ADDRESSING = 0x10000,/* Use 39 bit addressing scheme. */ 358 AHD_64BIT_ADDRESSING = 0x20000,/* Use 64 bit addressing scheme. */ 359 AHD_CURRENT_SENSING = 0x40000, 360 AHD_SCB_CONFIG_USED = 0x80000,/* No SEEPROM but SCB had info. */ 361 AHD_HP_BOARD = 0x100000, 362 AHD_BUS_RESET_ACTIVE = 0x200000, 363 AHD_UPDATE_PEND_CMDS = 0x400000, 364 AHD_RUNNING_QOUTFIFO = 0x800000, 365 AHD_HAD_FIRST_SEL = 0x1000000 366} ahd_flag; 367 368/************************* Hardware SCB Definition ***************************/ 369 370/* 371 * The driver keeps up to MAX_SCB scb structures per card in memory. The SCB 372 * consists of a "hardware SCB" mirroring the fields available on the card 373 * and additional information the kernel stores for each transaction. 374 * 375 * To minimize space utilization, a portion of the hardware scb stores 376 * different data during different portions of a SCSI transaction. 377 * As initialized by the host driver for the initiator role, this area 378 * contains the SCSI cdb (or a pointer to the cdb) to be executed. After 379 * the cdb has been presented to the target, this area serves to store 380 * residual transfer information and the SCSI status byte. 381 * For the target role, the contents of this area do not change, but 382 * still serve a different purpose than for the initiator role. See 383 * struct target_data for details. 384 */ 385 386/* 387 * Status information embedded in the shared poriton of 388 * an SCB after passing the cdb to the target. The kernel 389 * driver will only read this data for transactions that 390 * complete abnormally. 391 */ 392struct initiator_status { 393 uint32_t residual_datacnt; /* Residual in the current S/G seg */ 394 uint32_t residual_sgptr; /* The next S/G for this transfer */ 395 uint8_t scsi_status; /* Standard SCSI status byte */ 396}; 397 398struct target_status { 399 uint32_t residual_datacnt; /* Residual in the current S/G seg */ 400 uint32_t residual_sgptr; /* The next S/G for this transfer */ 401 uint8_t scsi_status; /* SCSI status to give to initiator */ 402 uint8_t target_phases; /* Bitmap of phases to execute */ 403 uint8_t data_phase; /* Data-In or Data-Out */ 404 uint8_t initiator_tag; /* Initiator's transaction tag */ 405}; 406 407/* 408 * Initiator mode SCB shared data area. 409 * If the embedded CDB is 12 bytes or less, we embed 410 * the sense buffer address in the SCB. This allows 411 * us to retrieve sense information without interrupting 412 * the host in packetized mode. 413 */ 414typedef uint32_t sense_addr_t; 415#define MAX_CDB_LEN 16 416#define MAX_CDB_LEN_WITH_SENSE_ADDR (MAX_CDB_LEN - sizeof(sense_addr_t)) 417union initiator_data { 418 struct { 419 uint64_t cdbptr; 420 uint8_t cdblen; 421 } cdb_from_host; 422 uint8_t cdb[MAX_CDB_LEN]; 423 struct { 424 uint8_t cdb[MAX_CDB_LEN_WITH_SENSE_ADDR]; 425 sense_addr_t sense_addr; 426 } cdb_plus_saddr; 427}; 428 429/* 430 * Target mode version of the shared data SCB segment. 431 */ 432struct target_data { 433 uint32_t spare[2]; 434 uint8_t scsi_status; /* SCSI status to give to initiator */ 435 uint8_t target_phases; /* Bitmap of phases to execute */ 436 uint8_t data_phase; /* Data-In or Data-Out */ 437 uint8_t initiator_tag; /* Initiator's transaction tag */ 438}; 439 440struct hardware_scb { 441/*0*/ union { 442 union initiator_data idata; 443 struct target_data tdata; 444 struct initiator_status istatus; 445 struct target_status tstatus; 446 } shared_data; 447/* 448 * A word about residuals. 449 * The scb is presented to the sequencer with the dataptr and datacnt 450 * fields initialized to the contents of the first S/G element to 451 * transfer. The sgptr field is initialized to the bus address for 452 * the S/G element that follows the first in the in core S/G array 453 * or'ed with the SG_FULL_RESID flag. Sgptr may point to an invalid 454 * S/G entry for this transfer (single S/G element transfer with the 455 * first elements address and length preloaded in the dataptr/datacnt 456 * fields). If no transfer is to occur, sgptr is set to SG_LIST_NULL. 457 * The SG_FULL_RESID flag ensures that the residual will be correctly 458 * noted even if no data transfers occur. Once the data phase is entered, 459 * the residual sgptr and datacnt are loaded from the sgptr and the 460 * datacnt fields. After each S/G element's dataptr and length are 461 * loaded into the hardware, the residual sgptr is advanced. After 462 * each S/G element is expired, its datacnt field is checked to see 463 * if the LAST_SEG flag is set. If so, SG_LIST_NULL is set in the 464 * residual sg ptr and the transfer is considered complete. If the 465 * sequencer determines that there is a residual in the tranfer, or 466 * there is non-zero status, it will set the SG_STATUS_VALID flag in 467 * sgptr and dma the scb back into host memory. To sumarize: 468 * 469 * Sequencer: 470 * o A residual has occurred if SG_FULL_RESID is set in sgptr, 471 * or residual_sgptr does not have SG_LIST_NULL set. 472 * 473 * o We are transfering the last segment if residual_datacnt has 474 * the SG_LAST_SEG flag set. 475 * 476 * Host: 477 * o A residual can only have occurred if a completed scb has the 478 * SG_STATUS_VALID flag set. Inspection of the SCSI status field, 479 * the residual_datacnt, and the residual_sgptr field will tell 480 * for sure. 481 * 482 * o residual_sgptr and sgptr refer to the "next" sg entry 483 * and so may point beyond the last valid sg entry for the 484 * transfer. 485 */ 486#define SG_PTR_MASK 0xFFFFFFF8 487/*16*/ uint16_t tag; /* Reused by Sequencer. */ 488/*18*/ uint8_t control; /* See SCB_CONTROL in aic79xx.reg for details */ 489/*19*/ uint8_t scsiid; /* 490 * Selection out Id 491 * Our Id (bits 0-3) Their ID (bits 4-7) 492 */ 493/*20*/ uint8_t lun; 494/*21*/ uint8_t task_attribute; 495/*22*/ uint8_t cdb_len; 496/*23*/ uint8_t task_management; 497/*24*/ uint64_t dataptr; 498/*32*/ uint32_t datacnt; /* Byte 3 is spare. */ 499/*36*/ uint32_t sgptr; 500/*40*/ uint32_t hscb_busaddr; 501/*44*/ uint32_t next_hscb_busaddr; 502/********** Long lun field only downloaded for full 8 byte lun support ********/ 503/*48*/ uint8_t pkt_long_lun[8]; 504/******* Fields below are not Downloaded (Sequencer may use for scratch) ******/ 505/*56*/ uint8_t spare[8]; 506}; 507 508/************************ Kernel SCB Definitions ******************************/ 509/* 510 * Some fields of the SCB are OS dependent. Here we collect the 511 * definitions for elements that all OS platforms need to include 512 * in there SCB definition. 513 */ 514 515/* 516 * Definition of a scatter/gather element as transfered to the controller. 517 * The aic7xxx chips only support a 24bit length. We use the top byte of 518 * the length to store additional address bits and a flag to indicate 519 * that a given segment terminates the transfer. This gives us an 520 * addressable range of 512GB on machines with 64bit PCI or with chips 521 * that can support dual address cycles on 32bit PCI busses. 522 */ 523struct ahd_dma_seg { 524 uint32_t addr; 525 uint32_t len; 526#define AHD_DMA_LAST_SEG 0x80000000 527#define AHD_SG_HIGH_ADDR_MASK 0x7F000000 528#define AHD_SG_LEN_MASK 0x00FFFFFF 529}; 530 531struct ahd_dma64_seg { 532 uint64_t addr; 533 uint32_t len; 534 uint32_t pad; 535}; 536 537struct map_node { 538 bus_dmamap_t dmamap; 539 dma_addr_t physaddr; 540 uint8_t *vaddr; 541 SLIST_ENTRY(map_node) links; 542}; 543 544/* 545 * The current state of this SCB. 546 */ 547typedef enum { 548 SCB_FLAG_NONE = 0x00000, 549 SCB_TRANSMISSION_ERROR = 0x00001,/* 550 * We detected a parity or CRC 551 * error that has effected the 552 * payload of the command. This 553 * flag is checked when normal 554 * status is returned to catch 555 * the case of a target not 556 * responding to our attempt 557 * to report the error. 558 */ 559 SCB_OTHERTCL_TIMEOUT = 0x00002,/* 560 * Another device was active 561 * during the first timeout for 562 * this SCB so we gave ourselves 563 * an additional timeout period 564 * in case it was hogging the 565 * bus. 566 */ 567 SCB_DEVICE_RESET = 0x00004, 568 SCB_SENSE = 0x00008, 569 SCB_CDB32_PTR = 0x00010, 570 SCB_RECOVERY_SCB = 0x00020, 571 SCB_AUTO_NEGOTIATE = 0x00040,/* Negotiate to achieve goal. */ 572 SCB_NEGOTIATE = 0x00080,/* Negotiation forced for command. */ 573 SCB_ABORT = 0x00100, 574 SCB_ACTIVE = 0x00200, 575 SCB_TARGET_IMMEDIATE = 0x00400, 576 SCB_PACKETIZED = 0x00800, 577 SCB_EXPECT_PPR_BUSFREE = 0x01000, 578 SCB_PKT_SENSE = 0x02000, 579 SCB_EXTERNAL_RESET = 0x04000,/* Device was reset externally */ 580 SCB_ON_COL_LIST = 0x08000, 581 SCB_SILENT = 0x10000 /* 582 * Be quiet about transmission type 583 * errors. They are expected and we 584 * don't want to upset the user. This 585 * flag is typically used during DV. 586 */ 587} scb_flag; 588 589struct scb { 590 struct hardware_scb *hscb; 591 union { 592 SLIST_ENTRY(scb) sle; 593 LIST_ENTRY(scb) le; 594 TAILQ_ENTRY(scb) tqe; 595 } links; 596 union { 597 SLIST_ENTRY(scb) sle; 598 LIST_ENTRY(scb) le; 599 TAILQ_ENTRY(scb) tqe; 600 } links2; 601#define pending_links links2.le 602#define collision_links links2.le 603 struct scb *col_scb; 604 ahd_io_ctx_t io_ctx; 605 struct ahd_softc *ahd_softc; 606 scb_flag flags; 607#ifndef __linux__ 608 bus_dmamap_t dmamap; 609#endif 610 struct scb_platform_data *platform_data; 611 struct map_node *hscb_map; 612 struct map_node *sg_map; 613 struct map_node *sense_map; 614 void *sg_list; 615 uint8_t *sense_data; 616 dma_addr_t sg_list_busaddr; 617 dma_addr_t sense_busaddr; 618 u_int sg_count;/* How full ahd_dma_seg is */ 619#define AHD_MAX_LQ_CRC_ERRORS 5 620 u_int crc_retry_count; 621}; 622 623TAILQ_HEAD(scb_tailq, scb); 624LIST_HEAD(scb_list, scb); 625 626struct scb_data { 627 /* 628 * TAILQ of lists of free SCBs grouped by device 629 * collision domains. 630 */ 631 struct scb_tailq free_scbs; 632 633 /* 634 * Per-device lists of SCBs whose tag ID would collide 635 * with an already active tag on the device. 636 */ 637 struct scb_list free_scb_lists[AHD_NUM_TARGETS * AHD_NUM_LUNS_NONPKT]; 638 639 /* 640 * SCBs that will not collide with any active device. 641 */ 642 struct scb_list any_dev_free_scb_list; 643 644 /* 645 * Mapping from tag to SCB. 646 */ 647 struct scb *scbindex[AHD_SCB_MAX]; 648 649 /* 650 * "Bus" addresses of our data structures. 651 */ 652 bus_dma_tag_t hscb_dmat; /* dmat for our hardware SCB array */ 653 bus_dma_tag_t sg_dmat; /* dmat for our sg segments */ 654 bus_dma_tag_t sense_dmat; /* dmat for our sense buffers */ 655 SLIST_HEAD(, map_node) hscb_maps; 656 SLIST_HEAD(, map_node) sg_maps; 657 SLIST_HEAD(, map_node) sense_maps; 658 int scbs_left; /* unallocated scbs in head map_node */ 659 int sgs_left; /* unallocated sgs in head map_node */ 660 int sense_left; /* unallocated sense in head map_node */ 661 uint16_t numscbs; 662 uint16_t maxhscbs; /* Number of SCBs on the card */ 663 uint8_t init_level; /* 664 * How far we've initialized 665 * this structure. 666 */ 667}; 668 669/************************ Target Mode Definitions *****************************/ 670 671/* 672 * Connection desciptor for select-in requests in target mode. 673 */ 674struct target_cmd { 675 uint8_t scsiid; /* Our ID and the initiator's ID */ 676 uint8_t identify; /* Identify message */ 677 uint8_t bytes[22]; /* 678 * Bytes contains any additional message 679 * bytes terminated by 0xFF. The remainder 680 * is the cdb to execute. 681 */ 682 uint8_t cmd_valid; /* 683 * When a command is complete, the firmware 684 * will set cmd_valid to all bits set. 685 * After the host has seen the command, 686 * the bits are cleared. This allows us 687 * to just peek at host memory to determine 688 * if more work is complete. cmd_valid is on 689 * an 8 byte boundary to simplify setting 690 * it on aic7880 hardware which only has 691 * limited direct access to the DMA FIFO. 692 */ 693 uint8_t pad[7]; 694}; 695 696/* 697 * Number of events we can buffer up if we run out 698 * of immediate notify ccbs. 699 */ 700#define AHD_TMODE_EVENT_BUFFER_SIZE 8 701struct ahd_tmode_event { 702 uint8_t initiator_id; 703 uint8_t event_type; /* MSG type or EVENT_TYPE_BUS_RESET */ 704#define EVENT_TYPE_BUS_RESET 0xFF 705 uint8_t event_arg; 706}; 707 708/* 709 * Per enabled lun target mode state. 710 * As this state is directly influenced by the host OS'es target mode 711 * environment, we let the OS module define it. Forward declare the 712 * structure here so we can store arrays of them, etc. in OS neutral 713 * data structures. 714 */ 715#ifdef AHD_TARGET_MODE 716struct ahd_tmode_lstate { 717 struct cam_path *path; 718 struct ccb_hdr_slist accept_tios; 719 struct ccb_hdr_slist immed_notifies; 720 struct ahd_tmode_event event_buffer[AHD_TMODE_EVENT_BUFFER_SIZE]; 721 uint8_t event_r_idx; 722 uint8_t event_w_idx; 723}; 724#else 725struct ahd_tmode_lstate; 726#endif 727 728/******************** Transfer Negotiation Datastructures *********************/ 729#define AHD_TRANS_CUR 0x01 /* Modify current neogtiation status */ 730#define AHD_TRANS_ACTIVE 0x03 /* Assume this target is on the bus */ 731#define AHD_TRANS_GOAL 0x04 /* Modify negotiation goal */ 732#define AHD_TRANS_USER 0x08 /* Modify user negotiation settings */ 733#define AHD_PERIOD_10MHz 0x19 734 735#define AHD_WIDTH_UNKNOWN 0xFF 736#define AHD_PERIOD_UNKNOWN 0xFF 737#define AHD_OFFSET_UNKNOWN 0xFF 738#define AHD_PPR_OPTS_UNKNOWN 0xFF 739 740/* 741 * Transfer Negotiation Information. 742 */ 743struct ahd_transinfo { 744 uint8_t protocol_version; /* SCSI Revision level */ 745 uint8_t transport_version; /* SPI Revision level */ 746 uint8_t width; /* Bus width */ 747 uint8_t period; /* Sync rate factor */ 748 uint8_t offset; /* Sync offset */ 749 uint8_t ppr_options; /* Parallel Protocol Request options */ 750}; 751 752/* 753 * Per-initiator current, goal and user transfer negotiation information. */ 754struct ahd_initiator_tinfo { 755 struct ahd_transinfo curr; 756 struct ahd_transinfo goal; 757 struct ahd_transinfo user; 758}; 759 760/* 761 * Per enabled target ID state. 762 * Pointers to lun target state as well as sync/wide negotiation information 763 * for each initiator<->target mapping. For the initiator role we pretend 764 * that we are the target and the targets are the initiators since the 765 * negotiation is the same regardless of role. 766 */ 767struct ahd_tmode_tstate { 768 struct ahd_tmode_lstate* enabled_luns[AHD_NUM_LUNS]; 769 struct ahd_initiator_tinfo transinfo[AHD_NUM_TARGETS]; 770 771 /* 772 * Per initiator state bitmasks. 773 */ 774 uint16_t auto_negotiate;/* Auto Negotiation Required */ 775 uint16_t discenable; /* Disconnection allowed */ 776 uint16_t tagenable; /* Tagged Queuing allowed */ 777}; 778 779/* 780 * Points of interest along the negotiated transfer scale. 781 */ 782#define AHD_SYNCRATE_160 0x8 783#define AHD_SYNCRATE_PACED 0x8 784#define AHD_SYNCRATE_DT 0x9 785#define AHD_SYNCRATE_ULTRA2 0xa 786#define AHD_SYNCRATE_ULTRA 0xc 787#define AHD_SYNCRATE_FAST 0x19 788#define AHD_SYNCRATE_MIN_DT AHD_SYNCRATE_FAST 789#define AHD_SYNCRATE_SYNC 0x32 790#define AHD_SYNCRATE_MIN 0x60 791#define AHD_SYNCRATE_ASYNC 0xFF 792#define AHD_SYNCRATE_MAX AHD_SYNCRATE_160 793 794/* Safe and valid period for async negotiations. */ 795#define AHD_ASYNC_XFER_PERIOD 0x44 796 797/* 798 * In RevA, the synctable uses a 120MHz rate for the period 799 * factor 8 and 160MHz for the period factor 7. The 120MHz 800 * rate never made it into the official SCSI spec, so we must 801 * compensate when setting the negotiation table for Rev A 802 * parts. 803 */ 804#define AHD_SYNCRATE_REVA_120 0x8 805#define AHD_SYNCRATE_REVA_160 0x7 806 807/***************************** Lookup Tables **********************************/ 808/* 809 * Phase -> name and message out response 810 * to parity errors in each phase table. 811 */ 812struct ahd_phase_table_entry { 813 uint8_t phase; 814 uint8_t mesg_out; /* Message response to parity errors */ 815 char *phasemsg; 816}; 817 818/************************** Serial EEPROM Format ******************************/ 819 820struct seeprom_config { 821/* 822 * Per SCSI ID Configuration Flags 823 */ 824 uint16_t device_flags[16]; /* words 0-15 */ 825#define CFXFER 0x003F /* synchronous transfer rate */ 826#define CFXFER_ASYNC 0x3F 827#define CFQAS 0x0040 /* Negotiate QAS */ 828#define CFPACKETIZED 0x0080 /* Negotiate Packetized Transfers */ 829#define CFSTART 0x0100 /* send start unit SCSI command */ 830#define CFINCBIOS 0x0200 /* include in BIOS scan */ 831#define CFDISC 0x0400 /* enable disconnection */ 832#define CFMULTILUNDEV 0x0800 /* Probe multiple luns in BIOS scan */ 833#define CFWIDEB 0x1000 /* wide bus device */ 834#define CFHOSTMANAGED 0x8000 /* Managed by a RAID controller */ 835 836/* 837 * BIOS Control Bits 838 */ 839 uint16_t bios_control; /* word 16 */ 840#define CFSUPREM 0x0001 /* support all removeable drives */ 841#define CFSUPREMB 0x0002 /* support removeable boot drives */ 842#define CFBIOSSTATE 0x000C /* BIOS Action State */ 843#define CFBS_DISABLED 0x00 844#define CFBS_ENABLED 0x04 845#define CFBS_DISABLED_SCAN 0x08 846#define CFENABLEDV 0x0010 /* Perform Domain Validation */ 847#define CFCTRL_A 0x0020 /* BIOS displays Ctrl-A message */ 848#define CFSPARITY 0x0040 /* SCSI parity */ 849#define CFEXTEND 0x0080 /* extended translation enabled */ 850#define CFBOOTCD 0x0100 /* Support Bootable CD-ROM */ 851#define CFMSG_LEVEL 0x0600 /* BIOS Message Level */ 852#define CFMSG_VERBOSE 0x0000 853#define CFMSG_SILENT 0x0200 854#define CFMSG_DIAG 0x0400 855#define CFRESETB 0x0800 /* reset SCSI bus at boot */ 856/* UNUSED 0xf000 */ 857 858/* 859 * Host Adapter Control Bits 860 */ 861 uint16_t adapter_control; /* word 17 */ 862#define CFAUTOTERM 0x0001 /* Perform Auto termination */ 863#define CFSTERM 0x0002 /* SCSI low byte termination */ 864#define CFWSTERM 0x0004 /* SCSI high byte termination */ 865#define CFSEAUTOTERM 0x0008 /* Ultra2 Perform secondary Auto Term*/ 866#define CFSELOWTERM 0x0010 /* Ultra2 secondary low term */ 867#define CFSEHIGHTERM 0x0020 /* Ultra2 secondary high term */ 868#define CFSTPWLEVEL 0x0040 /* Termination level control */ 869#define CFBIOSAUTOTERM 0x0080 /* Perform Auto termination */ 870#define CFTERM_MENU 0x0100 /* BIOS displays termination menu */ 871#define CFCLUSTERENB 0x8000 /* Cluster Enable */ 872 873/* 874 * Bus Release Time, Host Adapter ID 875 */ 876 uint16_t brtime_id; /* word 18 */ 877#define CFSCSIID 0x000f /* host adapter SCSI ID */ 878/* UNUSED 0x00f0 */ 879#define CFBRTIME 0xff00 /* bus release time/PCI Latency Time */ 880 881/* 882 * Maximum targets 883 */ 884 uint16_t max_targets; /* word 19 */ 885#define CFMAXTARG 0x00ff /* maximum targets */ 886#define CFBOOTLUN 0x0f00 /* Lun to boot from */ 887#define CFBOOTID 0xf000 /* Target to boot from */ 888 uint16_t res_1[10]; /* words 20-29 */ 889 uint16_t signature; /* BIOS Signature */ 890#define CFSIGNATURE 0x400 891 uint16_t checksum; /* word 31 */ 892}; 893 894/* 895 * Vital Product Data used during POST and by the BIOS. 896 */ 897struct vpd_config { 898 uint8_t bios_flags; 899#define VPDMASTERBIOS 0x0001 900#define VPDBOOTHOST 0x0002 901 uint8_t reserved_1[21]; 902 uint8_t resource_type; 903 uint8_t resource_len[2]; 904 uint8_t resource_data[8]; 905 uint8_t vpd_tag; 906 uint16_t vpd_len; 907 uint8_t vpd_keyword[2]; 908 uint8_t length; 909 uint8_t revision; 910 uint8_t device_flags; 911 uint8_t termnation_menus[2]; 912 uint8_t fifo_threshold; 913 uint8_t end_tag; 914 uint8_t vpd_checksum; 915 uint16_t default_target_flags; 916 uint16_t default_bios_flags; 917 uint16_t default_ctrl_flags; 918 uint8_t default_irq; 919 uint8_t pci_lattime; 920 uint8_t max_target; 921 uint8_t boot_lun; 922 uint16_t signature; 923 uint8_t reserved_2; 924 uint8_t checksum; 925 uint8_t reserved_3[4]; 926}; 927 928/****************************** Flexport Logic ********************************/ 929#define FLXADDR_TERMCTL 0x0 930#define FLX_TERMCTL_ENSECHIGH 0x8 931#define FLX_TERMCTL_ENSECLOW 0x4 932#define FLX_TERMCTL_ENPRIHIGH 0x2 933#define FLX_TERMCTL_ENPRILOW 0x1 934#define FLXADDR_ROMSTAT_CURSENSECTL 0x1 935#define FLX_ROMSTAT_SEECFG 0xF0 936#define FLX_ROMSTAT_EECFG 0x0F 937#define FLX_ROMSTAT_SEE_93C66 0x00 938#define FLX_ROMSTAT_SEE_NONE 0xF0 939#define FLX_ROMSTAT_EE_512x8 0x0 940#define FLX_ROMSTAT_EE_1MBx8 0x1 941#define FLX_ROMSTAT_EE_2MBx8 0x2 942#define FLX_ROMSTAT_EE_4MBx8 0x3 943#define FLX_ROMSTAT_EE_16MBx8 0x4 944#define CURSENSE_ENB 0x1 945#define FLXADDR_FLEXSTAT 0x2 946#define FLX_FSTAT_BUSY 0x1 947#define FLXADDR_CURRENT_STAT 0x4 948#define FLX_CSTAT_SEC_HIGH 0xC0 949#define FLX_CSTAT_SEC_LOW 0x30 950#define FLX_CSTAT_PRI_HIGH 0x0C 951#define FLX_CSTAT_PRI_LOW 0x03 952#define FLX_CSTAT_MASK 0x03 953#define FLX_CSTAT_SHIFT 2 954#define FLX_CSTAT_OKAY 0x0 955#define FLX_CSTAT_OVER 0x1 956#define FLX_CSTAT_UNDER 0x2 957#define FLX_CSTAT_INVALID 0x3 958 959int ahd_read_seeprom(struct ahd_softc *ahd, uint16_t *buf, 960 u_int start_addr, u_int count, int bstream); 961 962int ahd_write_seeprom(struct ahd_softc *ahd, uint16_t *buf, 963 u_int start_addr, u_int count); 964int ahd_verify_cksum(struct seeprom_config *sc); 965int ahd_acquire_seeprom(struct ahd_softc *ahd); 966void ahd_release_seeprom(struct ahd_softc *ahd); 967 968/**************************** Message Buffer *********************************/ 969typedef enum { 970 MSG_FLAG_NONE = 0x00, 971 MSG_FLAG_EXPECT_PPR_BUSFREE = 0x01, 972 MSG_FLAG_IU_REQ_CHANGED = 0x02, 973 MSG_FLAG_EXPECT_IDE_BUSFREE = 0x04, 974 MSG_FLAG_EXPECT_QASREJ_BUSFREE = 0x08, 975 MSG_FLAG_PACKETIZED = 0x10 976} ahd_msg_flags; 977 978typedef enum { 979 MSG_TYPE_NONE = 0x00, 980 MSG_TYPE_INITIATOR_MSGOUT = 0x01, 981 MSG_TYPE_INITIATOR_MSGIN = 0x02, 982 MSG_TYPE_TARGET_MSGOUT = 0x03, 983 MSG_TYPE_TARGET_MSGIN = 0x04 984} ahd_msg_type; 985 986typedef enum { 987 MSGLOOP_IN_PROG, 988 MSGLOOP_MSGCOMPLETE, 989 MSGLOOP_TERMINATED 990} msg_loop_stat; 991 992/*********************** Software Configuration Structure *********************/ 993struct ahd_suspend_channel_state { 994 uint8_t scsiseq; 995 uint8_t sxfrctl0; 996 uint8_t sxfrctl1; 997 uint8_t simode0; 998 uint8_t simode1; 999 uint8_t seltimer; 1000 uint8_t seqctl; 1001}; 1002 1003struct ahd_suspend_state { 1004 struct ahd_suspend_channel_state channel[2]; 1005 uint8_t optionmode; 1006 uint8_t dscommand0; 1007 uint8_t dspcistatus; 1008 /* hsmailbox */ 1009 uint8_t crccontrol1; 1010 uint8_t scbbaddr; 1011 /* Host and sequencer SCB counts */ 1012 uint8_t dff_thrsh; 1013 uint8_t *scratch_ram; 1014 uint8_t *btt; 1015}; 1016 1017typedef void (*ahd_bus_intr_t)(struct ahd_softc *); 1018 1019typedef enum { 1020 AHD_MODE_DFF0, 1021 AHD_MODE_DFF1, 1022 AHD_MODE_CCHAN, 1023 AHD_MODE_SCSI, 1024 AHD_MODE_CFG, 1025 AHD_MODE_UNKNOWN 1026} ahd_mode; 1027 1028#define AHD_MK_MSK(x) (0x01 << (x)) 1029#define AHD_MODE_DFF0_MSK AHD_MK_MSK(AHD_MODE_DFF0) 1030#define AHD_MODE_DFF1_MSK AHD_MK_MSK(AHD_MODE_DFF1) 1031#define AHD_MODE_CCHAN_MSK AHD_MK_MSK(AHD_MODE_CCHAN) 1032#define AHD_MODE_SCSI_MSK AHD_MK_MSK(AHD_MODE_SCSI) 1033#define AHD_MODE_CFG_MSK AHD_MK_MSK(AHD_MODE_CFG) 1034#define AHD_MODE_UNKNOWN_MSK AHD_MK_MSK(AHD_MODE_UNKNOWN) 1035#define AHD_MODE_ANY_MSK (~0) 1036 1037typedef uint8_t ahd_mode_state; 1038 1039typedef void ahd_callback_t (void *); 1040 1041struct ahd_completion 1042{ 1043 uint16_t tag; 1044 uint8_t sg_status; 1045 uint8_t valid_tag; 1046}; 1047 1048struct ahd_softc { 1049 bus_space_tag_t tags[2]; 1050 bus_space_handle_t bshs[2]; 1051#ifndef __linux__ 1052 bus_dma_tag_t buffer_dmat; /* dmat for buffer I/O */ 1053#endif 1054 struct scb_data scb_data; 1055 1056 struct hardware_scb *next_queued_hscb; 1057 struct map_node *next_queued_hscb_map; 1058 1059 /* 1060 * SCBs that have been sent to the controller 1061 */ 1062 LIST_HEAD(, scb) pending_scbs; 1063 1064 /* 1065 * Current register window mode information. 1066 */ 1067 ahd_mode dst_mode; 1068 ahd_mode src_mode; 1069 1070 /* 1071 * Saved register window mode information 1072 * used for restore on next unpause. 1073 */ 1074 ahd_mode saved_dst_mode; 1075 ahd_mode saved_src_mode; 1076 1077 /* 1078 * Platform specific data. 1079 */ 1080 struct ahd_platform_data *platform_data; 1081 1082 /* 1083 * Platform specific device information. 1084 */ 1085 ahd_dev_softc_t dev_softc; 1086 1087 /* 1088 * Bus specific device information. 1089 */ 1090 ahd_bus_intr_t bus_intr; 1091 1092 /* 1093 * Target mode related state kept on a per enabled lun basis. 1094 * Targets that are not enabled will have null entries. 1095 * As an initiator, we keep one target entry for our initiator 1096 * ID to store our sync/wide transfer settings. 1097 */ 1098 struct ahd_tmode_tstate *enabled_targets[AHD_NUM_TARGETS]; 1099 1100 /* 1101 * The black hole device responsible for handling requests for 1102 * disabled luns on enabled targets. 1103 */ 1104 struct ahd_tmode_lstate *black_hole; 1105 1106 /* 1107 * Device instance currently on the bus awaiting a continue TIO 1108 * for a command that was not given the disconnect priveledge. 1109 */ 1110 struct ahd_tmode_lstate *pending_device; 1111 1112 /* 1113 * Timer handles for timer driven callbacks. 1114 */ 1115 ahd_timer_t reset_timer; 1116 ahd_timer_t stat_timer; 1117 1118 /* 1119 * Statistics. 1120 */ 1121#define AHD_STAT_UPDATE_US 250000 /* 250ms */ 1122#define AHD_STAT_BUCKETS 4 1123 u_int cmdcmplt_bucket; 1124 uint32_t cmdcmplt_counts[AHD_STAT_BUCKETS]; 1125 uint32_t cmdcmplt_total; 1126 1127 /* 1128 * Card characteristics 1129 */ 1130 ahd_chip chip; 1131 ahd_feature features; 1132 ahd_bug bugs; 1133 ahd_flag flags; 1134 struct seeprom_config *seep_config; 1135 1136 /* Command Queues */ 1137 struct ahd_completion *qoutfifo; 1138 uint16_t qoutfifonext; 1139 uint16_t qoutfifonext_valid_tag; 1140 uint16_t qinfifonext; 1141 uint16_t qinfifo[AHD_SCB_MAX]; 1142 1143 /* 1144 * Our qfreeze count. The sequencer compares 1145 * this value with its own counter to determine 1146 * whether to allow selections to occur. 1147 */ 1148 uint16_t qfreeze_cnt; 1149 1150 /* Values to store in the SEQCTL register for pause and unpause */ 1151 uint8_t unpause; 1152 uint8_t pause; 1153 1154 /* Critical Section Data */ 1155 struct cs *critical_sections; 1156 u_int num_critical_sections; 1157 1158 /* Buffer for handling packetized bitbucket. */ 1159 uint8_t *overrun_buf; 1160 1161 /* Links for chaining softcs */ 1162 TAILQ_ENTRY(ahd_softc) links; 1163 1164 /* Channel Names ('A', 'B', etc.) */ 1165 char channel; 1166 1167 /* Initiator Bus ID */ 1168 uint8_t our_id; 1169 1170 /* 1171 * Target incoming command FIFO. 1172 */ 1173 struct target_cmd *targetcmds; 1174 uint8_t tqinfifonext; 1175 1176 /* 1177 * Cached verson of the hs_mailbox so we can avoid 1178 * pausing the sequencer during mailbox updates. 1179 */ 1180 uint8_t hs_mailbox; 1181 1182 /* 1183 * Incoming and outgoing message handling. 1184 */ 1185 uint8_t send_msg_perror; 1186 ahd_msg_flags msg_flags; 1187 ahd_msg_type msg_type; 1188 uint8_t msgout_buf[12];/* Message we are sending */ 1189 uint8_t msgin_buf[12];/* Message we are receiving */ 1190 u_int msgout_len; /* Length of message to send */ 1191 u_int msgout_index; /* Current index in msgout */ 1192 u_int msgin_index; /* Current index in msgin */ 1193 1194 /* 1195 * Mapping information for data structures shared 1196 * between the sequencer and kernel. 1197 */ 1198 bus_dma_tag_t parent_dmat; 1199 bus_dma_tag_t shared_data_dmat; 1200 struct map_node shared_data_map; 1201 1202 /* Information saved through suspend/resume cycles */ 1203 struct ahd_suspend_state suspend_state; 1204 1205 /* Number of enabled target mode device on this card */ 1206 u_int enabled_luns; 1207 1208 /* Initialization level of this data structure */ 1209 u_int init_level; 1210 1211 /* PCI cacheline size. */ 1212 u_int pci_cachesize; 1213 1214 /* IO Cell Parameters */ 1215 uint8_t iocell_opts[AHD_NUM_PER_DEV_ANNEXCOLS]; 1216 1217 u_int stack_size; 1218 uint16_t *saved_stack; 1219 1220 /* Per-Unit descriptive information */ 1221 const char *description; 1222 const char *bus_description; 1223 char *name; 1224 int unit; 1225 1226 /* Selection Timer settings */ 1227 int seltime; 1228 1229 /* 1230 * Interrupt coalescing settings. 1231 */ 1232#define AHD_INT_COALESCING_TIMER_DEFAULT 250 /*us*/ 1233#define AHD_INT_COALESCING_MAXCMDS_DEFAULT 10 1234#define AHD_INT_COALESCING_MAXCMDS_MAX 127 1235#define AHD_INT_COALESCING_MINCMDS_DEFAULT 5 1236#define AHD_INT_COALESCING_MINCMDS_MAX 127 1237#define AHD_INT_COALESCING_THRESHOLD_DEFAULT 2000 1238#define AHD_INT_COALESCING_STOP_THRESHOLD_DEFAULT 1000 1239 u_int int_coalescing_timer; 1240 u_int int_coalescing_maxcmds; 1241 u_int int_coalescing_mincmds; 1242 u_int int_coalescing_threshold; 1243 u_int int_coalescing_stop_threshold; 1244 1245 uint16_t user_discenable;/* Disconnection allowed */ 1246 uint16_t user_tagenable;/* Tagged Queuing allowed */ 1247}; 1248 1249/*************************** IO Cell Configuration ****************************/ 1250#define AHD_PRECOMP_SLEW_INDEX \ 1251 (AHD_ANNEXCOL_PRECOMP_SLEW - AHD_ANNEXCOL_PER_DEV0) 1252 1253#define AHD_AMPLITUDE_INDEX \ 1254 (AHD_ANNEXCOL_AMPLITUDE - AHD_ANNEXCOL_PER_DEV0) 1255 1256#define AHD_SET_SLEWRATE(ahd, new_slew) \ 1257do { \ 1258 (ahd)->iocell_opts[AHD_PRECOMP_SLEW_INDEX] &= ~AHD_SLEWRATE_MASK; \ 1259 (ahd)->iocell_opts[AHD_PRECOMP_SLEW_INDEX] |= \ 1260 (((new_slew) << AHD_SLEWRATE_SHIFT) & AHD_SLEWRATE_MASK); \ 1261} while (0) 1262 1263#define AHD_SET_PRECOMP(ahd, new_pcomp) \ 1264do { \ 1265 (ahd)->iocell_opts[AHD_PRECOMP_SLEW_INDEX] &= ~AHD_PRECOMP_MASK; \ 1266 (ahd)->iocell_opts[AHD_PRECOMP_SLEW_INDEX] |= \ 1267 (((new_pcomp) << AHD_PRECOMP_SHIFT) & AHD_PRECOMP_MASK); \ 1268} while (0) 1269 1270#define AHD_SET_AMPLITUDE(ahd, new_amp) \ 1271do { \ 1272 (ahd)->iocell_opts[AHD_AMPLITUDE_INDEX] &= ~AHD_AMPLITUDE_MASK; \ 1273 (ahd)->iocell_opts[AHD_AMPLITUDE_INDEX] |= \ 1274 (((new_amp) << AHD_AMPLITUDE_SHIFT) & AHD_AMPLITUDE_MASK); \ 1275} while (0) 1276 1277/************************ Active Device Information ***************************/ 1278typedef enum { 1279 ROLE_UNKNOWN, 1280 ROLE_INITIATOR, 1281 ROLE_TARGET 1282} role_t; 1283 1284struct ahd_devinfo { 1285 int our_scsiid; 1286 int target_offset; 1287 uint16_t target_mask; 1288 u_int target; 1289 u_int lun; 1290 char channel; 1291 role_t role; /* 1292 * Only guaranteed to be correct if not 1293 * in the busfree state. 1294 */ 1295}; 1296 1297/****************************** PCI Structures ********************************/ 1298#define AHD_PCI_IOADDR0 PCIR_BAR(0) /* I/O BAR*/ 1299#define AHD_PCI_MEMADDR PCIR_BAR(1) /* Memory BAR */ 1300#define AHD_PCI_IOADDR1 PCIR_BAR(3) /* Second I/O BAR */ 1301 1302typedef int (ahd_device_setup_t)(struct ahd_softc *); 1303 1304struct ahd_pci_identity { 1305 uint64_t full_id; 1306 uint64_t id_mask; 1307 char *name; 1308 ahd_device_setup_t *setup; 1309}; 1310 1311/***************************** VL/EISA Declarations ***************************/ 1312struct aic7770_identity { 1313 uint32_t full_id; 1314 uint32_t id_mask; 1315 char *name; 1316 ahd_device_setup_t *setup; 1317}; 1318extern struct aic7770_identity aic7770_ident_table []; 1319extern const int ahd_num_aic7770_devs; 1320 1321#define AHD_EISA_SLOT_OFFSET 0xc00 1322#define AHD_EISA_IOSIZE 0x100 1323 1324/*************************** Function Declarations ****************************/ 1325/******************************************************************************/ 1326void ahd_reset_cmds_pending(struct ahd_softc *ahd); 1327 1328/***************************** PCI Front End *********************************/ 1329struct ahd_pci_identity *ahd_find_pci_device(ahd_dev_softc_t); 1330int ahd_pci_config(struct ahd_softc *, 1331 struct ahd_pci_identity *); 1332int ahd_pci_test_register_access(struct ahd_softc *); 1333 1334/************************** SCB and SCB queue management **********************/ 1335void ahd_qinfifo_requeue_tail(struct ahd_softc *ahd, 1336 struct scb *scb); 1337 1338/****************************** Initialization ********************************/ 1339struct ahd_softc *ahd_alloc(void *platform_arg, char *name); 1340int ahd_softc_init(struct ahd_softc *); 1341void ahd_controller_info(struct ahd_softc *ahd, char *buf); 1342int ahd_init(struct ahd_softc *ahd); 1343int ahd_default_config(struct ahd_softc *ahd); 1344int ahd_parse_vpddata(struct ahd_softc *ahd, 1345 struct vpd_config *vpd); 1346int ahd_parse_cfgdata(struct ahd_softc *ahd, 1347 struct seeprom_config *sc); 1348void ahd_intr_enable(struct ahd_softc *ahd, int enable); 1349void ahd_pause_and_flushwork(struct ahd_softc *ahd); 1350int ahd_suspend(struct ahd_softc *ahd); 1351void ahd_set_unit(struct ahd_softc *, int); 1352void ahd_set_name(struct ahd_softc *, char *); 1353struct scb *ahd_get_scb(struct ahd_softc *ahd, u_int col_idx); 1354void ahd_free_scb(struct ahd_softc *ahd, struct scb *scb); 1355void ahd_free(struct ahd_softc *ahd); 1356int ahd_reset(struct ahd_softc *ahd, int reinit); 1357int ahd_write_flexport(struct ahd_softc *ahd, 1358 u_int addr, u_int value); 1359int ahd_read_flexport(struct ahd_softc *ahd, u_int addr, 1360 uint8_t *value); 1361 1362/*************************** Interrupt Services *******************************/ 1363void ahd_run_qoutfifo(struct ahd_softc *ahd); 1364#ifdef AHD_TARGET_MODE 1365void ahd_run_tqinfifo(struct ahd_softc *ahd, int paused); 1366#endif 1367void ahd_handle_hwerrint(struct ahd_softc *ahd); 1368void ahd_handle_seqint(struct ahd_softc *ahd, u_int intstat); 1369void ahd_handle_scsiint(struct ahd_softc *ahd, 1370 u_int intstat); 1371 1372/***************************** Error Recovery *********************************/ 1373typedef enum { 1374 SEARCH_COMPLETE, 1375 SEARCH_COUNT, 1376 SEARCH_REMOVE, 1377 SEARCH_PRINT 1378} ahd_search_action; 1379int ahd_search_qinfifo(struct ahd_softc *ahd, int target, 1380 char channel, int lun, u_int tag, 1381 role_t role, uint32_t status, 1382 ahd_search_action action); 1383int ahd_search_disc_list(struct ahd_softc *ahd, int target, 1384 char channel, int lun, u_int tag, 1385 int stop_on_first, int remove, 1386 int save_state); 1387int ahd_reset_channel(struct ahd_softc *ahd, char channel, 1388 int initiate_reset); 1389/*************************** Utility Functions ********************************/ 1390void ahd_compile_devinfo(struct ahd_devinfo *devinfo, 1391 u_int our_id, u_int target, 1392 u_int lun, char channel, 1393 role_t role); 1394/************************** Transfer Negotiation ******************************/ 1395void ahd_find_syncrate(struct ahd_softc *ahd, u_int *period, 1396 u_int *ppr_options, u_int maxsync); 1397/* 1398 * Negotiation types. These are used to qualify if we should renegotiate 1399 * even if our goal and current transport parameters are identical. 1400 */ 1401typedef enum { 1402 AHD_NEG_TO_GOAL, /* Renegotiate only if goal and curr differ. */ 1403 AHD_NEG_IF_NON_ASYNC, /* Renegotiate so long as goal is non-async. */ 1404 AHD_NEG_ALWAYS /* Renegotiat even if goal is async. */ 1405} ahd_neg_type; 1406int ahd_update_neg_request(struct ahd_softc*, 1407 struct ahd_devinfo*, 1408 struct ahd_tmode_tstate*, 1409 struct ahd_initiator_tinfo*, 1410 ahd_neg_type); 1411void ahd_set_width(struct ahd_softc *ahd, 1412 struct ahd_devinfo *devinfo, 1413 u_int width, u_int type, int paused); 1414void ahd_set_syncrate(struct ahd_softc *ahd, 1415 struct ahd_devinfo *devinfo, 1416 u_int period, u_int offset, 1417 u_int ppr_options, 1418 u_int type, int paused); 1419typedef enum { 1420 AHD_QUEUE_NONE, 1421 AHD_QUEUE_BASIC, 1422 AHD_QUEUE_TAGGED 1423} ahd_queue_alg; 1424 1425/**************************** Target Mode *************************************/ 1426#ifdef AHD_TARGET_MODE 1427void ahd_send_lstate_events(struct ahd_softc *, 1428 struct ahd_tmode_lstate *); 1429void ahd_handle_en_lun(struct ahd_softc *ahd, 1430 struct cam_sim *sim, union ccb *ccb); 1431cam_status ahd_find_tmode_devs(struct ahd_softc *ahd, 1432 struct cam_sim *sim, union ccb *ccb, 1433 struct ahd_tmode_tstate **tstate, 1434 struct ahd_tmode_lstate **lstate, 1435 int notfound_failure); 1436#ifndef AHD_TMODE_ENABLE 1437#define AHD_TMODE_ENABLE 0 1438#endif 1439#endif 1440/******************************* Debug ***************************************/ 1441#ifdef AHD_DEBUG 1442extern uint32_t ahd_debug; 1443#define AHD_SHOW_MISC 0x00001 1444#define AHD_SHOW_SENSE 0x00002 1445#define AHD_SHOW_RECOVERY 0x00004 1446#define AHD_DUMP_SEEPROM 0x00008 1447#define AHD_SHOW_TERMCTL 0x00010 1448#define AHD_SHOW_MEMORY 0x00020 1449#define AHD_SHOW_MESSAGES 0x00040 1450#define AHD_SHOW_MODEPTR 0x00080 1451#define AHD_SHOW_SELTO 0x00100 1452#define AHD_SHOW_FIFOS 0x00200 1453#define AHD_SHOW_QFULL 0x00400 1454#define AHD_SHOW_DV 0x00800 1455#define AHD_SHOW_MASKED_ERRORS 0x01000 1456#define AHD_SHOW_QUEUE 0x02000 1457#define AHD_SHOW_TQIN 0x04000 1458#define AHD_SHOW_SG 0x08000 1459#define AHD_SHOW_INT_COALESCING 0x10000 1460#define AHD_DEBUG_SEQUENCER 0x20000 1461#endif 1462void ahd_print_devinfo(struct ahd_softc *ahd, 1463 struct ahd_devinfo *devinfo); 1464void ahd_dump_card_state(struct ahd_softc *ahd); 1465int ahd_print_register(ahd_reg_parse_entry_t *table, 1466 u_int num_entries, 1467 const char *name, 1468 u_int address, 1469 u_int value, 1470 u_int *cur_column, 1471 u_int wrap_point); 1472#endif /* _AIC79XX_H_ */ 1473