1/* -*- mode: c; c-basic-offset: 8 -*- */ 2 3/* NCR Quad 720 MCA SCSI Driver 4 * 5 * Copyright (C) 2003 by James.Bottomley@HansenPartnership.com 6 */ 7 8#include <linux/blkdev.h> 9#include <linux/interrupt.h> 10#include <linux/kernel.h> 11#include <linux/module.h> 12#include <linux/mca.h> 13#include <linux/types.h> 14#include <linux/init.h> 15#include <linux/delay.h> 16#include <asm/io.h> 17 18#include "scsi.h" 19#include <scsi/scsi_host.h> 20 21#include "ncr53c8xx.h" 22 23#include "NCR_Q720.h" 24 25static struct ncr_chip q720_chip __initdata = { 26 .revision_id = 0x0f, 27 .burst_max = 3, 28 .offset_max = 8, 29 .nr_divisor = 4, 30 .features = FE_WIDE | FE_DIFF | FE_VARCLK, 31}; 32 33MODULE_AUTHOR("James Bottomley"); 34MODULE_DESCRIPTION("NCR Quad 720 SCSI Driver"); 35MODULE_LICENSE("GPL"); 36 37#define NCR_Q720_VERSION "0.9" 38 39/* We needs this helper because we have up to four hosts per struct device */ 40struct NCR_Q720_private { 41 struct device *dev; 42 void __iomem * mem_base; 43 __u32 phys_mem_base; 44 __u32 mem_size; 45 __u8 irq; 46 __u8 siops; 47 __u8 irq_enable; 48 struct Scsi_Host *hosts[4]; 49}; 50 51static struct scsi_host_template NCR_Q720_tpnt = { 52 .module = THIS_MODULE, 53 .proc_name = "NCR_Q720", 54}; 55 56static irqreturn_t 57NCR_Q720_intr(int irq, void *data) 58{ 59 struct NCR_Q720_private *p = (struct NCR_Q720_private *)data; 60 __u8 sir = (readb(p->mem_base + 0x0d) & 0xf0) >> 4; 61 __u8 siop; 62 63 sir |= ~p->irq_enable; 64 65 if(sir == 0xff) 66 return IRQ_NONE; 67 68 69 while((siop = ffz(sir)) < p->siops) { 70 sir |= 1<<siop; 71 ncr53c8xx_intr(irq, p->hosts[siop]); 72 } 73 return IRQ_HANDLED; 74} 75 76static int __init 77NCR_Q720_probe_one(struct NCR_Q720_private *p, int siop, 78 int irq, int slot, __u32 paddr, void __iomem *vaddr) 79{ 80 struct ncr_device device; 81 __u8 scsi_id; 82 static int unit = 0; 83 __u8 scsr1 = readb(vaddr + NCR_Q720_SCSR_OFFSET + 1); 84 __u8 differential = readb(vaddr + NCR_Q720_SCSR_OFFSET) & 0x20; 85 __u8 version; 86 int error; 87 88 scsi_id = scsr1 >> 4; 89 scsr1 |= 0x02; 90 /* force a siop reset */ 91 scsr1 |= 0x04; 92 writeb(scsr1, vaddr + NCR_Q720_SCSR_OFFSET + 1); 93 udelay(10); 94 version = readb(vaddr + 0x18) >> 4; 95 96 memset(&device, 0, sizeof(struct ncr_device)); 97 /* Initialise ncr_device structure with items required by ncr_attach. */ 98 device.chip = q720_chip; 99 device.chip.revision_id = version; 100 device.host_id = scsi_id; 101 device.dev = p->dev; 102 device.slot.base = paddr; 103 device.slot.base_c = paddr; 104 device.slot.base_v = vaddr; 105 device.slot.irq = irq; 106 device.differential = differential ? 2 : 0; 107 printk("Q720 probe unit %d (siop%d) at 0x%lx, diff = %d, vers = %d\n", unit, siop, 108 (unsigned long)paddr, differential, version); 109 110 p->hosts[siop] = ncr_attach(&NCR_Q720_tpnt, unit++, &device); 111 112 if (!p->hosts[siop]) 113 goto fail; 114 115 p->irq_enable |= (1<<siop); 116 scsr1 = readb(vaddr + NCR_Q720_SCSR_OFFSET + 1); 117 /* clear the disable interrupt bit */ 118 scsr1 &= ~0x01; 119 writeb(scsr1, vaddr + NCR_Q720_SCSR_OFFSET + 1); 120 121 error = scsi_add_host(p->hosts[siop], p->dev); 122 if (error) 123 ncr53c8xx_release(p->hosts[siop]); 124 else 125 scsi_scan_host(p->hosts[siop]); 126 return error; 127 128 fail: 129 return -ENODEV; 130} 131 132/* Detect a Q720 card. Note, because of the setup --- the chips are 133 * essentially connectecd to the MCA bus independently, it is easier 134 * to set them up as two separate host adapters, rather than one 135 * adapter with two channels */ 136static int __init 137NCR_Q720_probe(struct device *dev) 138{ 139 struct NCR_Q720_private *p; 140 static int banner = 1; 141 struct mca_device *mca_dev = to_mca_device(dev); 142 int slot = mca_dev->slot; 143 int found = 0; 144 int irq, i, siops; 145 __u8 pos2, pos4, asr2, asr9, asr10; 146 __u16 io_base; 147 __u32 base_addr, mem_size; 148 void __iomem *mem_base; 149 150 p = kmalloc(sizeof(*p), GFP_KERNEL); 151 if (!p) 152 return -ENOMEM; 153 154 memset(p, 0, sizeof(*p)); 155 pos2 = mca_device_read_pos(mca_dev, 2); 156 /* enable device */ 157 pos2 |= NCR_Q720_POS2_BOARD_ENABLE | NCR_Q720_POS2_INTERRUPT_ENABLE; 158 mca_device_write_pos(mca_dev, 2, pos2); 159 160 io_base = (pos2 & NCR_Q720_POS2_IO_MASK) << NCR_Q720_POS2_IO_SHIFT; 161 162 163 if(banner) { 164 printk(KERN_NOTICE "NCR Q720: Driver Version " NCR_Q720_VERSION "\n" 165 "NCR Q720: Copyright (c) 2003 by James.Bottomley@HansenPartnership.com\n" 166 "NCR Q720:\n"); 167 banner = 0; 168 } 169 io_base = mca_device_transform_ioport(mca_dev, io_base); 170 171 /* OK, this is phase one of the bootstrap, we now know the 172 * I/O space base address. All the configuration registers 173 * are mapped here (including pos) */ 174 175 /* sanity check I/O mapping */ 176 i = inb(io_base) | (inb(io_base+1)<<8); 177 if(i != NCR_Q720_MCA_ID) { 178 printk(KERN_ERR "NCR_Q720, adapter failed to I/O map registers correctly at 0x%x(0x%x)\n", io_base, i); 179 kfree(p); 180 return -ENODEV; 181 } 182 183 /* Phase II, find the ram base and memory map the board register */ 184 pos4 = inb(io_base + 4); 185 /* enable streaming data */ 186 pos4 |= 0x01; 187 outb(pos4, io_base + 4); 188 base_addr = (pos4 & 0x7e) << 20; 189 base_addr += (pos4 & 0x80) << 23; 190 asr10 = inb(io_base + 0x12); 191 base_addr += (asr10 & 0x80) << 24; 192 base_addr += (asr10 & 0x70) << 23; 193 194 /* OK, got the base addr, now we need to find the ram size, 195 * enable and map it */ 196 asr9 = inb(io_base + 0x11); 197 i = (asr9 & 0xc0) >> 6; 198 if(i == 0) 199 mem_size = 1024; 200 else 201 mem_size = 1 << (19 + i); 202 203 /* enable the sram mapping */ 204 asr9 |= 0x20; 205 206 /* disable the rom mapping */ 207 asr9 &= ~0x10; 208 209 outb(asr9, io_base + 0x11); 210 211 if(!request_mem_region(base_addr, mem_size, "NCR_Q720")) { 212 printk(KERN_ERR "NCR_Q720: Failed to claim memory region 0x%lx\n-0x%lx", 213 (unsigned long)base_addr, 214 (unsigned long)(base_addr + mem_size)); 215 goto out_free; 216 } 217 218 if (dma_declare_coherent_memory(dev, base_addr, base_addr, 219 mem_size, DMA_MEMORY_MAP) 220 != DMA_MEMORY_MAP) { 221 printk(KERN_ERR "NCR_Q720: DMA declare memory failed\n"); 222 goto out_release_region; 223 } 224 225 /* The first 1k of the memory buffer is a memory map of the registers 226 */ 227 mem_base = dma_mark_declared_memory_occupied(dev, base_addr, 228 1024); 229 if (IS_ERR(mem_base)) { 230 printk("NCR_Q720 failed to reserve memory mapped region\n"); 231 goto out_release; 232 } 233 234 /* now also enable accesses in asr 2 */ 235 asr2 = inb(io_base + 0x0a); 236 237 asr2 |= 0x01; 238 239 outb(asr2, io_base + 0x0a); 240 241 /* get the number of SIOPs (this should be 2 or 4) */ 242 siops = ((asr2 & 0xe0) >> 5) + 1; 243 244 /* sanity check mapping (again) */ 245 i = readw(mem_base); 246 if(i != NCR_Q720_MCA_ID) { 247 printk(KERN_ERR "NCR_Q720, adapter failed to memory map registers correctly at 0x%lx(0x%x)\n", (unsigned long)base_addr, i); 248 goto out_release; 249 } 250 251 irq = readb(mem_base + 5) & 0x0f; 252 253 254 /* now do the bus related transforms */ 255 irq = mca_device_transform_irq(mca_dev, irq); 256 257 printk(KERN_NOTICE "NCR Q720: found in slot %d irq = %d mem base = 0x%lx siops = %d\n", slot, irq, (unsigned long)base_addr, siops); 258 printk(KERN_NOTICE "NCR Q720: On board ram %dk\n", mem_size/1024); 259 260 p->dev = dev; 261 p->mem_base = mem_base; 262 p->phys_mem_base = base_addr; 263 p->mem_size = mem_size; 264 p->irq = irq; 265 p->siops = siops; 266 267 if (request_irq(irq, NCR_Q720_intr, IRQF_SHARED, "NCR_Q720", p)) { 268 printk(KERN_ERR "NCR_Q720: request irq %d failed\n", irq); 269 goto out_release; 270 } 271 /* disable all the siop interrupts */ 272 for(i = 0; i < siops; i++) { 273 void __iomem *reg_scsr1 = mem_base + NCR_Q720_CHIP_REGISTER_OFFSET 274 + i*NCR_Q720_SIOP_SHIFT + NCR_Q720_SCSR_OFFSET + 1; 275 __u8 scsr1 = readb(reg_scsr1); 276 scsr1 |= 0x01; 277 writeb(scsr1, reg_scsr1); 278 } 279 280 /* plumb in all 720 chips */ 281 for (i = 0; i < siops; i++) { 282 void __iomem *siop_v_base = mem_base + NCR_Q720_CHIP_REGISTER_OFFSET 283 + i*NCR_Q720_SIOP_SHIFT; 284 __u32 siop_p_base = base_addr + NCR_Q720_CHIP_REGISTER_OFFSET 285 + i*NCR_Q720_SIOP_SHIFT; 286 __u16 port = io_base + NCR_Q720_CHIP_REGISTER_OFFSET 287 + i*NCR_Q720_SIOP_SHIFT; 288 int err; 289 290 outb(0xff, port + 0x40); 291 outb(0x07, port + 0x41); 292 if ((err = NCR_Q720_probe_one(p, i, irq, slot, 293 siop_p_base, siop_v_base)) != 0) 294 printk("Q720: SIOP%d: probe failed, error = %d\n", 295 i, err); 296 else 297 found++; 298 } 299 300 if (!found) { 301 kfree(p); 302 return -ENODEV; 303 } 304 305 mca_device_set_claim(mca_dev, 1); 306 mca_device_set_name(mca_dev, "NCR_Q720"); 307 dev_set_drvdata(dev, p); 308 309 return 0; 310 311 out_release: 312 dma_release_declared_memory(dev); 313 out_release_region: 314 release_mem_region(base_addr, mem_size); 315 out_free: 316 kfree(p); 317 318 return -ENODEV; 319} 320 321static void __exit 322NCR_Q720_remove_one(struct Scsi_Host *host) 323{ 324 scsi_remove_host(host); 325 ncr53c8xx_release(host); 326} 327 328static int __exit 329NCR_Q720_remove(struct device *dev) 330{ 331 struct NCR_Q720_private *p = dev_get_drvdata(dev); 332 int i; 333 334 for (i = 0; i < p->siops; i++) 335 if(p->hosts[i]) 336 NCR_Q720_remove_one(p->hosts[i]); 337 338 dma_release_declared_memory(dev); 339 release_mem_region(p->phys_mem_base, p->mem_size); 340 free_irq(p->irq, p); 341 kfree(p); 342 return 0; 343} 344 345static short NCR_Q720_id_table[] = { NCR_Q720_MCA_ID, 0 }; 346 347static struct mca_driver NCR_Q720_driver = { 348 .id_table = NCR_Q720_id_table, 349 .driver = { 350 .name = "NCR_Q720", 351 .bus = &mca_bus_type, 352 .probe = NCR_Q720_probe, 353 .remove = __devexit_p(NCR_Q720_remove), 354 }, 355}; 356 357static int __init 358NCR_Q720_init(void) 359{ 360 int ret = ncr53c8xx_init(); 361 if (!ret) 362 ret = mca_register_driver(&NCR_Q720_driver); 363 if (ret) 364 ncr53c8xx_exit(); 365 return ret; 366} 367 368static void __exit 369NCR_Q720_exit(void) 370{ 371 mca_unregister_driver(&NCR_Q720_driver); 372 ncr53c8xx_exit(); 373} 374 375module_init(NCR_Q720_init); 376module_exit(NCR_Q720_exit); 377