1/* 2 * pc300.h Cyclades-PC300(tm) Kernel API Definitions. 3 * 4 * Author: Ivan Passos <ivan@cyclades.com> 5 * 6 * Copyright: (c) 1999-2002 Cyclades Corp. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License 10 * as published by the Free Software Foundation; either version 11 * 2 of the License, or (at your option) any later version. 12 * 13 * $Log: pc300.h,v $ 14 * Revision 1.1.1.1 2007/08/03 18:52:49 rnuti 15 * Importing Linux MIPS Kernel 2.6.22 16 * 17 * Revision 3.12 2002/03/07 14:17:09 henrique 18 * License data fixed 19 * 20 * Revision 3.11 2002/01/28 21:09:39 daniela 21 * Included ';' after pc300hw.bus. 22 * 23 * Revision 3.10 2002/01/17 17:58:52 ivan 24 * Support for PC300-TE/M (PMC). 25 * 26 * Revision 3.9 2001/09/28 13:30:53 daniela 27 * Renamed dma_start routine to rx_dma_start. 28 * 29 * Revision 3.8 2001/09/24 13:03:45 daniela 30 * Fixed BOF interrupt treatment. Created dma_start routine. 31 * 32 * Revision 3.7 2001/08/10 17:19:58 daniela 33 * Fixed IOCTLs defines. 34 * 35 * Revision 3.6 2001/07/18 19:24:42 daniela 36 * Included kernel version. 37 * 38 * Revision 3.5 2001/07/05 18:38:08 daniela 39 * DMA transmission bug fix. 40 * 41 * Revision 3.4 2001/06/26 17:10:40 daniela 42 * New configuration parameters (line code, CRC calculation and clock). 43 * 44 * Revision 3.3 2001/06/22 13:13:02 regina 45 * MLPPP implementation 46 * 47 * Revision 3.2 2001/06/18 17:56:09 daniela 48 * Increased DEF_MTU and TX_QUEUE_LEN. 49 * 50 * Revision 3.1 2001/06/15 12:41:10 regina 51 * upping major version number 52 * 53 * Revision 1.1.1.1 2001/06/13 20:25:06 daniela 54 * PC300 initial CVS version (3.4.0-pre1) 55 * 56 * Revision 2.3 2001/03/05 daniela 57 * Created struct pc300conf, to provide the hardware information to pc300util. 58 * Inclusion of 'alloc_ramsize' field on structure 'pc300hw'. 59 * 60 * Revision 2.2 2000/12/22 daniela 61 * Structures and defines to support pc300util: statistics, status, 62 * loopback tests, trace. 63 * 64 * Revision 2.1 2000/09/28 ivan 65 * Inclusion of 'iophys' and 'iosize' fields on structure 'pc300hw', to 66 * allow release of I/O region at module unload. 67 * Changed location of include files. 68 * 69 * Revision 2.0 2000/03/27 ivan 70 * Added support for the PC300/TE cards. 71 * 72 * Revision 1.1 2000/01/31 ivan 73 * Replaced 'pc300[drv|sca].h' former PC300 driver include files. 74 * 75 * Revision 1.0 1999/12/16 ivan 76 * First official release. 77 * Inclusion of 'nchan' field on structure 'pc300hw', to allow variable 78 * number of ports per card. 79 * Inclusion of 'if_ptr' field on structure 'pc300dev'. 80 * 81 * Revision 0.6 1999/11/17 ivan 82 * Changed X.25-specific function names to comply with adopted convention. 83 * 84 * Revision 0.5 1999/11/16 Daniela Squassoni 85 * X.25 support. 86 * 87 * Revision 0.4 1999/11/15 ivan 88 * Inclusion of 'clock' field on structure 'pc300hw'. 89 * 90 * Revision 0.3 1999/11/10 ivan 91 * IOCTL name changing. 92 * Inclusion of driver function prototypes. 93 * 94 * Revision 0.2 1999/11/03 ivan 95 * Inclusion of 'tx_skb' and union 'ifu' on structure 'pc300dev'. 96 * 97 * Revision 0.1 1999/01/15 ivan 98 * Initial version. 99 * 100 */ 101 102#ifndef _PC300_H 103#define _PC300_H 104 105#include <linux/hdlc.h> 106#include <net/syncppp.h> 107#include "hd64572.h" 108#include "pc300-falc-lh.h" 109 110#ifndef CY_TYPES 111#define CY_TYPES 112typedef __u64 ucdouble; /* 64 bits, unsigned */ 113typedef __u32 uclong; /* 32 bits, unsigned */ 114typedef __u16 ucshort; /* 16 bits, unsigned */ 115typedef __u8 ucchar; /* 8 bits, unsigned */ 116#endif /* CY_TYPES */ 117 118#define PC300_PROTO_MLPPP 1 119 120#define PC300_KERNEL "2.4.x" /* Kernel supported by this driver */ 121 122#define PC300_DEVNAME "hdlc" /* Dev. name base (for hdlc0, hdlc1, etc.) */ 123#define PC300_MAXINDEX 100 /* Max dev. name index (the '0' in hdlc0) */ 124 125#define PC300_MAXCARDS 4 /* Max number of cards per system */ 126#define PC300_MAXCHAN 2 /* Number of channels per card */ 127 128#define PC300_PLX_WIN 0x80 /* PLX control window size (128b) */ 129#define PC300_RAMSIZE 0x40000 /* RAM window size (256Kb) */ 130#define PC300_SCASIZE 0x400 /* SCA window size (1Kb) */ 131#define PC300_FALCSIZE 0x400 /* FALC window size (1Kb) */ 132 133#define PC300_OSC_CLOCK 24576000 134#define PC300_PCI_CLOCK 33000000 135 136#define BD_DEF_LEN 0x0800 /* DMA buffer length (2KB) */ 137#define DMA_TX_MEMSZ 0x8000 /* Total DMA Tx memory size (32KB/ch) */ 138#define DMA_RX_MEMSZ 0x10000 /* Total DMA Rx memory size (64KB/ch) */ 139 140#define N_DMA_TX_BUF (DMA_TX_MEMSZ / BD_DEF_LEN) /* DMA Tx buffers */ 141#define N_DMA_RX_BUF (DMA_RX_MEMSZ / BD_DEF_LEN) /* DMA Rx buffers */ 142 143/* DMA Buffer Offsets */ 144#define DMA_TX_BASE ((N_DMA_TX_BUF + N_DMA_RX_BUF) * \ 145 PC300_MAXCHAN * sizeof(pcsca_bd_t)) 146#define DMA_RX_BASE (DMA_TX_BASE + PC300_MAXCHAN*DMA_TX_MEMSZ) 147 148/* DMA Descriptor Offsets */ 149#define DMA_TX_BD_BASE 0x0000 150#define DMA_RX_BD_BASE (DMA_TX_BD_BASE + ((PC300_MAXCHAN*DMA_TX_MEMSZ / \ 151 BD_DEF_LEN) * sizeof(pcsca_bd_t))) 152 153/* DMA Descriptor Macros */ 154#define TX_BD_ADDR(chan, n) (DMA_TX_BD_BASE + \ 155 ((N_DMA_TX_BUF*chan) + n) * sizeof(pcsca_bd_t)) 156#define RX_BD_ADDR(chan, n) (DMA_RX_BD_BASE + \ 157 ((N_DMA_RX_BUF*chan) + n) * sizeof(pcsca_bd_t)) 158 159/* Macro to access the FALC registers (TE only) */ 160#define F_REG(reg, chan) (0x200*(chan) + ((reg)<<2)) 161 162/*************************************** 163 * Memory access functions/macros * 164 * (required to support Alpha systems) * 165 ***************************************/ 166#ifdef __KERNEL__ 167#define cpc_writeb(port,val) {writeb((ucchar)(val),(port)); mb();} 168#define cpc_writew(port,val) {writew((ushort)(val),(port)); mb();} 169#define cpc_writel(port,val) {writel((uclong)(val),(port)); mb();} 170 171#define cpc_readb(port) readb(port) 172#define cpc_readw(port) readw(port) 173#define cpc_readl(port) readl(port) 174 175#else /* __KERNEL__ */ 176#define cpc_writeb(port,val) (*(volatile ucchar *)(port) = (ucchar)(val)) 177#define cpc_writew(port,val) (*(volatile ucshort *)(port) = (ucshort)(val)) 178#define cpc_writel(port,val) (*(volatile uclong *)(port) = (uclong)(val)) 179 180#define cpc_readb(port) (*(volatile ucchar *)(port)) 181#define cpc_readw(port) (*(volatile ucshort *)(port)) 182#define cpc_readl(port) (*(volatile uclong *)(port)) 183 184#endif /* __KERNEL__ */ 185 186/****** Data Structures *****************************************************/ 187 188/* 189 * RUNTIME_9050 - PLX PCI9050-1 local configuration and shared runtime 190 * registers. This structure can be used to access the 9050 registers 191 * (memory mapped). 192 */ 193struct RUNTIME_9050 { 194 uclong loc_addr_range[4]; /* 00-0Ch : Local Address Ranges */ 195 uclong loc_rom_range; /* 10h : Local ROM Range */ 196 uclong loc_addr_base[4]; /* 14-20h : Local Address Base Addrs */ 197 uclong loc_rom_base; /* 24h : Local ROM Base */ 198 uclong loc_bus_descr[4]; /* 28-34h : Local Bus Descriptors */ 199 uclong rom_bus_descr; /* 38h : ROM Bus Descriptor */ 200 uclong cs_base[4]; /* 3C-48h : Chip Select Base Addrs */ 201 uclong intr_ctrl_stat; /* 4Ch : Interrupt Control/Status */ 202 uclong init_ctrl; /* 50h : EEPROM ctrl, Init Ctrl, etc */ 203}; 204 205#define PLX_9050_LINT1_ENABLE 0x01 206#define PLX_9050_LINT1_POL 0x02 207#define PLX_9050_LINT1_STATUS 0x04 208#define PLX_9050_LINT2_ENABLE 0x08 209#define PLX_9050_LINT2_POL 0x10 210#define PLX_9050_LINT2_STATUS 0x20 211#define PLX_9050_INTR_ENABLE 0x40 212#define PLX_9050_SW_INTR 0x80 213 214/* Masks to access the init_ctrl PLX register */ 215#define PC300_CLKSEL_MASK (0x00000004UL) 216#define PC300_CHMEDIA_MASK(chan) (0x00000020UL<<(chan*3)) 217#define PC300_CTYPE_MASK (0x00000800UL) 218 219/* CPLD Registers (base addr = falcbase, TE only) */ 220/* CPLD v. 0 */ 221#define CPLD_REG1 0x140 /* Chip resets, DCD/CTS status */ 222#define CPLD_REG2 0x144 /* Clock enable , LED control */ 223/* CPLD v. 2 or higher */ 224#define CPLD_V2_REG1 0x100 /* Chip resets, DCD/CTS status */ 225#define CPLD_V2_REG2 0x104 /* Clock enable , LED control */ 226#define CPLD_ID_REG 0x108 /* CPLD version */ 227 228/* CPLD Register bit description: for the FALC bits, they should always be 229 set based on the channel (use (bit<<(2*ch)) to access the correct bit for 230 that channel) */ 231#define CPLD_REG1_FALC_RESET 0x01 232#define CPLD_REG1_SCA_RESET 0x02 233#define CPLD_REG1_GLOBAL_CLK 0x08 234#define CPLD_REG1_FALC_DCD 0x10 235#define CPLD_REG1_FALC_CTS 0x20 236 237#define CPLD_REG2_FALC_TX_CLK 0x01 238#define CPLD_REG2_FALC_RX_CLK 0x02 239#define CPLD_REG2_FALC_LED1 0x10 240#define CPLD_REG2_FALC_LED2 0x20 241 242/* Structure with FALC-related fields (TE only) */ 243#define PC300_FALC_MAXLOOP 0x0000ffff /* for falc_issue_cmd() */ 244 245typedef struct falc { 246 ucchar sync; /* If true FALC is synchronized */ 247 ucchar active; /* if TRUE then already active */ 248 ucchar loop_active; /* if TRUE a line loopback UP was received */ 249 ucchar loop_gen; /* if TRUE a line loopback UP was issued */ 250 251 ucchar num_channels; 252 ucchar offset; /* 1 for T1, 0 for E1 */ 253 ucchar full_bandwidth; 254 255 ucchar xmb_cause; 256 ucchar multiframe_mode; 257 258 /* Statistics */ 259 ucshort pden; /* Pulse Density violation count */ 260 ucshort los; /* Loss of Signal count */ 261 ucshort losr; /* Loss of Signal recovery count */ 262 ucshort lfa; /* Loss of frame alignment count */ 263 ucshort farec; /* Frame Alignment Recovery count */ 264 ucshort lmfa; /* Loss of multiframe alignment count */ 265 ucshort ais; /* Remote Alarm indication Signal count */ 266 ucshort sec; /* One-second timer */ 267 ucshort es; /* Errored second */ 268 ucshort rai; /* remote alarm received */ 269 ucshort bec; 270 ucshort fec; 271 ucshort cvc; 272 ucshort cec; 273 ucshort ebc; 274 275 /* Status */ 276 ucchar red_alarm; 277 ucchar blue_alarm; 278 ucchar loss_fa; 279 ucchar yellow_alarm; 280 ucchar loss_mfa; 281 ucchar prbs; 282} falc_t; 283 284typedef struct falc_status { 285 ucchar sync; /* If true FALC is synchronized */ 286 ucchar red_alarm; 287 ucchar blue_alarm; 288 ucchar loss_fa; 289 ucchar yellow_alarm; 290 ucchar loss_mfa; 291 ucchar prbs; 292} falc_status_t; 293 294typedef struct rsv_x21_status { 295 ucchar dcd; 296 ucchar dsr; 297 ucchar cts; 298 ucchar rts; 299 ucchar dtr; 300} rsv_x21_status_t; 301 302typedef struct pc300stats { 303 int hw_type; 304 uclong line_on; 305 uclong line_off; 306 struct net_device_stats gen_stats; 307 falc_t te_stats; 308} pc300stats_t; 309 310typedef struct pc300status { 311 int hw_type; 312 rsv_x21_status_t gen_status; 313 falc_status_t te_status; 314} pc300status_t; 315 316typedef struct pc300loopback { 317 char loop_type; 318 char loop_on; 319} pc300loopback_t; 320 321typedef struct pc300patterntst { 322 char patrntst_on; /* 0 - off; 1 - on; 2 - read num_errors */ 323 ucshort num_errors; 324} pc300patterntst_t; 325 326typedef struct pc300dev { 327 void *if_ptr; /* General purpose pointer */ 328 struct pc300ch *chan; 329 ucchar trace_on; 330 uclong line_on; /* DCD(X.21, RSV) / sync(TE) change counters */ 331 uclong line_off; 332#ifdef __KERNEL__ 333 char name[16]; 334 struct net_device *dev; 335 336 void *private; 337 struct sk_buff *tx_skb; 338 union { /* This union has all the protocol-specific structures */ 339 struct ppp_device pppdev; 340 }ifu; 341#ifdef CONFIG_PC300_MLPPP 342 void *cpc_tty; /* information to PC300 TTY driver */ 343#endif 344#endif /* __KERNEL__ */ 345}pc300dev_t; 346 347typedef struct pc300hw { 348 int type; /* RSV, X21, etc. */ 349 int bus; /* Bus (PCI, PMC, etc.) */ 350 int nchan; /* number of channels */ 351 int irq; /* interrupt request level */ 352 uclong clock; /* Board clock */ 353 ucchar cpld_id; /* CPLD ID (TE only) */ 354 ucshort cpld_reg1; /* CPLD reg 1 (TE only) */ 355 ucshort cpld_reg2; /* CPLD reg 2 (TE only) */ 356 ucshort gpioc_reg; /* PLX GPIOC reg */ 357 ucshort intctl_reg; /* PLX Int Ctrl/Status reg */ 358 uclong iophys; /* PLX registers I/O base */ 359 uclong iosize; /* PLX registers I/O size */ 360 uclong plxphys; /* PLX registers MMIO base (physical) */ 361 void __iomem * plxbase; /* PLX registers MMIO base (virtual) */ 362 uclong plxsize; /* PLX registers MMIO size */ 363 uclong scaphys; /* SCA registers MMIO base (physical) */ 364 void __iomem * scabase; /* SCA registers MMIO base (virtual) */ 365 uclong scasize; /* SCA registers MMIO size */ 366 uclong ramphys; /* On-board RAM MMIO base (physical) */ 367 void __iomem * rambase; /* On-board RAM MMIO base (virtual) */ 368 uclong alloc_ramsize; /* RAM MMIO size allocated by the PCI bridge */ 369 uclong ramsize; /* On-board RAM MMIO size */ 370 uclong falcphys; /* FALC registers MMIO base (physical) */ 371 void __iomem * falcbase;/* FALC registers MMIO base (virtual) */ 372 uclong falcsize; /* FALC registers MMIO size */ 373} pc300hw_t; 374 375typedef struct pc300chconf { 376 sync_serial_settings phys_settings; /* Clock type/rate (in bps), 377 loopback mode */ 378 raw_hdlc_proto proto_settings; /* Encoding, parity (CRC) */ 379 uclong media; /* HW media (RS232, V.35, etc.) */ 380 uclong proto; /* Protocol (PPP, X.25, etc.) */ 381 ucchar monitor; /* Monitor mode (0 = off, !0 = on) */ 382 383 /* TE-specific parameters */ 384 ucchar lcode; /* Line Code (AMI, B8ZS, etc.) */ 385 ucchar fr_mode; /* Frame Mode (ESF, D4, etc.) */ 386 ucchar lbo; /* Line Build Out */ 387 ucchar rx_sens; /* Rx Sensitivity (long- or short-haul) */ 388 uclong tslot_bitmap; /* bit[i]=1 => timeslot _i_ is active */ 389} pc300chconf_t; 390 391typedef struct pc300ch { 392 struct pc300 *card; 393 int channel; 394 pc300dev_t d; 395 pc300chconf_t conf; 396 ucchar tx_first_bd; /* First TX DMA block descr. w/ data */ 397 ucchar tx_next_bd; /* Next free TX DMA block descriptor */ 398 ucchar rx_first_bd; /* First free RX DMA block descriptor */ 399 ucchar rx_last_bd; /* Last free RX DMA block descriptor */ 400 ucchar nfree_tx_bd; /* Number of free TX DMA block descriptors */ 401 falc_t falc; /* FALC structure (TE only) */ 402} pc300ch_t; 403 404typedef struct pc300 { 405 pc300hw_t hw; /* hardware config. */ 406 pc300ch_t chan[PC300_MAXCHAN]; 407#ifdef __KERNEL__ 408 spinlock_t card_lock; 409#endif /* __KERNEL__ */ 410} pc300_t; 411 412typedef struct pc300conf { 413 pc300hw_t hw; 414 pc300chconf_t conf; 415} pc300conf_t; 416 417/* DEV ioctl() commands */ 418#define N_SPPP_IOCTLS 2 419 420enum pc300_ioctl_cmds { 421 SIOCCPCRESERVED = (SIOCDEVPRIVATE + N_SPPP_IOCTLS), 422 SIOCGPC300CONF, 423 SIOCSPC300CONF, 424 SIOCGPC300STATUS, 425 SIOCGPC300FALCSTATUS, 426 SIOCGPC300UTILSTATS, 427 SIOCGPC300UTILSTATUS, 428 SIOCSPC300TRACE, 429 SIOCSPC300LOOPBACK, 430 SIOCSPC300PATTERNTEST, 431}; 432 433/* Loopback types - PC300/TE boards */ 434enum pc300_loopback_cmds { 435 PC300LOCLOOP = 1, 436 PC300REMLOOP, 437 PC300PAYLOADLOOP, 438 PC300GENLOOPUP, 439 PC300GENLOOPDOWN, 440}; 441 442/* Control Constant Definitions */ 443#define PC300_RSV 0x01 444#define PC300_X21 0x02 445#define PC300_TE 0x03 446 447#define PC300_PCI 0x00 448#define PC300_PMC 0x01 449 450#define PC300_LC_AMI 0x01 451#define PC300_LC_B8ZS 0x02 452#define PC300_LC_NRZ 0x03 453#define PC300_LC_HDB3 0x04 454 455/* Framing (T1) */ 456#define PC300_FR_ESF 0x01 457#define PC300_FR_D4 0x02 458#define PC300_FR_ESF_JAPAN 0x03 459 460/* Framing (E1) */ 461#define PC300_FR_MF_CRC4 0x04 462#define PC300_FR_MF_NON_CRC4 0x05 463#define PC300_FR_UNFRAMED 0x06 464 465#define PC300_LBO_0_DB 0x00 466#define PC300_LBO_7_5_DB 0x01 467#define PC300_LBO_15_DB 0x02 468#define PC300_LBO_22_5_DB 0x03 469 470#define PC300_RX_SENS_SH 0x01 471#define PC300_RX_SENS_LH 0x02 472 473#define PC300_TX_TIMEOUT (2*HZ) 474#define PC300_TX_QUEUE_LEN 100 475#define PC300_DEF_MTU 1600 476 477#ifdef __KERNEL__ 478/* Function Prototypes */ 479void tx_dma_start(pc300_t *, int); 480int cpc_open(struct net_device *dev); 481int cpc_set_media(hdlc_device *, int); 482#endif /* __KERNEL__ */ 483 484#endif /* _PC300_H */ 485