1/* 2 * Definitions for the new Marvell Yukon 2 driver. 3 */ 4#ifndef _SKY2_H 5#define _SKY2_H 6 7#define ETH_JUMBO_MTU 9000 /* Maximum MTU supported */ 8 9/* PCI config registers */ 10enum { 11 PCI_DEV_REG1 = 0x40, 12 PCI_DEV_REG2 = 0x44, 13 PCI_DEV_STATUS = 0x7c, 14 PCI_DEV_REG3 = 0x80, 15 PCI_DEV_REG4 = 0x84, 16 PCI_DEV_REG5 = 0x88, 17}; 18 19enum { 20 PEX_DEV_CAP = 0xe4, 21 PEX_DEV_CTRL = 0xe8, 22 PEX_DEV_STA = 0xea, 23 PEX_LNK_STAT = 0xf2, 24 PEX_UNC_ERR_STAT= 0x104, 25}; 26 27/* Yukon-2 */ 28enum pci_dev_reg_1 { 29 PCI_Y2_PIG_ENA = 1<<31, /* Enable Plug-in-Go (YUKON-2) */ 30 PCI_Y2_DLL_DIS = 1<<30, /* Disable PCI DLL (YUKON-2) */ 31 PCI_Y2_PHY2_COMA = 1<<29, /* Set PHY 2 to Coma Mode (YUKON-2) */ 32 PCI_Y2_PHY1_COMA = 1<<28, /* Set PHY 1 to Coma Mode (YUKON-2) */ 33 PCI_Y2_PHY2_POWD = 1<<27, /* Set PHY 2 to Power Down (YUKON-2) */ 34 PCI_Y2_PHY1_POWD = 1<<26, /* Set PHY 1 to Power Down (YUKON-2) */ 35 PCI_Y2_PME_LEGACY= 1<<15, /* PCI Express legacy power management mode */ 36}; 37 38enum pci_dev_reg_2 { 39 PCI_VPD_WR_THR = 0xffL<<24, /* Bit 31..24: VPD Write Threshold */ 40 PCI_DEV_SEL = 0x7fL<<17, /* Bit 23..17: EEPROM Device Select */ 41 PCI_VPD_ROM_SZ = 7L<<14, /* Bit 16..14: VPD ROM Size */ 42 43 PCI_PATCH_DIR = 0xfL<<8, /* Bit 11.. 8: Ext Patches dir 3..0 */ 44 PCI_EXT_PATCHS = 0xfL<<4, /* Bit 7.. 4: Extended Patches 3..0 */ 45 PCI_EN_DUMMY_RD = 1<<3, /* Enable Dummy Read */ 46 PCI_REV_DESC = 1<<2, /* Reverse Desc. Bytes */ 47 48 PCI_USEDATA64 = 1<<0, /* Use 64Bit Data bus ext */ 49}; 50 51/* PCI_OUR_REG_4 32 bit Our Register 4 (Yukon-ECU only) */ 52enum pci_dev_reg_4 { 53 /* (Link Training & Status State Machine) */ 54 P_TIMER_VALUE_MSK = 0xffL<<16, /* Bit 23..16: Timer Value Mask */ 55 /* (Active State Power Management) */ 56 P_FORCE_ASPM_REQUEST = 1<<15, /* Force ASPM Request (A1 only) */ 57 P_ASPM_GPHY_LINK_DOWN = 1<<14, /* GPHY Link Down (A1 only) */ 58 P_ASPM_INT_FIFO_EMPTY = 1<<13, /* Internal FIFO Empty (A1 only) */ 59 P_ASPM_CLKRUN_REQUEST = 1<<12, /* CLKRUN Request (A1 only) */ 60 61 P_ASPM_FORCE_CLKREQ_ENA = 1<<4, /* Force CLKREQ Enable (A1b only) */ 62 P_ASPM_CLKREQ_PAD_CTL = 1<<3, /* CLKREQ PAD Control (A1 only) */ 63 P_ASPM_A1_MODE_SELECT = 1<<2, /* A1 Mode Select (A1 only) */ 64 P_CLK_GATE_PEX_UNIT_ENA = 1<<1, /* Enable Gate PEX Unit Clock */ 65 P_CLK_GATE_ROOT_COR_ENA = 1<<0, /* Enable Gate Root Core Clock */ 66 P_ASPM_CONTROL_MSK = P_FORCE_ASPM_REQUEST | P_ASPM_GPHY_LINK_DOWN 67 | P_ASPM_CLKRUN_REQUEST | P_ASPM_INT_FIFO_EMPTY, 68}; 69 70 71#define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \ 72 PCI_STATUS_SIG_SYSTEM_ERROR | \ 73 PCI_STATUS_REC_MASTER_ABORT | \ 74 PCI_STATUS_REC_TARGET_ABORT | \ 75 PCI_STATUS_PARITY) 76 77enum pex_dev_ctrl { 78 PEX_DC_MAX_RRS_MSK = 7<<12, /* Bit 14..12: Max. Read Request Size */ 79 PEX_DC_EN_NO_SNOOP = 1<<11,/* Enable No Snoop */ 80 PEX_DC_EN_AUX_POW = 1<<10,/* Enable AUX Power */ 81 PEX_DC_EN_PHANTOM = 1<<9, /* Enable Phantom Functions */ 82 PEX_DC_EN_EXT_TAG = 1<<8, /* Enable Extended Tag Field */ 83 PEX_DC_MAX_PLS_MSK = 7<<5, /* Bit 7.. 5: Max. Payload Size Mask */ 84 PEX_DC_EN_REL_ORD = 1<<4, /* Enable Relaxed Ordering */ 85 PEX_DC_EN_UNS_RQ_RP = 1<<3, /* Enable Unsupported Request Reporting */ 86 PEX_DC_EN_FAT_ER_RP = 1<<2, /* Enable Fatal Error Reporting */ 87 PEX_DC_EN_NFA_ER_RP = 1<<1, /* Enable Non-Fatal Error Reporting */ 88 PEX_DC_EN_COR_ER_RP = 1<<0, /* Enable Correctable Error Reporting */ 89}; 90#define PEX_DC_MAX_RD_RQ_SIZE(x) (((x)<<12) & PEX_DC_MAX_RRS_MSK) 91 92/* PEX_UNC_ERR_STAT PEX Uncorrectable Errors Status Register (Yukon-2) */ 93enum pex_err { 94 PEX_UNSUP_REQ = 1<<20, /* Unsupported Request Error */ 95 96 PEX_MALFOR_TLP = 1<<18, /* Malformed TLP */ 97 98 PEX_UNEXP_COMP = 1<<16, /* Unexpected Completion */ 99 100 PEX_COMP_TO = 1<<14, /* Completion Timeout */ 101 PEX_FLOW_CTRL_P = 1<<13, /* Flow Control Protocol Error */ 102 PEX_POIS_TLP = 1<<12, /* Poisoned TLP */ 103 104 PEX_DATA_LINK_P = 1<<4, /* Data Link Protocol Error */ 105 PEX_FATAL_ERRORS= (PEX_MALFOR_TLP | PEX_FLOW_CTRL_P | PEX_DATA_LINK_P), 106}; 107 108 109enum csr_regs { 110 B0_RAP = 0x0000, 111 B0_CTST = 0x0004, 112 B0_Y2LED = 0x0005, 113 B0_POWER_CTRL = 0x0007, 114 B0_ISRC = 0x0008, 115 B0_IMSK = 0x000c, 116 B0_HWE_ISRC = 0x0010, 117 B0_HWE_IMSK = 0x0014, 118 119 /* Special ISR registers (Yukon-2 only) */ 120 B0_Y2_SP_ISRC2 = 0x001c, 121 B0_Y2_SP_ISRC3 = 0x0020, 122 B0_Y2_SP_EISR = 0x0024, 123 B0_Y2_SP_LISR = 0x0028, 124 B0_Y2_SP_ICR = 0x002c, 125 126 B2_MAC_1 = 0x0100, 127 B2_MAC_2 = 0x0108, 128 B2_MAC_3 = 0x0110, 129 B2_CONN_TYP = 0x0118, 130 B2_PMD_TYP = 0x0119, 131 B2_MAC_CFG = 0x011a, 132 B2_CHIP_ID = 0x011b, 133 B2_E_0 = 0x011c, 134 135 B2_Y2_CLK_GATE = 0x011d, 136 B2_Y2_HW_RES = 0x011e, 137 B2_E_3 = 0x011f, 138 B2_Y2_CLK_CTRL = 0x0120, 139 140 B2_TI_INI = 0x0130, 141 B2_TI_VAL = 0x0134, 142 B2_TI_CTRL = 0x0138, 143 B2_TI_TEST = 0x0139, 144 145 B2_TST_CTRL1 = 0x0158, 146 B2_TST_CTRL2 = 0x0159, 147 B2_GP_IO = 0x015c, 148 149 B2_I2C_CTRL = 0x0160, 150 B2_I2C_DATA = 0x0164, 151 B2_I2C_IRQ = 0x0168, 152 B2_I2C_SW = 0x016c, 153 154 B3_RAM_ADDR = 0x0180, 155 B3_RAM_DATA_LO = 0x0184, 156 B3_RAM_DATA_HI = 0x0188, 157 158/* RAM Interface Registers */ 159/* Yukon-2: use RAM_BUFFER() to access the RAM buffer */ 160/* 161 * The HW-Spec. calls this registers Timeout Value 0..11. But this names are 162 * not usable in SW. Please notice these are NOT real timeouts, these are 163 * the number of qWords transferred continuously. 164 */ 165#define RAM_BUFFER(port, reg) (reg | (port <<6)) 166 167 B3_RI_WTO_R1 = 0x0190, 168 B3_RI_WTO_XA1 = 0x0191, 169 B3_RI_WTO_XS1 = 0x0192, 170 B3_RI_RTO_R1 = 0x0193, 171 B3_RI_RTO_XA1 = 0x0194, 172 B3_RI_RTO_XS1 = 0x0195, 173 B3_RI_WTO_R2 = 0x0196, 174 B3_RI_WTO_XA2 = 0x0197, 175 B3_RI_WTO_XS2 = 0x0198, 176 B3_RI_RTO_R2 = 0x0199, 177 B3_RI_RTO_XA2 = 0x019a, 178 B3_RI_RTO_XS2 = 0x019b, 179 B3_RI_TO_VAL = 0x019c, 180 B3_RI_CTRL = 0x01a0, 181 B3_RI_TEST = 0x01a2, 182 B3_MA_TOINI_RX1 = 0x01b0, 183 B3_MA_TOINI_RX2 = 0x01b1, 184 B3_MA_TOINI_TX1 = 0x01b2, 185 B3_MA_TOINI_TX2 = 0x01b3, 186 B3_MA_TOVAL_RX1 = 0x01b4, 187 B3_MA_TOVAL_RX2 = 0x01b5, 188 B3_MA_TOVAL_TX1 = 0x01b6, 189 B3_MA_TOVAL_TX2 = 0x01b7, 190 B3_MA_TO_CTRL = 0x01b8, 191 B3_MA_TO_TEST = 0x01ba, 192 B3_MA_RCINI_RX1 = 0x01c0, 193 B3_MA_RCINI_RX2 = 0x01c1, 194 B3_MA_RCINI_TX1 = 0x01c2, 195 B3_MA_RCINI_TX2 = 0x01c3, 196 B3_MA_RCVAL_RX1 = 0x01c4, 197 B3_MA_RCVAL_RX2 = 0x01c5, 198 B3_MA_RCVAL_TX1 = 0x01c6, 199 B3_MA_RCVAL_TX2 = 0x01c7, 200 B3_MA_RC_CTRL = 0x01c8, 201 B3_MA_RC_TEST = 0x01ca, 202 B3_PA_TOINI_RX1 = 0x01d0, 203 B3_PA_TOINI_RX2 = 0x01d4, 204 B3_PA_TOINI_TX1 = 0x01d8, 205 B3_PA_TOINI_TX2 = 0x01dc, 206 B3_PA_TOVAL_RX1 = 0x01e0, 207 B3_PA_TOVAL_RX2 = 0x01e4, 208 B3_PA_TOVAL_TX1 = 0x01e8, 209 B3_PA_TOVAL_TX2 = 0x01ec, 210 B3_PA_CTRL = 0x01f0, 211 B3_PA_TEST = 0x01f2, 212 213 Y2_CFG_SPC = 0x1c00, 214}; 215 216/* B0_CTST 16 bit Control/Status register */ 217enum { 218 Y2_VMAIN_AVAIL = 1<<17,/* VMAIN available (YUKON-2 only) */ 219 Y2_VAUX_AVAIL = 1<<16,/* VAUX available (YUKON-2 only) */ 220 Y2_HW_WOL_ON = 1<<15,/* HW WOL On (Yukon-EC Ultra A1 only) */ 221 Y2_HW_WOL_OFF = 1<<14,/* HW WOL On (Yukon-EC Ultra A1 only) */ 222 Y2_ASF_ENABLE = 1<<13,/* ASF Unit Enable (YUKON-2 only) */ 223 Y2_ASF_DISABLE = 1<<12,/* ASF Unit Disable (YUKON-2 only) */ 224 Y2_CLK_RUN_ENA = 1<<11,/* CLK_RUN Enable (YUKON-2 only) */ 225 Y2_CLK_RUN_DIS = 1<<10,/* CLK_RUN Disable (YUKON-2 only) */ 226 Y2_LED_STAT_ON = 1<<9, /* Status LED On (YUKON-2 only) */ 227 Y2_LED_STAT_OFF = 1<<8, /* Status LED Off (YUKON-2 only) */ 228 229 CS_ST_SW_IRQ = 1<<7, /* Set IRQ SW Request */ 230 CS_CL_SW_IRQ = 1<<6, /* Clear IRQ SW Request */ 231 CS_STOP_DONE = 1<<5, /* Stop Master is finished */ 232 CS_STOP_MAST = 1<<4, /* Command Bit to stop the master */ 233 CS_MRST_CLR = 1<<3, /* Clear Master reset */ 234 CS_MRST_SET = 1<<2, /* Set Master reset */ 235 CS_RST_CLR = 1<<1, /* Clear Software reset */ 236 CS_RST_SET = 1, /* Set Software reset */ 237}; 238 239/* B0_LED 8 Bit LED register */ 240enum { 241/* Bit 7.. 2: reserved */ 242 LED_STAT_ON = 1<<1, /* Status LED on */ 243 LED_STAT_OFF = 1, /* Status LED off */ 244}; 245 246/* B0_POWER_CTRL 8 Bit Power Control reg (YUKON only) */ 247enum { 248 PC_VAUX_ENA = 1<<7, /* Switch VAUX Enable */ 249 PC_VAUX_DIS = 1<<6, /* Switch VAUX Disable */ 250 PC_VCC_ENA = 1<<5, /* Switch VCC Enable */ 251 PC_VCC_DIS = 1<<4, /* Switch VCC Disable */ 252 PC_VAUX_ON = 1<<3, /* Switch VAUX On */ 253 PC_VAUX_OFF = 1<<2, /* Switch VAUX Off */ 254 PC_VCC_ON = 1<<1, /* Switch VCC On */ 255 PC_VCC_OFF = 1<<0, /* Switch VCC Off */ 256}; 257 258/* B2_IRQM_MSK 32 bit IRQ Moderation Mask */ 259 260/* B0_Y2_SP_ISRC2 32 bit Special Interrupt Source Reg 2 */ 261/* B0_Y2_SP_ISRC3 32 bit Special Interrupt Source Reg 3 */ 262/* B0_Y2_SP_EISR 32 bit Enter ISR Reg */ 263/* B0_Y2_SP_LISR 32 bit Leave ISR Reg */ 264enum { 265 Y2_IS_HW_ERR = 1<<31, /* Interrupt HW Error */ 266 Y2_IS_STAT_BMU = 1<<30, /* Status BMU Interrupt */ 267 Y2_IS_ASF = 1<<29, /* ASF subsystem Interrupt */ 268 269 Y2_IS_POLL_CHK = 1<<27, /* Check IRQ from polling unit */ 270 Y2_IS_TWSI_RDY = 1<<26, /* IRQ on end of TWSI Tx */ 271 Y2_IS_IRQ_SW = 1<<25, /* SW forced IRQ */ 272 Y2_IS_TIMINT = 1<<24, /* IRQ from Timer */ 273 274 Y2_IS_IRQ_PHY2 = 1<<12, /* Interrupt from PHY 2 */ 275 Y2_IS_IRQ_MAC2 = 1<<11, /* Interrupt from MAC 2 */ 276 Y2_IS_CHK_RX2 = 1<<10, /* Descriptor error Rx 2 */ 277 Y2_IS_CHK_TXS2 = 1<<9, /* Descriptor error TXS 2 */ 278 Y2_IS_CHK_TXA2 = 1<<8, /* Descriptor error TXA 2 */ 279 280 Y2_IS_IRQ_PHY1 = 1<<4, /* Interrupt from PHY 1 */ 281 Y2_IS_IRQ_MAC1 = 1<<3, /* Interrupt from MAC 1 */ 282 Y2_IS_CHK_RX1 = 1<<2, /* Descriptor error Rx 1 */ 283 Y2_IS_CHK_TXS1 = 1<<1, /* Descriptor error TXS 1 */ 284 Y2_IS_CHK_TXA1 = 1<<0, /* Descriptor error TXA 1 */ 285 286 Y2_IS_BASE = Y2_IS_HW_ERR | Y2_IS_STAT_BMU, 287 Y2_IS_PORT_1 = Y2_IS_IRQ_PHY1 | Y2_IS_IRQ_MAC1 288 | Y2_IS_CHK_TXA1 | Y2_IS_CHK_RX1, 289 Y2_IS_PORT_2 = Y2_IS_IRQ_PHY2 | Y2_IS_IRQ_MAC2 290 | Y2_IS_CHK_TXA2 | Y2_IS_CHK_RX2, 291 Y2_IS_ERROR = Y2_IS_HW_ERR | 292 Y2_IS_IRQ_MAC1 | Y2_IS_CHK_TXA1 | Y2_IS_CHK_RX1 | 293 Y2_IS_IRQ_MAC2 | Y2_IS_CHK_TXA2 | Y2_IS_CHK_RX2, 294}; 295 296/* B2_IRQM_HWE_MSK 32 bit IRQ Moderation HW Error Mask */ 297enum { 298 IS_ERR_MSK = 0x00003fff,/* All Error bits */ 299 300 IS_IRQ_TIST_OV = 1<<13, /* Time Stamp Timer Overflow (YUKON only) */ 301 IS_IRQ_SENSOR = 1<<12, /* IRQ from Sensor (YUKON only) */ 302 IS_IRQ_MST_ERR = 1<<11, /* IRQ master error detected */ 303 IS_IRQ_STAT = 1<<10, /* IRQ status exception */ 304 IS_NO_STAT_M1 = 1<<9, /* No Rx Status from MAC 1 */ 305 IS_NO_STAT_M2 = 1<<8, /* No Rx Status from MAC 2 */ 306 IS_NO_TIST_M1 = 1<<7, /* No Time Stamp from MAC 1 */ 307 IS_NO_TIST_M2 = 1<<6, /* No Time Stamp from MAC 2 */ 308 IS_RAM_RD_PAR = 1<<5, /* RAM Read Parity Error */ 309 IS_RAM_WR_PAR = 1<<4, /* RAM Write Parity Error */ 310 IS_M1_PAR_ERR = 1<<3, /* MAC 1 Parity Error */ 311 IS_M2_PAR_ERR = 1<<2, /* MAC 2 Parity Error */ 312 IS_R1_PAR_ERR = 1<<1, /* Queue R1 Parity Error */ 313 IS_R2_PAR_ERR = 1<<0, /* Queue R2 Parity Error */ 314}; 315 316/* Hardware error interrupt mask for Yukon 2 */ 317enum { 318 Y2_IS_TIST_OV = 1<<29,/* Time Stamp Timer overflow interrupt */ 319 Y2_IS_SENSOR = 1<<28, /* Sensor interrupt */ 320 Y2_IS_MST_ERR = 1<<27, /* Master error interrupt */ 321 Y2_IS_IRQ_STAT = 1<<26, /* Status exception interrupt */ 322 Y2_IS_PCI_EXP = 1<<25, /* PCI-Express interrupt */ 323 Y2_IS_PCI_NEXP = 1<<24, /* PCI-Express error similar to PCI error */ 324 /* Link 2 */ 325 Y2_IS_PAR_RD2 = 1<<13, /* Read RAM parity error interrupt */ 326 Y2_IS_PAR_WR2 = 1<<12, /* Write RAM parity error interrupt */ 327 Y2_IS_PAR_MAC2 = 1<<11, /* MAC hardware fault interrupt */ 328 Y2_IS_PAR_RX2 = 1<<10, /* Parity Error Rx Queue 2 */ 329 Y2_IS_TCP_TXS2 = 1<<9, /* TCP length mismatch sync Tx queue IRQ */ 330 Y2_IS_TCP_TXA2 = 1<<8, /* TCP length mismatch async Tx queue IRQ */ 331 /* Link 1 */ 332 Y2_IS_PAR_RD1 = 1<<5, /* Read RAM parity error interrupt */ 333 Y2_IS_PAR_WR1 = 1<<4, /* Write RAM parity error interrupt */ 334 Y2_IS_PAR_MAC1 = 1<<3, /* MAC hardware fault interrupt */ 335 Y2_IS_PAR_RX1 = 1<<2, /* Parity Error Rx Queue 1 */ 336 Y2_IS_TCP_TXS1 = 1<<1, /* TCP length mismatch sync Tx queue IRQ */ 337 Y2_IS_TCP_TXA1 = 1<<0, /* TCP length mismatch async Tx queue IRQ */ 338 339 Y2_HWE_L1_MASK = Y2_IS_PAR_RD1 | Y2_IS_PAR_WR1 | Y2_IS_PAR_MAC1 | 340 Y2_IS_PAR_RX1 | Y2_IS_TCP_TXS1| Y2_IS_TCP_TXA1, 341 Y2_HWE_L2_MASK = Y2_IS_PAR_RD2 | Y2_IS_PAR_WR2 | Y2_IS_PAR_MAC2 | 342 Y2_IS_PAR_RX2 | Y2_IS_TCP_TXS2| Y2_IS_TCP_TXA2, 343 344 Y2_HWE_ALL_MASK = Y2_IS_TIST_OV | Y2_IS_MST_ERR | Y2_IS_IRQ_STAT | 345 Y2_IS_PCI_EXP | 346 Y2_HWE_L1_MASK | Y2_HWE_L2_MASK, 347}; 348 349/* B28_DPT_CTRL 8 bit Descriptor Poll Timer Ctrl Reg */ 350enum { 351 DPT_START = 1<<1, 352 DPT_STOP = 1<<0, 353}; 354 355/* B2_TST_CTRL1 8 bit Test Control Register 1 */ 356enum { 357 TST_FRC_DPERR_MR = 1<<7, /* force DATAPERR on MST RD */ 358 TST_FRC_DPERR_MW = 1<<6, /* force DATAPERR on MST WR */ 359 TST_FRC_DPERR_TR = 1<<5, /* force DATAPERR on TRG RD */ 360 TST_FRC_DPERR_TW = 1<<4, /* force DATAPERR on TRG WR */ 361 TST_FRC_APERR_M = 1<<3, /* force ADDRPERR on MST */ 362 TST_FRC_APERR_T = 1<<2, /* force ADDRPERR on TRG */ 363 TST_CFG_WRITE_ON = 1<<1, /* Enable Config Reg WR */ 364 TST_CFG_WRITE_OFF= 1<<0, /* Disable Config Reg WR */ 365}; 366 367/* B2_MAC_CFG 8 bit MAC Configuration / Chip Revision */ 368enum { 369 CFG_CHIP_R_MSK = 0xf<<4, /* Bit 7.. 4: Chip Revision */ 370 /* Bit 3.. 2: reserved */ 371 CFG_DIS_M2_CLK = 1<<1, /* Disable Clock for 2nd MAC */ 372 CFG_SNG_MAC = 1<<0, /* MAC Config: 0=2 MACs / 1=1 MAC*/ 373}; 374 375/* B2_CHIP_ID 8 bit Chip Identification Number */ 376enum { 377 CHIP_ID_YUKON_XL = 0xb3, /* Chip ID for YUKON-2 XL */ 378 CHIP_ID_YUKON_EC_U = 0xb4, /* Chip ID for YUKON-2 EC Ultra */ 379 CHIP_ID_YUKON_EX = 0xb5, /* Chip ID for YUKON-2 Extreme */ 380 CHIP_ID_YUKON_EC = 0xb6, /* Chip ID for YUKON-2 EC */ 381 CHIP_ID_YUKON_FE = 0xb7, /* Chip ID for YUKON-2 FE */ 382 383 CHIP_REV_YU_EC_A1 = 0, /* Chip Rev. for Yukon-EC A1/A0 */ 384 CHIP_REV_YU_EC_A2 = 1, /* Chip Rev. for Yukon-EC A2 */ 385 CHIP_REV_YU_EC_A3 = 2, /* Chip Rev. for Yukon-EC A3 */ 386 387 CHIP_REV_YU_EC_U_A0 = 1, 388 CHIP_REV_YU_EC_U_A1 = 2, 389 CHIP_REV_YU_EC_U_B0 = 3, 390 391 CHIP_REV_YU_FE_A1 = 1, 392 CHIP_REV_YU_FE_A2 = 2, 393 394}; 395 396/* B2_Y2_CLK_GATE 8 bit Clock Gating (Yukon-2 only) */ 397enum { 398 Y2_STATUS_LNK2_INAC = 1<<7, /* Status Link 2 inactive (0 = active) */ 399 Y2_CLK_GAT_LNK2_DIS = 1<<6, /* Disable clock gating Link 2 */ 400 Y2_COR_CLK_LNK2_DIS = 1<<5, /* Disable Core clock Link 2 */ 401 Y2_PCI_CLK_LNK2_DIS = 1<<4, /* Disable PCI clock Link 2 */ 402 Y2_STATUS_LNK1_INAC = 1<<3, /* Status Link 1 inactive (0 = active) */ 403 Y2_CLK_GAT_LNK1_DIS = 1<<2, /* Disable clock gating Link 1 */ 404 Y2_COR_CLK_LNK1_DIS = 1<<1, /* Disable Core clock Link 1 */ 405 Y2_PCI_CLK_LNK1_DIS = 1<<0, /* Disable PCI clock Link 1 */ 406}; 407 408/* B2_Y2_HW_RES 8 bit HW Resources (Yukon-2 only) */ 409enum { 410 CFG_LED_MODE_MSK = 7<<2, /* Bit 4.. 2: LED Mode Mask */ 411 CFG_LINK_2_AVAIL = 1<<1, /* Link 2 available */ 412 CFG_LINK_1_AVAIL = 1<<0, /* Link 1 available */ 413}; 414#define CFG_LED_MODE(x) (((x) & CFG_LED_MODE_MSK) >> 2) 415#define CFG_DUAL_MAC_MSK (CFG_LINK_2_AVAIL | CFG_LINK_1_AVAIL) 416 417 418/* B2_Y2_CLK_CTRL 32 bit Clock Frequency Control Register (Yukon-2/EC) */ 419enum { 420 Y2_CLK_DIV_VAL_MSK = 0xff<<16,/* Bit 23..16: Clock Divisor Value */ 421#define Y2_CLK_DIV_VAL(x) (((x)<<16) & Y2_CLK_DIV_VAL_MSK) 422 Y2_CLK_DIV_VAL2_MSK = 7<<21, /* Bit 23..21: Clock Divisor Value */ 423 Y2_CLK_SELECT2_MSK = 0x1f<<16,/* Bit 20..16: Clock Select */ 424#define Y2_CLK_DIV_VAL_2(x) (((x)<<21) & Y2_CLK_DIV_VAL2_MSK) 425#define Y2_CLK_SEL_VAL_2(x) (((x)<<16) & Y2_CLK_SELECT2_MSK) 426 Y2_CLK_DIV_ENA = 1<<1, /* Enable Core Clock Division */ 427 Y2_CLK_DIV_DIS = 1<<0, /* Disable Core Clock Division */ 428}; 429 430/* B2_TI_CTRL 8 bit Timer control */ 431/* B2_IRQM_CTRL 8 bit IRQ Moderation Timer Control */ 432enum { 433 TIM_START = 1<<2, /* Start Timer */ 434 TIM_STOP = 1<<1, /* Stop Timer */ 435 TIM_CLR_IRQ = 1<<0, /* Clear Timer IRQ (!IRQM) */ 436}; 437 438/* B2_TI_TEST 8 Bit Timer Test */ 439/* B2_IRQM_TEST 8 bit IRQ Moderation Timer Test */ 440/* B28_DPT_TST 8 bit Descriptor Poll Timer Test Reg */ 441enum { 442 TIM_T_ON = 1<<2, /* Test mode on */ 443 TIM_T_OFF = 1<<1, /* Test mode off */ 444 TIM_T_STEP = 1<<0, /* Test step */ 445}; 446 447/* B3_RAM_ADDR 32 bit RAM Address, to read or write */ 448 /* Bit 31..19: reserved */ 449#define RAM_ADR_RAN 0x0007ffffL /* Bit 18.. 0: RAM Address Range */ 450/* RAM Interface Registers */ 451 452/* B3_RI_CTRL 16 bit RAM Interface Control Register */ 453enum { 454 RI_CLR_RD_PERR = 1<<9, /* Clear IRQ RAM Read Parity Err */ 455 RI_CLR_WR_PERR = 1<<8, /* Clear IRQ RAM Write Parity Err*/ 456 457 RI_RST_CLR = 1<<1, /* Clear RAM Interface Reset */ 458 RI_RST_SET = 1<<0, /* Set RAM Interface Reset */ 459}; 460 461#define SK_RI_TO_53 36 /* RAM interface timeout */ 462 463 464/* Port related registers FIFO, and Arbiter */ 465#define SK_REG(port,reg) (((port)<<7)+(reg)) 466 467/* Transmit Arbiter Registers MAC 1 and 2, use SK_REG() to access */ 468/* TXA_ITI_INI 32 bit Tx Arb Interval Timer Init Val */ 469/* TXA_ITI_VAL 32 bit Tx Arb Interval Timer Value */ 470/* TXA_LIM_INI 32 bit Tx Arb Limit Counter Init Val */ 471/* TXA_LIM_VAL 32 bit Tx Arb Limit Counter Value */ 472 473#define TXA_MAX_VAL 0x00ffffffUL /* Bit 23.. 0: Max TXA Timer/Cnt Val */ 474 475/* TXA_CTRL 8 bit Tx Arbiter Control Register */ 476enum { 477 TXA_ENA_FSYNC = 1<<7, /* Enable force of sync Tx queue */ 478 TXA_DIS_FSYNC = 1<<6, /* Disable force of sync Tx queue */ 479 TXA_ENA_ALLOC = 1<<5, /* Enable alloc of free bandwidth */ 480 TXA_DIS_ALLOC = 1<<4, /* Disable alloc of free bandwidth */ 481 TXA_START_RC = 1<<3, /* Start sync Rate Control */ 482 TXA_STOP_RC = 1<<2, /* Stop sync Rate Control */ 483 TXA_ENA_ARB = 1<<1, /* Enable Tx Arbiter */ 484 TXA_DIS_ARB = 1<<0, /* Disable Tx Arbiter */ 485}; 486 487/* 488 * Bank 4 - 5 489 */ 490/* Transmit Arbiter Registers MAC 1 and 2, use SK_REG() to access */ 491enum { 492 TXA_ITI_INI = 0x0200,/* 32 bit Tx Arb Interval Timer Init Val*/ 493 TXA_ITI_VAL = 0x0204,/* 32 bit Tx Arb Interval Timer Value */ 494 TXA_LIM_INI = 0x0208,/* 32 bit Tx Arb Limit Counter Init Val */ 495 TXA_LIM_VAL = 0x020c,/* 32 bit Tx Arb Limit Counter Value */ 496 TXA_CTRL = 0x0210,/* 8 bit Tx Arbiter Control Register */ 497 TXA_TEST = 0x0211,/* 8 bit Tx Arbiter Test Register */ 498 TXA_STAT = 0x0212,/* 8 bit Tx Arbiter Status Register */ 499}; 500 501 502enum { 503 B6_EXT_REG = 0x0300,/* External registers (GENESIS only) */ 504 B7_CFG_SPC = 0x0380,/* copy of the Configuration register */ 505 B8_RQ1_REGS = 0x0400,/* Receive Queue 1 */ 506 B8_RQ2_REGS = 0x0480,/* Receive Queue 2 */ 507 B8_TS1_REGS = 0x0600,/* Transmit sync queue 1 */ 508 B8_TA1_REGS = 0x0680,/* Transmit async queue 1 */ 509 B8_TS2_REGS = 0x0700,/* Transmit sync queue 2 */ 510 B8_TA2_REGS = 0x0780,/* Transmit sync queue 2 */ 511 B16_RAM_REGS = 0x0800,/* RAM Buffer Registers */ 512}; 513 514/* Queue Register Offsets, use Q_ADDR() to access */ 515enum { 516 B8_Q_REGS = 0x0400, /* base of Queue registers */ 517 Q_D = 0x00, /* 8*32 bit Current Descriptor */ 518 Q_DA_L = 0x20, /* 32 bit Current Descriptor Address Low dWord */ 519 Q_DA_H = 0x24, /* 32 bit Current Descriptor Address High dWord */ 520 Q_AC_L = 0x28, /* 32 bit Current Address Counter Low dWord */ 521 Q_AC_H = 0x2c, /* 32 bit Current Address Counter High dWord */ 522 Q_BC = 0x30, /* 32 bit Current Byte Counter */ 523 Q_CSR = 0x34, /* 32 bit BMU Control/Status Register */ 524 Q_F = 0x38, /* 32 bit Flag Register */ 525 Q_T1 = 0x3c, /* 32 bit Test Register 1 */ 526 Q_T1_TR = 0x3c, /* 8 bit Test Register 1 Transfer SM */ 527 Q_T1_WR = 0x3d, /* 8 bit Test Register 1 Write Descriptor SM */ 528 Q_T1_RD = 0x3e, /* 8 bit Test Register 1 Read Descriptor SM */ 529 Q_T1_SV = 0x3f, /* 8 bit Test Register 1 Supervisor SM */ 530 Q_T2 = 0x40, /* 32 bit Test Register 2 */ 531 Q_T3 = 0x44, /* 32 bit Test Register 3 */ 532 533/* Yukon-2 */ 534 Q_DONE = 0x24, /* 16 bit Done Index (Yukon-2 only) */ 535 Q_WM = 0x40, /* 16 bit FIFO Watermark */ 536 Q_AL = 0x42, /* 8 bit FIFO Alignment */ 537 Q_RSP = 0x44, /* 16 bit FIFO Read Shadow Pointer */ 538 Q_RSL = 0x46, /* 8 bit FIFO Read Shadow Level */ 539 Q_RP = 0x48, /* 8 bit FIFO Read Pointer */ 540 Q_RL = 0x4a, /* 8 bit FIFO Read Level */ 541 Q_WP = 0x4c, /* 8 bit FIFO Write Pointer */ 542 Q_WSP = 0x4d, /* 8 bit FIFO Write Shadow Pointer */ 543 Q_WL = 0x4e, /* 8 bit FIFO Write Level */ 544 Q_WSL = 0x4f, /* 8 bit FIFO Write Shadow Level */ 545}; 546#define Q_ADDR(reg, offs) (B8_Q_REGS + (reg) + (offs)) 547 548/* Q_F 32 bit Flag Register */ 549enum { 550 F_ALM_FULL = 1<<27, /* Rx FIFO: almost full */ 551 F_EMPTY = 1<<27, /* Tx FIFO: empty flag */ 552 F_FIFO_EOF = 1<<26, /* Tag (EOF Flag) bit in FIFO */ 553 F_WM_REACHED = 1<<25, /* Watermark reached */ 554 F_M_RX_RAM_DIS = 1<<24, /* MAC Rx RAM Read Port disable */ 555 F_FIFO_LEVEL = 0x1fL<<16, /* Bit 23..16: # of Qwords in FIFO */ 556 F_WATER_MARK = 0x0007ffL, /* Bit 10.. 0: Watermark */ 557}; 558 559/* Queue Prefetch Unit Offsets, use Y2_QADDR() to address (Yukon-2 only)*/ 560enum { 561 Y2_B8_PREF_REGS = 0x0450, 562 563 PREF_UNIT_CTRL = 0x00, /* 32 bit Control register */ 564 PREF_UNIT_LAST_IDX = 0x04, /* 16 bit Last Index */ 565 PREF_UNIT_ADDR_LO = 0x08, /* 32 bit List start addr, low part */ 566 PREF_UNIT_ADDR_HI = 0x0c, /* 32 bit List start addr, high part*/ 567 PREF_UNIT_GET_IDX = 0x10, /* 16 bit Get Index */ 568 PREF_UNIT_PUT_IDX = 0x14, /* 16 bit Put Index */ 569 PREF_UNIT_FIFO_WP = 0x20, /* 8 bit FIFO write pointer */ 570 PREF_UNIT_FIFO_RP = 0x24, /* 8 bit FIFO read pointer */ 571 PREF_UNIT_FIFO_WM = 0x28, /* 8 bit FIFO watermark */ 572 PREF_UNIT_FIFO_LEV = 0x2c, /* 8 bit FIFO level */ 573 574 PREF_UNIT_MASK_IDX = 0x0fff, 575}; 576#define Y2_QADDR(q,reg) (Y2_B8_PREF_REGS + (q) + (reg)) 577 578/* RAM Buffer Register Offsets */ 579enum { 580 581 RB_START = 0x00,/* 32 bit RAM Buffer Start Address */ 582 RB_END = 0x04,/* 32 bit RAM Buffer End Address */ 583 RB_WP = 0x08,/* 32 bit RAM Buffer Write Pointer */ 584 RB_RP = 0x0c,/* 32 bit RAM Buffer Read Pointer */ 585 RB_RX_UTPP = 0x10,/* 32 bit Rx Upper Threshold, Pause Packet */ 586 RB_RX_LTPP = 0x14,/* 32 bit Rx Lower Threshold, Pause Packet */ 587 RB_RX_UTHP = 0x18,/* 32 bit Rx Upper Threshold, High Prio */ 588 RB_RX_LTHP = 0x1c,/* 32 bit Rx Lower Threshold, High Prio */ 589 /* 0x10 - 0x1f: reserved at Tx RAM Buffer Registers */ 590 RB_PC = 0x20,/* 32 bit RAM Buffer Packet Counter */ 591 RB_LEV = 0x24,/* 32 bit RAM Buffer Level Register */ 592 RB_CTRL = 0x28,/* 32 bit RAM Buffer Control Register */ 593 RB_TST1 = 0x29,/* 8 bit RAM Buffer Test Register 1 */ 594 RB_TST2 = 0x2a,/* 8 bit RAM Buffer Test Register 2 */ 595}; 596 597/* Receive and Transmit Queues */ 598enum { 599 Q_R1 = 0x0000, /* Receive Queue 1 */ 600 Q_R2 = 0x0080, /* Receive Queue 2 */ 601 Q_XS1 = 0x0200, /* Synchronous Transmit Queue 1 */ 602 Q_XA1 = 0x0280, /* Asynchronous Transmit Queue 1 */ 603 Q_XS2 = 0x0300, /* Synchronous Transmit Queue 2 */ 604 Q_XA2 = 0x0380, /* Asynchronous Transmit Queue 2 */ 605}; 606 607/* Different PHY Types */ 608enum { 609 PHY_ADDR_MARV = 0, 610}; 611 612#define RB_ADDR(offs, queue) ((u16) B16_RAM_REGS + (queue) + (offs)) 613 614 615enum { 616 LNK_SYNC_INI = 0x0c30,/* 32 bit Link Sync Cnt Init Value */ 617 LNK_SYNC_VAL = 0x0c34,/* 32 bit Link Sync Cnt Current Value */ 618 LNK_SYNC_CTRL = 0x0c38,/* 8 bit Link Sync Cnt Control Register */ 619 LNK_SYNC_TST = 0x0c39,/* 8 bit Link Sync Cnt Test Register */ 620 621 LNK_LED_REG = 0x0c3c,/* 8 bit Link LED Register */ 622 623/* Receive GMAC FIFO (YUKON and Yukon-2) */ 624 625 RX_GMF_EA = 0x0c40,/* 32 bit Rx GMAC FIFO End Address */ 626 RX_GMF_AF_THR = 0x0c44,/* 32 bit Rx GMAC FIFO Almost Full Thresh. */ 627 RX_GMF_CTRL_T = 0x0c48,/* 32 bit Rx GMAC FIFO Control/Test */ 628 RX_GMF_FL_MSK = 0x0c4c,/* 32 bit Rx GMAC FIFO Flush Mask */ 629 RX_GMF_FL_THR = 0x0c50,/* 32 bit Rx GMAC FIFO Flush Threshold */ 630 RX_GMF_TR_THR = 0x0c54,/* 32 bit Rx Truncation Threshold (Yukon-2) */ 631 RX_GMF_UP_THR = 0x0c58,/* 8 bit Rx Upper Pause Thr (Yukon-EC_U) */ 632 RX_GMF_LP_THR = 0x0c5a,/* 8 bit Rx Lower Pause Thr (Yukon-EC_U) */ 633 RX_GMF_VLAN = 0x0c5c,/* 32 bit Rx VLAN Type Register (Yukon-2) */ 634 RX_GMF_WP = 0x0c60,/* 32 bit Rx GMAC FIFO Write Pointer */ 635 636 RX_GMF_WLEV = 0x0c68,/* 32 bit Rx GMAC FIFO Write Level */ 637 638 RX_GMF_RP = 0x0c70,/* 32 bit Rx GMAC FIFO Read Pointer */ 639 640 RX_GMF_RLEV = 0x0c78,/* 32 bit Rx GMAC FIFO Read Level */ 641}; 642 643 644/* Q_BC 32 bit Current Byte Counter */ 645 646/* BMU Control Status Registers */ 647/* B0_R1_CSR 32 bit BMU Ctrl/Stat Rx Queue 1 */ 648/* B0_R2_CSR 32 bit BMU Ctrl/Stat Rx Queue 2 */ 649/* B0_XA1_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 1 */ 650/* B0_XS1_CSR 32 bit BMU Ctrl/Stat Async Tx Queue 1 */ 651/* B0_XA2_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 2 */ 652/* B0_XS2_CSR 32 bit BMU Ctrl/Stat Async Tx Queue 2 */ 653/* Q_CSR 32 bit BMU Control/Status Register */ 654 655/* Rx BMU Control / Status Registers (Yukon-2) */ 656enum { 657 BMU_IDLE = 1<<31, /* BMU Idle State */ 658 BMU_RX_TCP_PKT = 1<<30, /* Rx TCP Packet (when RSS Hash enabled) */ 659 BMU_RX_IP_PKT = 1<<29, /* Rx IP Packet (when RSS Hash enabled) */ 660 661 BMU_ENA_RX_RSS_HASH = 1<<15, /* Enable Rx RSS Hash */ 662 BMU_DIS_RX_RSS_HASH = 1<<14, /* Disable Rx RSS Hash */ 663 BMU_ENA_RX_CHKSUM = 1<<13, /* Enable Rx TCP/IP Checksum Check */ 664 BMU_DIS_RX_CHKSUM = 1<<12, /* Disable Rx TCP/IP Checksum Check */ 665 BMU_CLR_IRQ_PAR = 1<<11, /* Clear IRQ on Parity errors (Rx) */ 666 BMU_CLR_IRQ_TCP = 1<<11, /* Clear IRQ on TCP segment. error (Tx) */ 667 BMU_CLR_IRQ_CHK = 1<<10, /* Clear IRQ Check */ 668 BMU_STOP = 1<<9, /* Stop Rx/Tx Queue */ 669 BMU_START = 1<<8, /* Start Rx/Tx Queue */ 670 BMU_FIFO_OP_ON = 1<<7, /* FIFO Operational On */ 671 BMU_FIFO_OP_OFF = 1<<6, /* FIFO Operational Off */ 672 BMU_FIFO_ENA = 1<<5, /* Enable FIFO */ 673 BMU_FIFO_RST = 1<<4, /* Reset FIFO */ 674 BMU_OP_ON = 1<<3, /* BMU Operational On */ 675 BMU_OP_OFF = 1<<2, /* BMU Operational Off */ 676 BMU_RST_CLR = 1<<1, /* Clear BMU Reset (Enable) */ 677 BMU_RST_SET = 1<<0, /* Set BMU Reset */ 678 679 BMU_CLR_RESET = BMU_FIFO_RST | BMU_OP_OFF | BMU_RST_CLR, 680 BMU_OPER_INIT = BMU_CLR_IRQ_PAR | BMU_CLR_IRQ_CHK | BMU_START | 681 BMU_FIFO_ENA | BMU_OP_ON, 682 683 BMU_WM_DEFAULT = 0x600, 684 BMU_WM_PEX = 0x80, 685}; 686 687/* Tx BMU Control / Status Registers (Yukon-2) */ 688 /* Bit 31: same as for Rx */ 689enum { 690 BMU_TX_IPIDINCR_ON = 1<<13, /* Enable IP ID Increment */ 691 BMU_TX_IPIDINCR_OFF = 1<<12, /* Disable IP ID Increment */ 692 BMU_TX_CLR_IRQ_TCP = 1<<11, /* Clear IRQ on TCP segment length mismatch */ 693}; 694 695/* Queue Prefetch Unit Offsets, use Y2_QADDR() to address (Yukon-2 only)*/ 696/* PREF_UNIT_CTRL 32 bit Prefetch Control register */ 697enum { 698 PREF_UNIT_OP_ON = 1<<3, /* prefetch unit operational */ 699 PREF_UNIT_OP_OFF = 1<<2, /* prefetch unit not operational */ 700 PREF_UNIT_RST_CLR = 1<<1, /* Clear Prefetch Unit Reset */ 701 PREF_UNIT_RST_SET = 1<<0, /* Set Prefetch Unit Reset */ 702}; 703 704/* RAM Buffer Register Offsets, use RB_ADDR(Queue, Offs) to access */ 705/* RB_START 32 bit RAM Buffer Start Address */ 706/* RB_END 32 bit RAM Buffer End Address */ 707/* RB_WP 32 bit RAM Buffer Write Pointer */ 708/* RB_RP 32 bit RAM Buffer Read Pointer */ 709/* RB_RX_UTPP 32 bit Rx Upper Threshold, Pause Pack */ 710/* RB_RX_LTPP 32 bit Rx Lower Threshold, Pause Pack */ 711/* RB_RX_UTHP 32 bit Rx Upper Threshold, High Prio */ 712/* RB_RX_LTHP 32 bit Rx Lower Threshold, High Prio */ 713/* RB_PC 32 bit RAM Buffer Packet Counter */ 714/* RB_LEV 32 bit RAM Buffer Level Register */ 715 716#define RB_MSK 0x0007ffff /* Bit 18.. 0: RAM Buffer Pointer Bits */ 717/* RB_TST2 8 bit RAM Buffer Test Register 2 */ 718/* RB_TST1 8 bit RAM Buffer Test Register 1 */ 719 720/* RB_CTRL 8 bit RAM Buffer Control Register */ 721enum { 722 RB_ENA_STFWD = 1<<5, /* Enable Store & Forward */ 723 RB_DIS_STFWD = 1<<4, /* Disable Store & Forward */ 724 RB_ENA_OP_MD = 1<<3, /* Enable Operation Mode */ 725 RB_DIS_OP_MD = 1<<2, /* Disable Operation Mode */ 726 RB_RST_CLR = 1<<1, /* Clear RAM Buf STM Reset */ 727 RB_RST_SET = 1<<0, /* Set RAM Buf STM Reset */ 728}; 729 730 731/* Transmit GMAC FIFO (YUKON only) */ 732enum { 733 TX_GMF_EA = 0x0d40,/* 32 bit Tx GMAC FIFO End Address */ 734 TX_GMF_AE_THR = 0x0d44,/* 32 bit Tx GMAC FIFO Almost Empty Thresh.*/ 735 TX_GMF_CTRL_T = 0x0d48,/* 32 bit Tx GMAC FIFO Control/Test */ 736 737 TX_GMF_WP = 0x0d60,/* 32 bit Tx GMAC FIFO Write Pointer */ 738 TX_GMF_WSP = 0x0d64,/* 32 bit Tx GMAC FIFO Write Shadow Ptr. */ 739 TX_GMF_WLEV = 0x0d68,/* 32 bit Tx GMAC FIFO Write Level */ 740 741 TX_GMF_RP = 0x0d70,/* 32 bit Tx GMAC FIFO Read Pointer */ 742 TX_GMF_RSTP = 0x0d74,/* 32 bit Tx GMAC FIFO Restart Pointer */ 743 TX_GMF_RLEV = 0x0d78,/* 32 bit Tx GMAC FIFO Read Level */ 744 745 /* Threshold values for Yukon-EC Ultra and Extreme */ 746 ECU_AE_THR = 0x0070, /* Almost Empty Threshold */ 747 ECU_TXFF_LEV = 0x01a0, /* Tx BMU FIFO Level */ 748 ECU_JUMBO_WM = 0x0080, /* Jumbo Mode Watermark */ 749}; 750 751/* Descriptor Poll Timer Registers */ 752enum { 753 B28_DPT_INI = 0x0e00,/* 24 bit Descriptor Poll Timer Init Val */ 754 B28_DPT_VAL = 0x0e04,/* 24 bit Descriptor Poll Timer Curr Val */ 755 B28_DPT_CTRL = 0x0e08,/* 8 bit Descriptor Poll Timer Ctrl Reg */ 756 757 B28_DPT_TST = 0x0e0a,/* 8 bit Descriptor Poll Timer Test Reg */ 758}; 759 760/* Time Stamp Timer Registers (YUKON only) */ 761enum { 762 GMAC_TI_ST_VAL = 0x0e14,/* 32 bit Time Stamp Timer Curr Val */ 763 GMAC_TI_ST_CTRL = 0x0e18,/* 8 bit Time Stamp Timer Ctrl Reg */ 764 GMAC_TI_ST_TST = 0x0e1a,/* 8 bit Time Stamp Timer Test Reg */ 765}; 766 767/* Polling Unit Registers (Yukon-2 only) */ 768enum { 769 POLL_CTRL = 0x0e20, /* 32 bit Polling Unit Control Reg */ 770 POLL_LAST_IDX = 0x0e24,/* 16 bit Polling Unit List Last Index */ 771 772 POLL_LIST_ADDR_LO= 0x0e28,/* 32 bit Poll. List Start Addr (low) */ 773 POLL_LIST_ADDR_HI= 0x0e2c,/* 32 bit Poll. List Start Addr (high) */ 774}; 775 776enum { 777 SMB_CFG = 0x0e40, /* 32 bit SMBus Config Register */ 778 SMB_CSR = 0x0e44, /* 32 bit SMBus Control/Status Register */ 779}; 780 781enum { 782 CPU_WDOG = 0x0e48, /* 32 bit Watchdog Register */ 783 CPU_CNTR = 0x0e4C, /* 32 bit Counter Register */ 784 CPU_TIM = 0x0e50,/* 32 bit Timer Compare Register */ 785 CPU_AHB_ADDR = 0x0e54, /* 32 bit CPU AHB Debug Register */ 786 CPU_AHB_WDATA = 0x0e58, /* 32 bit CPU AHB Debug Register */ 787 CPU_AHB_RDATA = 0x0e5C, /* 32 bit CPU AHB Debug Register */ 788 HCU_MAP_BASE = 0x0e60, /* 32 bit Reset Mapping Base */ 789 CPU_AHB_CTRL = 0x0e64, /* 32 bit CPU AHB Debug Register */ 790 HCU_CCSR = 0x0e68, /* 32 bit CPU Control and Status Register */ 791 HCU_HCSR = 0x0e6C, /* 32 bit Host Control and Status Register */ 792}; 793 794/* ASF Subsystem Registers (Yukon-2 only) */ 795enum { 796 B28_Y2_SMB_CONFIG = 0x0e40,/* 32 bit ASF SMBus Config Register */ 797 B28_Y2_SMB_CSD_REG = 0x0e44,/* 32 bit ASF SMB Control/Status/Data */ 798 B28_Y2_ASF_IRQ_V_BASE=0x0e60,/* 32 bit ASF IRQ Vector Base */ 799 800 B28_Y2_ASF_STAT_CMD= 0x0e68,/* 32 bit ASF Status and Command Reg */ 801 B28_Y2_ASF_HOST_COM= 0x0e6c,/* 32 bit ASF Host Communication Reg */ 802 B28_Y2_DATA_REG_1 = 0x0e70,/* 32 bit ASF/Host Data Register 1 */ 803 B28_Y2_DATA_REG_2 = 0x0e74,/* 32 bit ASF/Host Data Register 2 */ 804 B28_Y2_DATA_REG_3 = 0x0e78,/* 32 bit ASF/Host Data Register 3 */ 805 B28_Y2_DATA_REG_4 = 0x0e7c,/* 32 bit ASF/Host Data Register 4 */ 806}; 807 808/* Status BMU Registers (Yukon-2 only)*/ 809enum { 810 STAT_CTRL = 0x0e80,/* 32 bit Status BMU Control Reg */ 811 STAT_LAST_IDX = 0x0e84,/* 16 bit Status BMU Last Index */ 812 813 STAT_LIST_ADDR_LO= 0x0e88,/* 32 bit Status List Start Addr (low) */ 814 STAT_LIST_ADDR_HI= 0x0e8c,/* 32 bit Status List Start Addr (high) */ 815 STAT_TXA1_RIDX = 0x0e90,/* 16 bit Status TxA1 Report Index Reg */ 816 STAT_TXS1_RIDX = 0x0e92,/* 16 bit Status TxS1 Report Index Reg */ 817 STAT_TXA2_RIDX = 0x0e94,/* 16 bit Status TxA2 Report Index Reg */ 818 STAT_TXS2_RIDX = 0x0e96,/* 16 bit Status TxS2 Report Index Reg */ 819 STAT_TX_IDX_TH = 0x0e98,/* 16 bit Status Tx Index Threshold Reg */ 820 STAT_PUT_IDX = 0x0e9c,/* 16 bit Status Put Index Reg */ 821 822/* FIFO Control/Status Registers (Yukon-2 only)*/ 823 STAT_FIFO_WP = 0x0ea0,/* 8 bit Status FIFO Write Pointer Reg */ 824 STAT_FIFO_RP = 0x0ea4,/* 8 bit Status FIFO Read Pointer Reg */ 825 STAT_FIFO_RSP = 0x0ea6,/* 8 bit Status FIFO Read Shadow Ptr */ 826 STAT_FIFO_LEVEL = 0x0ea8,/* 8 bit Status FIFO Level Reg */ 827 STAT_FIFO_SHLVL = 0x0eaa,/* 8 bit Status FIFO Shadow Level Reg */ 828 STAT_FIFO_WM = 0x0eac,/* 8 bit Status FIFO Watermark Reg */ 829 STAT_FIFO_ISR_WM= 0x0ead,/* 8 bit Status FIFO ISR Watermark Reg */ 830 831/* Level and ISR Timer Registers (Yukon-2 only)*/ 832 STAT_LEV_TIMER_INI= 0x0eb0,/* 32 bit Level Timer Init. Value Reg */ 833 STAT_LEV_TIMER_CNT= 0x0eb4,/* 32 bit Level Timer Counter Reg */ 834 STAT_LEV_TIMER_CTRL= 0x0eb8,/* 8 bit Level Timer Control Reg */ 835 STAT_LEV_TIMER_TEST= 0x0eb9,/* 8 bit Level Timer Test Reg */ 836 STAT_TX_TIMER_INI = 0x0ec0,/* 32 bit Tx Timer Init. Value Reg */ 837 STAT_TX_TIMER_CNT = 0x0ec4,/* 32 bit Tx Timer Counter Reg */ 838 STAT_TX_TIMER_CTRL = 0x0ec8,/* 8 bit Tx Timer Control Reg */ 839 STAT_TX_TIMER_TEST = 0x0ec9,/* 8 bit Tx Timer Test Reg */ 840 STAT_ISR_TIMER_INI = 0x0ed0,/* 32 bit ISR Timer Init. Value Reg */ 841 STAT_ISR_TIMER_CNT = 0x0ed4,/* 32 bit ISR Timer Counter Reg */ 842 STAT_ISR_TIMER_CTRL= 0x0ed8,/* 8 bit ISR Timer Control Reg */ 843 STAT_ISR_TIMER_TEST= 0x0ed9,/* 8 bit ISR Timer Test Reg */ 844}; 845 846enum { 847 LINKLED_OFF = 0x01, 848 LINKLED_ON = 0x02, 849 LINKLED_LINKSYNC_OFF = 0x04, 850 LINKLED_LINKSYNC_ON = 0x08, 851 LINKLED_BLINK_OFF = 0x10, 852 LINKLED_BLINK_ON = 0x20, 853}; 854 855/* GMAC and GPHY Control Registers (YUKON only) */ 856enum { 857 GMAC_CTRL = 0x0f00,/* 32 bit GMAC Control Reg */ 858 GPHY_CTRL = 0x0f04,/* 32 bit GPHY Control Reg */ 859 GMAC_IRQ_SRC = 0x0f08,/* 8 bit GMAC Interrupt Source Reg */ 860 GMAC_IRQ_MSK = 0x0f0c,/* 8 bit GMAC Interrupt Mask Reg */ 861 GMAC_LINK_CTRL = 0x0f10,/* 16 bit Link Control Reg */ 862 863/* Wake-up Frame Pattern Match Control Registers (YUKON only) */ 864 WOL_CTRL_STAT = 0x0f20,/* 16 bit WOL Control/Status Reg */ 865 WOL_MATCH_CTL = 0x0f22,/* 8 bit WOL Match Control Reg */ 866 WOL_MATCH_RES = 0x0f23,/* 8 bit WOL Match Result Reg */ 867 WOL_MAC_ADDR = 0x0f24,/* 32 bit WOL MAC Address */ 868 WOL_PATT_RPTR = 0x0f2c,/* 8 bit WOL Pattern Read Pointer */ 869 870/* WOL Pattern Length Registers (YUKON only) */ 871 WOL_PATT_LEN_LO = 0x0f30,/* 32 bit WOL Pattern Length 3..0 */ 872 WOL_PATT_LEN_HI = 0x0f34,/* 24 bit WOL Pattern Length 6..4 */ 873 874/* WOL Pattern Counter Registers (YUKON only) */ 875 WOL_PATT_CNT_0 = 0x0f38,/* 32 bit WOL Pattern Counter 3..0 */ 876 WOL_PATT_CNT_4 = 0x0f3c,/* 24 bit WOL Pattern Counter 6..4 */ 877}; 878#define WOL_REGS(port, x) (x + (port)*0x80) 879 880enum { 881 WOL_PATT_RAM_1 = 0x1000,/* WOL Pattern RAM Link 1 */ 882 WOL_PATT_RAM_2 = 0x1400,/* WOL Pattern RAM Link 2 */ 883}; 884#define WOL_PATT_RAM_BASE(port) (WOL_PATT_RAM_1 + (port)*0x400) 885 886enum { 887 BASE_GMAC_1 = 0x2800,/* GMAC 1 registers */ 888 BASE_GMAC_2 = 0x3800,/* GMAC 2 registers */ 889}; 890 891/* 892 * Marvel-PHY Registers, indirect addressed over GMAC 893 */ 894enum { 895 PHY_MARV_CTRL = 0x00,/* 16 bit r/w PHY Control Register */ 896 PHY_MARV_STAT = 0x01,/* 16 bit r/o PHY Status Register */ 897 PHY_MARV_ID0 = 0x02,/* 16 bit r/o PHY ID0 Register */ 898 PHY_MARV_ID1 = 0x03,/* 16 bit r/o PHY ID1 Register */ 899 PHY_MARV_AUNE_ADV = 0x04,/* 16 bit r/w Auto-Neg. Advertisement */ 900 PHY_MARV_AUNE_LP = 0x05,/* 16 bit r/o Link Part Ability Reg */ 901 PHY_MARV_AUNE_EXP = 0x06,/* 16 bit r/o Auto-Neg. Expansion Reg */ 902 PHY_MARV_NEPG = 0x07,/* 16 bit r/w Next Page Register */ 903 PHY_MARV_NEPG_LP = 0x08,/* 16 bit r/o Next Page Link Partner */ 904 /* Marvel-specific registers */ 905 PHY_MARV_1000T_CTRL = 0x09,/* 16 bit r/w 1000Base-T Control Reg */ 906 PHY_MARV_1000T_STAT = 0x0a,/* 16 bit r/o 1000Base-T Status Reg */ 907 PHY_MARV_EXT_STAT = 0x0f,/* 16 bit r/o Extended Status Reg */ 908 PHY_MARV_PHY_CTRL = 0x10,/* 16 bit r/w PHY Specific Ctrl Reg */ 909 PHY_MARV_PHY_STAT = 0x11,/* 16 bit r/o PHY Specific Stat Reg */ 910 PHY_MARV_INT_MASK = 0x12,/* 16 bit r/w Interrupt Mask Reg */ 911 PHY_MARV_INT_STAT = 0x13,/* 16 bit r/o Interrupt Status Reg */ 912 PHY_MARV_EXT_CTRL = 0x14,/* 16 bit r/w Ext. PHY Specific Ctrl */ 913 PHY_MARV_RXE_CNT = 0x15,/* 16 bit r/w Receive Error Counter */ 914 PHY_MARV_EXT_ADR = 0x16,/* 16 bit r/w Ext. Ad. for Cable Diag. */ 915 PHY_MARV_PORT_IRQ = 0x17,/* 16 bit r/o Port 0 IRQ (88E1111 only) */ 916 PHY_MARV_LED_CTRL = 0x18,/* 16 bit r/w LED Control Reg */ 917 PHY_MARV_LED_OVER = 0x19,/* 16 bit r/w Manual LED Override Reg */ 918 PHY_MARV_EXT_CTRL_2 = 0x1a,/* 16 bit r/w Ext. PHY Specific Ctrl 2 */ 919 PHY_MARV_EXT_P_STAT = 0x1b,/* 16 bit r/w Ext. PHY Spec. Stat Reg */ 920 PHY_MARV_CABLE_DIAG = 0x1c,/* 16 bit r/o Cable Diagnostic Reg */ 921 PHY_MARV_PAGE_ADDR = 0x1d,/* 16 bit r/w Extended Page Address Reg */ 922 PHY_MARV_PAGE_DATA = 0x1e,/* 16 bit r/w Extended Page Data Reg */ 923 924/* for 10/100 Fast Ethernet PHY (88E3082 only) */ 925 PHY_MARV_FE_LED_PAR = 0x16,/* 16 bit r/w LED Parallel Select Reg. */ 926 PHY_MARV_FE_LED_SER = 0x17,/* 16 bit r/w LED Stream Select S. LED */ 927 PHY_MARV_FE_VCT_TX = 0x1a,/* 16 bit r/w VCT Reg. for TXP/N Pins */ 928 PHY_MARV_FE_VCT_RX = 0x1b,/* 16 bit r/o VCT Reg. for RXP/N Pins */ 929 PHY_MARV_FE_SPEC_2 = 0x1c,/* 16 bit r/w Specific Control Reg. 2 */ 930}; 931 932enum { 933 PHY_CT_RESET = 1<<15, /* Bit 15: (sc) clear all PHY related regs */ 934 PHY_CT_LOOP = 1<<14, /* Bit 14: enable Loopback over PHY */ 935 PHY_CT_SPS_LSB = 1<<13, /* Bit 13: Speed select, lower bit */ 936 PHY_CT_ANE = 1<<12, /* Bit 12: Auto-Negotiation Enabled */ 937 PHY_CT_PDOWN = 1<<11, /* Bit 11: Power Down Mode */ 938 PHY_CT_ISOL = 1<<10, /* Bit 10: Isolate Mode */ 939 PHY_CT_RE_CFG = 1<<9, /* Bit 9: (sc) Restart Auto-Negotiation */ 940 PHY_CT_DUP_MD = 1<<8, /* Bit 8: Duplex Mode */ 941 PHY_CT_COL_TST = 1<<7, /* Bit 7: Collision Test enabled */ 942 PHY_CT_SPS_MSB = 1<<6, /* Bit 6: Speed select, upper bit */ 943}; 944 945enum { 946 PHY_CT_SP1000 = PHY_CT_SPS_MSB, /* enable speed of 1000 Mbps */ 947 PHY_CT_SP100 = PHY_CT_SPS_LSB, /* enable speed of 100 Mbps */ 948 PHY_CT_SP10 = 0, /* enable speed of 10 Mbps */ 949}; 950 951enum { 952 PHY_ST_EXT_ST = 1<<8, /* Bit 8: Extended Status Present */ 953 954 PHY_ST_PRE_SUP = 1<<6, /* Bit 6: Preamble Suppression */ 955 PHY_ST_AN_OVER = 1<<5, /* Bit 5: Auto-Negotiation Over */ 956 PHY_ST_REM_FLT = 1<<4, /* Bit 4: Remote Fault Condition Occured */ 957 PHY_ST_AN_CAP = 1<<3, /* Bit 3: Auto-Negotiation Capability */ 958 PHY_ST_LSYNC = 1<<2, /* Bit 2: Link Synchronized */ 959 PHY_ST_JAB_DET = 1<<1, /* Bit 1: Jabber Detected */ 960 PHY_ST_EXT_REG = 1<<0, /* Bit 0: Extended Register available */ 961}; 962 963enum { 964 PHY_I1_OUI_MSK = 0x3f<<10, /* Bit 15..10: Organization Unique ID */ 965 PHY_I1_MOD_NUM = 0x3f<<4, /* Bit 9.. 4: Model Number */ 966 PHY_I1_REV_MSK = 0xf, /* Bit 3.. 0: Revision Number */ 967}; 968 969/* different Marvell PHY Ids */ 970enum { 971 PHY_MARV_ID0_VAL= 0x0141, /* Marvell Unique Identifier */ 972 973 PHY_BCOM_ID1_A1 = 0x6041, 974 PHY_BCOM_ID1_B2 = 0x6043, 975 PHY_BCOM_ID1_C0 = 0x6044, 976 PHY_BCOM_ID1_C5 = 0x6047, 977 978 PHY_MARV_ID1_B0 = 0x0C23, /* Yukon (PHY 88E1011) */ 979 PHY_MARV_ID1_B2 = 0x0C25, /* Yukon-Plus (PHY 88E1011) */ 980 PHY_MARV_ID1_C2 = 0x0CC2, /* Yukon-EC (PHY 88E1111) */ 981 PHY_MARV_ID1_Y2 = 0x0C91, /* Yukon-2 (PHY 88E1112) */ 982 PHY_MARV_ID1_FE = 0x0C83, /* Yukon-FE (PHY 88E3082 Rev.A1) */ 983 PHY_MARV_ID1_ECU= 0x0CB0, /* Yukon-ECU (PHY 88E1149 Rev.B2?) */ 984}; 985 986/* Advertisement register bits */ 987enum { 988 PHY_AN_NXT_PG = 1<<15, /* Bit 15: Request Next Page */ 989 PHY_AN_ACK = 1<<14, /* Bit 14: (ro) Acknowledge Received */ 990 PHY_AN_RF = 1<<13, /* Bit 13: Remote Fault Bits */ 991 992 PHY_AN_PAUSE_ASYM = 1<<11,/* Bit 11: Try for asymmetric */ 993 PHY_AN_PAUSE_CAP = 1<<10, /* Bit 10: Try for pause */ 994 PHY_AN_100BASE4 = 1<<9, /* Bit 9: Try for 100mbps 4k packets */ 995 PHY_AN_100FULL = 1<<8, /* Bit 8: Try for 100mbps full-duplex */ 996 PHY_AN_100HALF = 1<<7, /* Bit 7: Try for 100mbps half-duplex */ 997 PHY_AN_10FULL = 1<<6, /* Bit 6: Try for 10mbps full-duplex */ 998 PHY_AN_10HALF = 1<<5, /* Bit 5: Try for 10mbps half-duplex */ 999 PHY_AN_CSMA = 1<<0, /* Bit 0: Only selector supported */ 1000 PHY_AN_SEL = 0x1f, /* Bit 4..0: Selector Field, 00001=Ethernet*/ 1001 PHY_AN_FULL = PHY_AN_100FULL | PHY_AN_10FULL | PHY_AN_CSMA, 1002 PHY_AN_ALL = PHY_AN_10HALF | PHY_AN_10FULL | 1003 PHY_AN_100HALF | PHY_AN_100FULL, 1004}; 1005 1006/***** PHY_BCOM_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/ 1007/***** PHY_MARV_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/ 1008enum { 1009 PHY_B_1000S_MSF = 1<<15, /* Bit 15: Master/Slave Fault */ 1010 PHY_B_1000S_MSR = 1<<14, /* Bit 14: Master/Slave Result */ 1011 PHY_B_1000S_LRS = 1<<13, /* Bit 13: Local Receiver Status */ 1012 PHY_B_1000S_RRS = 1<<12, /* Bit 12: Remote Receiver Status */ 1013 PHY_B_1000S_LP_FD = 1<<11, /* Bit 11: Link Partner can FD */ 1014 PHY_B_1000S_LP_HD = 1<<10, /* Bit 10: Link Partner can HD */ 1015 /* Bit 9..8: reserved */ 1016 PHY_B_1000S_IEC = 0xff, /* Bit 7..0: Idle Error Count */ 1017}; 1018 1019/** Marvell-Specific */ 1020enum { 1021 PHY_M_AN_NXT_PG = 1<<15, /* Request Next Page */ 1022 PHY_M_AN_ACK = 1<<14, /* (ro) Acknowledge Received */ 1023 PHY_M_AN_RF = 1<<13, /* Remote Fault */ 1024 1025 PHY_M_AN_ASP = 1<<11, /* Asymmetric Pause */ 1026 PHY_M_AN_PC = 1<<10, /* MAC Pause implemented */ 1027 PHY_M_AN_100_T4 = 1<<9, /* Not cap. 100Base-T4 (always 0) */ 1028 PHY_M_AN_100_FD = 1<<8, /* Advertise 100Base-TX Full Duplex */ 1029 PHY_M_AN_100_HD = 1<<7, /* Advertise 100Base-TX Half Duplex */ 1030 PHY_M_AN_10_FD = 1<<6, /* Advertise 10Base-TX Full Duplex */ 1031 PHY_M_AN_10_HD = 1<<5, /* Advertise 10Base-TX Half Duplex */ 1032 PHY_M_AN_SEL_MSK =0x1f<<4, /* Bit 4.. 0: Selector Field Mask */ 1033}; 1034 1035/* special defines for FIBER (88E1011S only) */ 1036enum { 1037 PHY_M_AN_ASP_X = 1<<8, /* Asymmetric Pause */ 1038 PHY_M_AN_PC_X = 1<<7, /* MAC Pause implemented */ 1039 PHY_M_AN_1000X_AHD = 1<<6, /* Advertise 10000Base-X Half Duplex */ 1040 PHY_M_AN_1000X_AFD = 1<<5, /* Advertise 10000Base-X Full Duplex */ 1041}; 1042 1043/* Pause Bits (PHY_M_AN_ASP_X and PHY_M_AN_PC_X) encoding */ 1044enum { 1045 PHY_M_P_NO_PAUSE_X = 0<<7,/* Bit 8.. 7: no Pause Mode */ 1046 PHY_M_P_SYM_MD_X = 1<<7, /* Bit 8.. 7: symmetric Pause Mode */ 1047 PHY_M_P_ASYM_MD_X = 2<<7,/* Bit 8.. 7: asymmetric Pause Mode */ 1048 PHY_M_P_BOTH_MD_X = 3<<7,/* Bit 8.. 7: both Pause Mode */ 1049}; 1050 1051/***** PHY_MARV_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/ 1052enum { 1053 PHY_M_1000C_TEST = 7<<13,/* Bit 15..13: Test Modes */ 1054 PHY_M_1000C_MSE = 1<<12, /* Manual Master/Slave Enable */ 1055 PHY_M_1000C_MSC = 1<<11, /* M/S Configuration (1=Master) */ 1056 PHY_M_1000C_MPD = 1<<10, /* Multi-Port Device */ 1057 PHY_M_1000C_AFD = 1<<9, /* Advertise Full Duplex */ 1058 PHY_M_1000C_AHD = 1<<8, /* Advertise Half Duplex */ 1059}; 1060 1061/***** PHY_MARV_PHY_CTRL 16 bit r/w PHY Specific Ctrl Reg *****/ 1062enum { 1063 PHY_M_PC_TX_FFD_MSK = 3<<14,/* Bit 15..14: Tx FIFO Depth Mask */ 1064 PHY_M_PC_RX_FFD_MSK = 3<<12,/* Bit 13..12: Rx FIFO Depth Mask */ 1065 PHY_M_PC_ASS_CRS_TX = 1<<11, /* Assert CRS on Transmit */ 1066 PHY_M_PC_FL_GOOD = 1<<10, /* Force Link Good */ 1067 PHY_M_PC_EN_DET_MSK = 3<<8,/* Bit 9.. 8: Energy Detect Mask */ 1068 PHY_M_PC_ENA_EXT_D = 1<<7, /* Enable Ext. Distance (10BT) */ 1069 PHY_M_PC_MDIX_MSK = 3<<5,/* Bit 6.. 5: MDI/MDIX Config. Mask */ 1070 PHY_M_PC_DIS_125CLK = 1<<4, /* Disable 125 CLK */ 1071 PHY_M_PC_MAC_POW_UP = 1<<3, /* MAC Power up */ 1072 PHY_M_PC_SQE_T_ENA = 1<<2, /* SQE Test Enabled */ 1073 PHY_M_PC_POL_R_DIS = 1<<1, /* Polarity Reversal Disabled */ 1074 PHY_M_PC_DIS_JABBER = 1<<0, /* Disable Jabber */ 1075}; 1076 1077enum { 1078 PHY_M_PC_EN_DET = 2<<8, /* Energy Detect (Mode 1) */ 1079 PHY_M_PC_EN_DET_PLUS = 3<<8, /* Energy Detect Plus (Mode 2) */ 1080}; 1081 1082#define PHY_M_PC_MDI_XMODE(x) (((u16)(x)<<5) & PHY_M_PC_MDIX_MSK) 1083 1084enum { 1085 PHY_M_PC_MAN_MDI = 0, /* 00 = Manual MDI configuration */ 1086 PHY_M_PC_MAN_MDIX = 1, /* 01 = Manual MDIX configuration */ 1087 PHY_M_PC_ENA_AUTO = 3, /* 11 = Enable Automatic Crossover */ 1088}; 1089 1090/* for 10/100 Fast Ethernet PHY (88E3082 only) */ 1091enum { 1092 PHY_M_PC_ENA_DTE_DT = 1<<15, /* Enable Data Terminal Equ. (DTE) Detect */ 1093 PHY_M_PC_ENA_ENE_DT = 1<<14, /* Enable Energy Detect (sense & pulse) */ 1094 PHY_M_PC_DIS_NLP_CK = 1<<13, /* Disable Normal Link Puls (NLP) Check */ 1095 PHY_M_PC_ENA_LIP_NP = 1<<12, /* Enable Link Partner Next Page Reg. */ 1096 PHY_M_PC_DIS_NLP_GN = 1<<11, /* Disable Normal Link Puls Generation */ 1097 1098 PHY_M_PC_DIS_SCRAMB = 1<<9, /* Disable Scrambler */ 1099 PHY_M_PC_DIS_FEFI = 1<<8, /* Disable Far End Fault Indic. (FEFI) */ 1100 1101 PHY_M_PC_SH_TP_SEL = 1<<6, /* Shielded Twisted Pair Select */ 1102 PHY_M_PC_RX_FD_MSK = 3<<2,/* Bit 3.. 2: Rx FIFO Depth Mask */ 1103}; 1104 1105/***** PHY_MARV_PHY_STAT 16 bit r/o PHY Specific Status Reg *****/ 1106enum { 1107 PHY_M_PS_SPEED_MSK = 3<<14, /* Bit 15..14: Speed Mask */ 1108 PHY_M_PS_SPEED_1000 = 1<<15, /* 10 = 1000 Mbps */ 1109 PHY_M_PS_SPEED_100 = 1<<14, /* 01 = 100 Mbps */ 1110 PHY_M_PS_SPEED_10 = 0, /* 00 = 10 Mbps */ 1111 PHY_M_PS_FULL_DUP = 1<<13, /* Full Duplex */ 1112 PHY_M_PS_PAGE_REC = 1<<12, /* Page Received */ 1113 PHY_M_PS_SPDUP_RES = 1<<11, /* Speed & Duplex Resolved */ 1114 PHY_M_PS_LINK_UP = 1<<10, /* Link Up */ 1115 PHY_M_PS_CABLE_MSK = 7<<7, /* Bit 9.. 7: Cable Length Mask */ 1116 PHY_M_PS_MDI_X_STAT = 1<<6, /* MDI Crossover Stat (1=MDIX) */ 1117 PHY_M_PS_DOWNS_STAT = 1<<5, /* Downshift Status (1=downsh.) */ 1118 PHY_M_PS_ENDET_STAT = 1<<4, /* Energy Detect Status (1=act) */ 1119 PHY_M_PS_TX_P_EN = 1<<3, /* Tx Pause Enabled */ 1120 PHY_M_PS_RX_P_EN = 1<<2, /* Rx Pause Enabled */ 1121 PHY_M_PS_POL_REV = 1<<1, /* Polarity Reversed */ 1122 PHY_M_PS_JABBER = 1<<0, /* Jabber */ 1123}; 1124 1125#define PHY_M_PS_PAUSE_MSK (PHY_M_PS_TX_P_EN | PHY_M_PS_RX_P_EN) 1126 1127/* for 10/100 Fast Ethernet PHY (88E3082 only) */ 1128enum { 1129 PHY_M_PS_DTE_DETECT = 1<<15, /* Data Terminal Equipment (DTE) Detected */ 1130 PHY_M_PS_RES_SPEED = 1<<14, /* Resolved Speed (1=100 Mbps, 0=10 Mbps */ 1131}; 1132 1133enum { 1134 PHY_M_IS_AN_ERROR = 1<<15, /* Auto-Negotiation Error */ 1135 PHY_M_IS_LSP_CHANGE = 1<<14, /* Link Speed Changed */ 1136 PHY_M_IS_DUP_CHANGE = 1<<13, /* Duplex Mode Changed */ 1137 PHY_M_IS_AN_PR = 1<<12, /* Page Received */ 1138 PHY_M_IS_AN_COMPL = 1<<11, /* Auto-Negotiation Completed */ 1139 PHY_M_IS_LST_CHANGE = 1<<10, /* Link Status Changed */ 1140 PHY_M_IS_SYMB_ERROR = 1<<9, /* Symbol Error */ 1141 PHY_M_IS_FALSE_CARR = 1<<8, /* False Carrier */ 1142 PHY_M_IS_FIFO_ERROR = 1<<7, /* FIFO Overflow/Underrun Error */ 1143 PHY_M_IS_MDI_CHANGE = 1<<6, /* MDI Crossover Changed */ 1144 PHY_M_IS_DOWNSH_DET = 1<<5, /* Downshift Detected */ 1145 PHY_M_IS_END_CHANGE = 1<<4, /* Energy Detect Changed */ 1146 1147 PHY_M_IS_DTE_CHANGE = 1<<2, /* DTE Power Det. Status Changed */ 1148 PHY_M_IS_POL_CHANGE = 1<<1, /* Polarity Changed */ 1149 PHY_M_IS_JABBER = 1<<0, /* Jabber */ 1150 1151 PHY_M_DEF_MSK = PHY_M_IS_LSP_CHANGE | PHY_M_IS_LST_CHANGE 1152 | PHY_M_IS_DUP_CHANGE, 1153 PHY_M_AN_MSK = PHY_M_IS_AN_ERROR | PHY_M_IS_AN_COMPL, 1154}; 1155 1156 1157/***** PHY_MARV_EXT_CTRL 16 bit r/w Ext. PHY Specific Ctrl *****/ 1158enum { 1159 PHY_M_EC_ENA_BC_EXT = 1<<15, /* Enable Block Carr. Ext. (88E1111 only) */ 1160 PHY_M_EC_ENA_LIN_LB = 1<<14, /* Enable Line Loopback (88E1111 only) */ 1161 1162 PHY_M_EC_DIS_LINK_P = 1<<12, /* Disable Link Pulses (88E1111 only) */ 1163 PHY_M_EC_M_DSC_MSK = 3<<10, /* Bit 11..10: Master Downshift Counter */ 1164 /* (88E1011 only) */ 1165 PHY_M_EC_S_DSC_MSK = 3<<8,/* Bit 9.. 8: Slave Downshift Counter */ 1166 /* (88E1011 only) */ 1167 PHY_M_EC_M_DSC_MSK2 = 7<<9,/* Bit 11.. 9: Master Downshift Counter */ 1168 /* (88E1111 only) */ 1169 PHY_M_EC_DOWN_S_ENA = 1<<8, /* Downshift Enable (88E1111 only) */ 1170 /* !!! Errata in spec. (1 = disable) */ 1171 PHY_M_EC_RX_TIM_CT = 1<<7, /* RGMII Rx Timing Control*/ 1172 PHY_M_EC_MAC_S_MSK = 7<<4,/* Bit 6.. 4: Def. MAC interface speed */ 1173 PHY_M_EC_FIB_AN_ENA = 1<<3, /* Fiber Auto-Neg. Enable (88E1011S only) */ 1174 PHY_M_EC_DTE_D_ENA = 1<<2, /* DTE Detect Enable (88E1111 only) */ 1175 PHY_M_EC_TX_TIM_CT = 1<<1, /* RGMII Tx Timing Control */ 1176 PHY_M_EC_TRANS_DIS = 1<<0, /* Transmitter Disable (88E1111 only) */}; 1177 1178#define PHY_M_EC_M_DSC(x) ((u16)(x)<<10 & PHY_M_EC_M_DSC_MSK) 1179 /* 00=1x; 01=2x; 10=3x; 11=4x */ 1180#define PHY_M_EC_S_DSC(x) ((u16)(x)<<8 & PHY_M_EC_S_DSC_MSK) 1181 /* 00=dis; 01=1x; 10=2x; 11=3x */ 1182#define PHY_M_EC_DSC_2(x) ((u16)(x)<<9 & PHY_M_EC_M_DSC_MSK2) 1183 /* 000=1x; 001=2x; 010=3x; 011=4x */ 1184#define PHY_M_EC_MAC_S(x) ((u16)(x)<<4 & PHY_M_EC_MAC_S_MSK) 1185 /* 01X=0; 110=2.5; 111=25 (MHz) */ 1186 1187/* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */ 1188enum { 1189 PHY_M_PC_DIS_LINK_Pa = 1<<15,/* Disable Link Pulses */ 1190 PHY_M_PC_DSC_MSK = 7<<12,/* Bit 14..12: Downshift Counter */ 1191 PHY_M_PC_DOWN_S_ENA = 1<<11,/* Downshift Enable */ 1192}; 1193/* !!! Errata in spec. (1 = disable) */ 1194 1195#define PHY_M_PC_DSC(x) (((u16)(x)<<12) & PHY_M_PC_DSC_MSK) 1196 /* 100=5x; 101=6x; 110=7x; 111=8x */ 1197enum { 1198 MAC_TX_CLK_0_MHZ = 2, 1199 MAC_TX_CLK_2_5_MHZ = 6, 1200 MAC_TX_CLK_25_MHZ = 7, 1201}; 1202 1203/***** PHY_MARV_LED_CTRL 16 bit r/w LED Control Reg *****/ 1204enum { 1205 PHY_M_LEDC_DIS_LED = 1<<15, /* Disable LED */ 1206 PHY_M_LEDC_PULS_MSK = 7<<12,/* Bit 14..12: Pulse Stretch Mask */ 1207 PHY_M_LEDC_F_INT = 1<<11, /* Force Interrupt */ 1208 PHY_M_LEDC_BL_R_MSK = 7<<8,/* Bit 10.. 8: Blink Rate Mask */ 1209 PHY_M_LEDC_DP_C_LSB = 1<<7, /* Duplex Control (LSB, 88E1111 only) */ 1210 PHY_M_LEDC_TX_C_LSB = 1<<6, /* Tx Control (LSB, 88E1111 only) */ 1211 PHY_M_LEDC_LK_C_MSK = 7<<3,/* Bit 5.. 3: Link Control Mask */ 1212 /* (88E1111 only) */ 1213}; 1214 1215enum { 1216 PHY_M_LEDC_LINK_MSK = 3<<3,/* Bit 4.. 3: Link Control Mask */ 1217 /* (88E1011 only) */ 1218 PHY_M_LEDC_DP_CTRL = 1<<2, /* Duplex Control */ 1219 PHY_M_LEDC_DP_C_MSB = 1<<2, /* Duplex Control (MSB, 88E1111 only) */ 1220 PHY_M_LEDC_RX_CTRL = 1<<1, /* Rx Activity / Link */ 1221 PHY_M_LEDC_TX_CTRL = 1<<0, /* Tx Activity / Link */ 1222 PHY_M_LEDC_TX_C_MSB = 1<<0, /* Tx Control (MSB, 88E1111 only) */ 1223}; 1224 1225#define PHY_M_LED_PULS_DUR(x) (((u16)(x)<<12) & PHY_M_LEDC_PULS_MSK) 1226 1227/***** PHY_MARV_PHY_STAT (page 3)16 bit r/w Polarity Control Reg. *****/ 1228enum { 1229 PHY_M_POLC_LS1M_MSK = 0xf<<12, /* Bit 15..12: LOS,STAT1 Mix % Mask */ 1230 PHY_M_POLC_IS0M_MSK = 0xf<<8, /* Bit 11.. 8: INIT,STAT0 Mix % Mask */ 1231 PHY_M_POLC_LOS_MSK = 0x3<<6, /* Bit 7.. 6: LOS Pol. Ctrl. Mask */ 1232 PHY_M_POLC_INIT_MSK = 0x3<<4, /* Bit 5.. 4: INIT Pol. Ctrl. Mask */ 1233 PHY_M_POLC_STA1_MSK = 0x3<<2, /* Bit 3.. 2: STAT1 Pol. Ctrl. Mask */ 1234 PHY_M_POLC_STA0_MSK = 0x3, /* Bit 1.. 0: STAT0 Pol. Ctrl. Mask */ 1235}; 1236 1237#define PHY_M_POLC_LS1_P_MIX(x) (((x)<<12) & PHY_M_POLC_LS1M_MSK) 1238#define PHY_M_POLC_IS0_P_MIX(x) (((x)<<8) & PHY_M_POLC_IS0M_MSK) 1239#define PHY_M_POLC_LOS_CTRL(x) (((x)<<6) & PHY_M_POLC_LOS_MSK) 1240#define PHY_M_POLC_INIT_CTRL(x) (((x)<<4) & PHY_M_POLC_INIT_MSK) 1241#define PHY_M_POLC_STA1_CTRL(x) (((x)<<2) & PHY_M_POLC_STA1_MSK) 1242#define PHY_M_POLC_STA0_CTRL(x) (((x)<<0) & PHY_M_POLC_STA0_MSK) 1243 1244enum { 1245 PULS_NO_STR = 0,/* no pulse stretching */ 1246 PULS_21MS = 1,/* 21 ms to 42 ms */ 1247 PULS_42MS = 2,/* 42 ms to 84 ms */ 1248 PULS_84MS = 3,/* 84 ms to 170 ms */ 1249 PULS_170MS = 4,/* 170 ms to 340 ms */ 1250 PULS_340MS = 5,/* 340 ms to 670 ms */ 1251 PULS_670MS = 6,/* 670 ms to 1.3 s */ 1252 PULS_1300MS = 7,/* 1.3 s to 2.7 s */ 1253}; 1254 1255#define PHY_M_LED_BLINK_RT(x) (((u16)(x)<<8) & PHY_M_LEDC_BL_R_MSK) 1256 1257enum { 1258 BLINK_42MS = 0,/* 42 ms */ 1259 BLINK_84MS = 1,/* 84 ms */ 1260 BLINK_170MS = 2,/* 170 ms */ 1261 BLINK_340MS = 3,/* 340 ms */ 1262 BLINK_670MS = 4,/* 670 ms */ 1263}; 1264 1265/**** PHY_MARV_LED_OVER 16 bit r/w LED control */ 1266enum { 1267 PHY_M_LED_MO_DUP = 3<<10,/* Bit 11..10: Duplex */ 1268 PHY_M_LED_MO_10 = 3<<8, /* Bit 9.. 8: Link 10 */ 1269 PHY_M_LED_MO_100 = 3<<6, /* Bit 7.. 6: Link 100 */ 1270 PHY_M_LED_MO_1000 = 3<<4, /* Bit 5.. 4: Link 1000 */ 1271 PHY_M_LED_MO_RX = 3<<2, /* Bit 3.. 2: Rx */ 1272 PHY_M_LED_MO_TX = 3<<0, /* Bit 1.. 0: Tx */ 1273 1274 PHY_M_LED_ALL = PHY_M_LED_MO_DUP | PHY_M_LED_MO_10 1275 | PHY_M_LED_MO_100 | PHY_M_LED_MO_1000 1276 | PHY_M_LED_MO_RX, 1277}; 1278 1279/***** PHY_MARV_EXT_CTRL_2 16 bit r/w Ext. PHY Specific Ctrl 2 *****/ 1280enum { 1281 PHY_M_EC2_FI_IMPED = 1<<6, /* Fiber Input Impedance */ 1282 PHY_M_EC2_FO_IMPED = 1<<5, /* Fiber Output Impedance */ 1283 PHY_M_EC2_FO_M_CLK = 1<<4, /* Fiber Mode Clock Enable */ 1284 PHY_M_EC2_FO_BOOST = 1<<3, /* Fiber Output Boost */ 1285 PHY_M_EC2_FO_AM_MSK = 7,/* Bit 2.. 0: Fiber Output Amplitude */ 1286}; 1287 1288/***** PHY_MARV_EXT_P_STAT 16 bit r/w Ext. PHY Specific Status *****/ 1289enum { 1290 PHY_M_FC_AUTO_SEL = 1<<15, /* Fiber/Copper Auto Sel. Dis. */ 1291 PHY_M_FC_AN_REG_ACC = 1<<14, /* Fiber/Copper AN Reg. Access */ 1292 PHY_M_FC_RESOLUTION = 1<<13, /* Fiber/Copper Resolution */ 1293 PHY_M_SER_IF_AN_BP = 1<<12, /* Ser. IF AN Bypass Enable */ 1294 PHY_M_SER_IF_BP_ST = 1<<11, /* Ser. IF AN Bypass Status */ 1295 PHY_M_IRQ_POLARITY = 1<<10, /* IRQ polarity */ 1296 PHY_M_DIS_AUT_MED = 1<<9, /* Disable Aut. Medium Reg. Selection */ 1297 /* (88E1111 only) */ 1298 1299 PHY_M_UNDOC1 = 1<<7, /* undocumented bit !! */ 1300 PHY_M_DTE_POW_STAT = 1<<4, /* DTE Power Status (88E1111 only) */ 1301 PHY_M_MODE_MASK = 0xf, /* Bit 3.. 0: copy of HWCFG MODE[3:0] */ 1302}; 1303 1304/* for 10/100 Fast Ethernet PHY (88E3082 only) */ 1305/***** PHY_MARV_FE_LED_PAR 16 bit r/w LED Parallel Select Reg. *****/ 1306 /* Bit 15..12: reserved (used internally) */ 1307enum { 1308 PHY_M_FELP_LED2_MSK = 0xf<<8, /* Bit 11.. 8: LED2 Mask (LINK) */ 1309 PHY_M_FELP_LED1_MSK = 0xf<<4, /* Bit 7.. 4: LED1 Mask (ACT) */ 1310 PHY_M_FELP_LED0_MSK = 0xf, /* Bit 3.. 0: LED0 Mask (SPEED) */ 1311}; 1312 1313#define PHY_M_FELP_LED2_CTRL(x) (((u16)(x)<<8) & PHY_M_FELP_LED2_MSK) 1314#define PHY_M_FELP_LED1_CTRL(x) (((u16)(x)<<4) & PHY_M_FELP_LED1_MSK) 1315#define PHY_M_FELP_LED0_CTRL(x) (((u16)(x)<<0) & PHY_M_FELP_LED0_MSK) 1316 1317enum { 1318 LED_PAR_CTRL_COLX = 0x00, 1319 LED_PAR_CTRL_ERROR = 0x01, 1320 LED_PAR_CTRL_DUPLEX = 0x02, 1321 LED_PAR_CTRL_DP_COL = 0x03, 1322 LED_PAR_CTRL_SPEED = 0x04, 1323 LED_PAR_CTRL_LINK = 0x05, 1324 LED_PAR_CTRL_TX = 0x06, 1325 LED_PAR_CTRL_RX = 0x07, 1326 LED_PAR_CTRL_ACT = 0x08, 1327 LED_PAR_CTRL_LNK_RX = 0x09, 1328 LED_PAR_CTRL_LNK_AC = 0x0a, 1329 LED_PAR_CTRL_ACT_BL = 0x0b, 1330 LED_PAR_CTRL_TX_BL = 0x0c, 1331 LED_PAR_CTRL_RX_BL = 0x0d, 1332 LED_PAR_CTRL_COL_BL = 0x0e, 1333 LED_PAR_CTRL_INACT = 0x0f 1334}; 1335 1336/*****,PHY_MARV_FE_SPEC_2 16 bit r/w Specific Control Reg. 2 *****/ 1337enum { 1338 PHY_M_FESC_DIS_WAIT = 1<<2, /* Disable TDR Waiting Period */ 1339 PHY_M_FESC_ENA_MCLK = 1<<1, /* Enable MAC Rx Clock in sleep mode */ 1340 PHY_M_FESC_SEL_CL_A = 1<<0, /* Select Class A driver (100B-TX) */ 1341}; 1342 1343/* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */ 1344/***** PHY_MARV_PHY_CTRL (page 1) 16 bit r/w Fiber Specific Ctrl *****/ 1345enum { 1346 PHY_M_FIB_FORCE_LNK = 1<<10,/* Force Link Good */ 1347 PHY_M_FIB_SIGD_POL = 1<<9, /* SIGDET Polarity */ 1348 PHY_M_FIB_TX_DIS = 1<<3, /* Transmitter Disable */ 1349}; 1350 1351/* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */ 1352/***** PHY_MARV_PHY_CTRL (page 2) 16 bit r/w MAC Specific Ctrl *****/ 1353enum { 1354 PHY_M_MAC_MD_MSK = 7<<7, /* Bit 9.. 7: Mode Select Mask */ 1355 PHY_M_MAC_MD_AUTO = 3,/* Auto Copper/1000Base-X */ 1356 PHY_M_MAC_MD_COPPER = 5,/* Copper only */ 1357 PHY_M_MAC_MD_1000BX = 7,/* 1000Base-X only */ 1358}; 1359#define PHY_M_MAC_MODE_SEL(x) (((x)<<7) & PHY_M_MAC_MD_MSK) 1360 1361/***** PHY_MARV_PHY_CTRL (page 3) 16 bit r/w LED Control Reg. *****/ 1362enum { 1363 PHY_M_LEDC_LOS_MSK = 0xf<<12,/* Bit 15..12: LOS LED Ctrl. Mask */ 1364 PHY_M_LEDC_INIT_MSK = 0xf<<8, /* Bit 11.. 8: INIT LED Ctrl. Mask */ 1365 PHY_M_LEDC_STA1_MSK = 0xf<<4,/* Bit 7.. 4: STAT1 LED Ctrl. Mask */ 1366 PHY_M_LEDC_STA0_MSK = 0xf, /* Bit 3.. 0: STAT0 LED Ctrl. Mask */ 1367}; 1368 1369#define PHY_M_LEDC_LOS_CTRL(x) (((x)<<12) & PHY_M_LEDC_LOS_MSK) 1370#define PHY_M_LEDC_INIT_CTRL(x) (((x)<<8) & PHY_M_LEDC_INIT_MSK) 1371#define PHY_M_LEDC_STA1_CTRL(x) (((x)<<4) & PHY_M_LEDC_STA1_MSK) 1372#define PHY_M_LEDC_STA0_CTRL(x) (((x)<<0) & PHY_M_LEDC_STA0_MSK) 1373 1374/* GMAC registers */ 1375/* Port Registers */ 1376enum { 1377 GM_GP_STAT = 0x0000, /* 16 bit r/o General Purpose Status */ 1378 GM_GP_CTRL = 0x0004, /* 16 bit r/w General Purpose Control */ 1379 GM_TX_CTRL = 0x0008, /* 16 bit r/w Transmit Control Reg. */ 1380 GM_RX_CTRL = 0x000c, /* 16 bit r/w Receive Control Reg. */ 1381 GM_TX_FLOW_CTRL = 0x0010, /* 16 bit r/w Transmit Flow-Control */ 1382 GM_TX_PARAM = 0x0014, /* 16 bit r/w Transmit Parameter Reg. */ 1383 GM_SERIAL_MODE = 0x0018, /* 16 bit r/w Serial Mode Register */ 1384/* Source Address Registers */ 1385 GM_SRC_ADDR_1L = 0x001c, /* 16 bit r/w Source Address 1 (low) */ 1386 GM_SRC_ADDR_1M = 0x0020, /* 16 bit r/w Source Address 1 (middle) */ 1387 GM_SRC_ADDR_1H = 0x0024, /* 16 bit r/w Source Address 1 (high) */ 1388 GM_SRC_ADDR_2L = 0x0028, /* 16 bit r/w Source Address 2 (low) */ 1389 GM_SRC_ADDR_2M = 0x002c, /* 16 bit r/w Source Address 2 (middle) */ 1390 GM_SRC_ADDR_2H = 0x0030, /* 16 bit r/w Source Address 2 (high) */ 1391 1392/* Multicast Address Hash Registers */ 1393 GM_MC_ADDR_H1 = 0x0034, /* 16 bit r/w Multicast Address Hash 1 */ 1394 GM_MC_ADDR_H2 = 0x0038, /* 16 bit r/w Multicast Address Hash 2 */ 1395 GM_MC_ADDR_H3 = 0x003c, /* 16 bit r/w Multicast Address Hash 3 */ 1396 GM_MC_ADDR_H4 = 0x0040, /* 16 bit r/w Multicast Address Hash 4 */ 1397 1398/* Interrupt Source Registers */ 1399 GM_TX_IRQ_SRC = 0x0044, /* 16 bit r/o Tx Overflow IRQ Source */ 1400 GM_RX_IRQ_SRC = 0x0048, /* 16 bit r/o Rx Overflow IRQ Source */ 1401 GM_TR_IRQ_SRC = 0x004c, /* 16 bit r/o Tx/Rx Over. IRQ Source */ 1402 1403/* Interrupt Mask Registers */ 1404 GM_TX_IRQ_MSK = 0x0050, /* 16 bit r/w Tx Overflow IRQ Mask */ 1405 GM_RX_IRQ_MSK = 0x0054, /* 16 bit r/w Rx Overflow IRQ Mask */ 1406 GM_TR_IRQ_MSK = 0x0058, /* 16 bit r/w Tx/Rx Over. IRQ Mask */ 1407 1408/* Serial Management Interface (SMI) Registers */ 1409 GM_SMI_CTRL = 0x0080, /* 16 bit r/w SMI Control Register */ 1410 GM_SMI_DATA = 0x0084, /* 16 bit r/w SMI Data Register */ 1411 GM_PHY_ADDR = 0x0088, /* 16 bit r/w GPHY Address Register */ 1412/* MIB Counters */ 1413 GM_MIB_CNT_BASE = 0x0100, /* Base Address of MIB Counters */ 1414 GM_MIB_CNT_END = 0x025C, /* Last MIB counter */ 1415}; 1416 1417 1418/* 1419 * MIB Counters base address definitions (low word) - 1420 * use offset 4 for access to high word (32 bit r/o) 1421 */ 1422enum { 1423 GM_RXF_UC_OK = GM_MIB_CNT_BASE + 0, /* Unicast Frames Received OK */ 1424 GM_RXF_BC_OK = GM_MIB_CNT_BASE + 8, /* Broadcast Frames Received OK */ 1425 GM_RXF_MPAUSE = GM_MIB_CNT_BASE + 16, /* Pause MAC Ctrl Frames Received */ 1426 GM_RXF_MC_OK = GM_MIB_CNT_BASE + 24, /* Multicast Frames Received OK */ 1427 GM_RXF_FCS_ERR = GM_MIB_CNT_BASE + 32, /* Rx Frame Check Seq. Error */ 1428 1429 GM_RXO_OK_LO = GM_MIB_CNT_BASE + 48, /* Octets Received OK Low */ 1430 GM_RXO_OK_HI = GM_MIB_CNT_BASE + 56, /* Octets Received OK High */ 1431 GM_RXO_ERR_LO = GM_MIB_CNT_BASE + 64, /* Octets Received Invalid Low */ 1432 GM_RXO_ERR_HI = GM_MIB_CNT_BASE + 72, /* Octets Received Invalid High */ 1433 GM_RXF_SHT = GM_MIB_CNT_BASE + 80, /* Frames <64 Byte Received OK */ 1434 GM_RXE_FRAG = GM_MIB_CNT_BASE + 88, /* Frames <64 Byte Received with FCS Err */ 1435 GM_RXF_64B = GM_MIB_CNT_BASE + 96, /* 64 Byte Rx Frame */ 1436 GM_RXF_127B = GM_MIB_CNT_BASE + 104,/* 65-127 Byte Rx Frame */ 1437 GM_RXF_255B = GM_MIB_CNT_BASE + 112,/* 128-255 Byte Rx Frame */ 1438 GM_RXF_511B = GM_MIB_CNT_BASE + 120,/* 256-511 Byte Rx Frame */ 1439 GM_RXF_1023B = GM_MIB_CNT_BASE + 128,/* 512-1023 Byte Rx Frame */ 1440 GM_RXF_1518B = GM_MIB_CNT_BASE + 136,/* 1024-1518 Byte Rx Frame */ 1441 GM_RXF_MAX_SZ = GM_MIB_CNT_BASE + 144,/* 1519-MaxSize Byte Rx Frame */ 1442 GM_RXF_LNG_ERR = GM_MIB_CNT_BASE + 152,/* Rx Frame too Long Error */ 1443 GM_RXF_JAB_PKT = GM_MIB_CNT_BASE + 160,/* Rx Jabber Packet Frame */ 1444 1445 GM_RXE_FIFO_OV = GM_MIB_CNT_BASE + 176,/* Rx FIFO overflow Event */ 1446 GM_TXF_UC_OK = GM_MIB_CNT_BASE + 192,/* Unicast Frames Xmitted OK */ 1447 GM_TXF_BC_OK = GM_MIB_CNT_BASE + 200,/* Broadcast Frames Xmitted OK */ 1448 GM_TXF_MPAUSE = GM_MIB_CNT_BASE + 208,/* Pause MAC Ctrl Frames Xmitted */ 1449 GM_TXF_MC_OK = GM_MIB_CNT_BASE + 216,/* Multicast Frames Xmitted OK */ 1450 GM_TXO_OK_LO = GM_MIB_CNT_BASE + 224,/* Octets Transmitted OK Low */ 1451 GM_TXO_OK_HI = GM_MIB_CNT_BASE + 232,/* Octets Transmitted OK High */ 1452 GM_TXF_64B = GM_MIB_CNT_BASE + 240,/* 64 Byte Tx Frame */ 1453 GM_TXF_127B = GM_MIB_CNT_BASE + 248,/* 65-127 Byte Tx Frame */ 1454 GM_TXF_255B = GM_MIB_CNT_BASE + 256,/* 128-255 Byte Tx Frame */ 1455 GM_TXF_511B = GM_MIB_CNT_BASE + 264,/* 256-511 Byte Tx Frame */ 1456 GM_TXF_1023B = GM_MIB_CNT_BASE + 272,/* 512-1023 Byte Tx Frame */ 1457 GM_TXF_1518B = GM_MIB_CNT_BASE + 280,/* 1024-1518 Byte Tx Frame */ 1458 GM_TXF_MAX_SZ = GM_MIB_CNT_BASE + 288,/* 1519-MaxSize Byte Tx Frame */ 1459 1460 GM_TXF_COL = GM_MIB_CNT_BASE + 304,/* Tx Collision */ 1461 GM_TXF_LAT_COL = GM_MIB_CNT_BASE + 312,/* Tx Late Collision */ 1462 GM_TXF_ABO_COL = GM_MIB_CNT_BASE + 320,/* Tx aborted due to Exces. Col. */ 1463 GM_TXF_MUL_COL = GM_MIB_CNT_BASE + 328,/* Tx Multiple Collision */ 1464 GM_TXF_SNG_COL = GM_MIB_CNT_BASE + 336,/* Tx Single Collision */ 1465 GM_TXE_FIFO_UR = GM_MIB_CNT_BASE + 344,/* Tx FIFO Underrun Event */ 1466}; 1467 1468/* GMAC Bit Definitions */ 1469/* GM_GP_STAT 16 bit r/o General Purpose Status Register */ 1470enum { 1471 GM_GPSR_SPEED = 1<<15, /* Bit 15: Port Speed (1 = 100 Mbps) */ 1472 GM_GPSR_DUPLEX = 1<<14, /* Bit 14: Duplex Mode (1 = Full) */ 1473 GM_GPSR_FC_TX_DIS = 1<<13, /* Bit 13: Tx Flow-Control Mode Disabled */ 1474 GM_GPSR_LINK_UP = 1<<12, /* Bit 12: Link Up Status */ 1475 GM_GPSR_PAUSE = 1<<11, /* Bit 11: Pause State */ 1476 GM_GPSR_TX_ACTIVE = 1<<10, /* Bit 10: Tx in Progress */ 1477 GM_GPSR_EXC_COL = 1<<9, /* Bit 9: Excessive Collisions Occured */ 1478 GM_GPSR_LAT_COL = 1<<8, /* Bit 8: Late Collisions Occured */ 1479 1480 GM_GPSR_PHY_ST_CH = 1<<5, /* Bit 5: PHY Status Change */ 1481 GM_GPSR_GIG_SPEED = 1<<4, /* Bit 4: Gigabit Speed (1 = 1000 Mbps) */ 1482 GM_GPSR_PART_MODE = 1<<3, /* Bit 3: Partition mode */ 1483 GM_GPSR_FC_RX_DIS = 1<<2, /* Bit 2: Rx Flow-Control Mode Disabled */ 1484 GM_GPSR_PROM_EN = 1<<1, /* Bit 1: Promiscuous Mode Enabled */ 1485}; 1486 1487/* GM_GP_CTRL 16 bit r/w General Purpose Control Register */ 1488enum { 1489 GM_GPCR_PROM_ENA = 1<<14, /* Bit 14: Enable Promiscuous Mode */ 1490 GM_GPCR_FC_TX_DIS = 1<<13, /* Bit 13: Disable Tx Flow-Control Mode */ 1491 GM_GPCR_TX_ENA = 1<<12, /* Bit 12: Enable Transmit */ 1492 GM_GPCR_RX_ENA = 1<<11, /* Bit 11: Enable Receive */ 1493 GM_GPCR_BURST_ENA = 1<<10, /* Bit 10: Enable Burst Mode */ 1494 GM_GPCR_LOOP_ENA = 1<<9, /* Bit 9: Enable MAC Loopback Mode */ 1495 GM_GPCR_PART_ENA = 1<<8, /* Bit 8: Enable Partition Mode */ 1496 GM_GPCR_GIGS_ENA = 1<<7, /* Bit 7: Gigabit Speed (1000 Mbps) */ 1497 GM_GPCR_FL_PASS = 1<<6, /* Bit 6: Force Link Pass */ 1498 GM_GPCR_DUP_FULL = 1<<5, /* Bit 5: Full Duplex Mode */ 1499 GM_GPCR_FC_RX_DIS = 1<<4, /* Bit 4: Disable Rx Flow-Control Mode */ 1500 GM_GPCR_SPEED_100 = 1<<3, /* Bit 3: Port Speed 100 Mbps */ 1501 GM_GPCR_AU_DUP_DIS = 1<<2, /* Bit 2: Disable Auto-Update Duplex */ 1502 GM_GPCR_AU_FCT_DIS = 1<<1, /* Bit 1: Disable Auto-Update Flow-C. */ 1503 GM_GPCR_AU_SPD_DIS = 1<<0, /* Bit 0: Disable Auto-Update Speed */ 1504}; 1505 1506#define GM_GPCR_SPEED_1000 (GM_GPCR_GIGS_ENA | GM_GPCR_SPEED_100) 1507#define GM_GPCR_AU_ALL_DIS (GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS|GM_GPCR_AU_SPD_DIS) 1508 1509/* GM_TX_CTRL 16 bit r/w Transmit Control Register */ 1510enum { 1511 GM_TXCR_FORCE_JAM = 1<<15, /* Bit 15: Force Jam / Flow-Control */ 1512 GM_TXCR_CRC_DIS = 1<<14, /* Bit 14: Disable insertion of CRC */ 1513 GM_TXCR_PAD_DIS = 1<<13, /* Bit 13: Disable padding of packets */ 1514 GM_TXCR_COL_THR_MSK = 7<<10, /* Bit 12..10: Collision Threshold */ 1515}; 1516 1517#define TX_COL_THR(x) (((x)<<10) & GM_TXCR_COL_THR_MSK) 1518#define TX_COL_DEF 0x04 1519 1520/* GM_RX_CTRL 16 bit r/w Receive Control Register */ 1521enum { 1522 GM_RXCR_UCF_ENA = 1<<15, /* Bit 15: Enable Unicast filtering */ 1523 GM_RXCR_MCF_ENA = 1<<14, /* Bit 14: Enable Multicast filtering */ 1524 GM_RXCR_CRC_DIS = 1<<13, /* Bit 13: Remove 4-byte CRC */ 1525 GM_RXCR_PASS_FC = 1<<12, /* Bit 12: Pass FC packets to FIFO */ 1526}; 1527 1528/* GM_TX_PARAM 16 bit r/w Transmit Parameter Register */ 1529enum { 1530 GM_TXPA_JAMLEN_MSK = 0x03<<14, /* Bit 15..14: Jam Length */ 1531 GM_TXPA_JAMIPG_MSK = 0x1f<<9, /* Bit 13..9: Jam IPG */ 1532 GM_TXPA_JAMDAT_MSK = 0x1f<<4, /* Bit 8..4: IPG Jam to Data */ 1533 GM_TXPA_BO_LIM_MSK = 0x0f, /* Bit 3.. 0: Backoff Limit Mask */ 1534 1535 TX_JAM_LEN_DEF = 0x03, 1536 TX_JAM_IPG_DEF = 0x0b, 1537 TX_IPG_JAM_DEF = 0x1c, 1538 TX_BOF_LIM_DEF = 0x04, 1539}; 1540 1541#define TX_JAM_LEN_VAL(x) (((x)<<14) & GM_TXPA_JAMLEN_MSK) 1542#define TX_JAM_IPG_VAL(x) (((x)<<9) & GM_TXPA_JAMIPG_MSK) 1543#define TX_IPG_JAM_DATA(x) (((x)<<4) & GM_TXPA_JAMDAT_MSK) 1544#define TX_BACK_OFF_LIM(x) ((x) & GM_TXPA_BO_LIM_MSK) 1545 1546 1547/* GM_SERIAL_MODE 16 bit r/w Serial Mode Register */ 1548enum { 1549 GM_SMOD_DATABL_MSK = 0x1f<<11, /* Bit 15..11: Data Blinder (r/o) */ 1550 GM_SMOD_LIMIT_4 = 1<<10, /* Bit 10: 4 consecutive Tx trials */ 1551 GM_SMOD_VLAN_ENA = 1<<9, /* Bit 9: Enable VLAN (Max. Frame Len) */ 1552 GM_SMOD_JUMBO_ENA = 1<<8, /* Bit 8: Enable Jumbo (Max. Frame Len) */ 1553 GM_SMOD_IPG_MSK = 0x1f /* Bit 4..0: Inter-Packet Gap (IPG) */ 1554}; 1555 1556#define DATA_BLIND_VAL(x) (((x)<<11) & GM_SMOD_DATABL_MSK) 1557#define DATA_BLIND_DEF 0x04 1558 1559#define IPG_DATA_VAL(x) (x & GM_SMOD_IPG_MSK) 1560#define IPG_DATA_DEF 0x1e 1561 1562/* GM_SMI_CTRL 16 bit r/w SMI Control Register */ 1563enum { 1564 GM_SMI_CT_PHY_A_MSK = 0x1f<<11,/* Bit 15..11: PHY Device Address */ 1565 GM_SMI_CT_REG_A_MSK = 0x1f<<6,/* Bit 10.. 6: PHY Register Address */ 1566 GM_SMI_CT_OP_RD = 1<<5, /* Bit 5: OpCode Read (0=Write)*/ 1567 GM_SMI_CT_RD_VAL = 1<<4, /* Bit 4: Read Valid (Read completed) */ 1568 GM_SMI_CT_BUSY = 1<<3, /* Bit 3: Busy (Operation in progress) */ 1569}; 1570 1571#define GM_SMI_CT_PHY_AD(x) (((u16)(x)<<11) & GM_SMI_CT_PHY_A_MSK) 1572#define GM_SMI_CT_REG_AD(x) (((u16)(x)<<6) & GM_SMI_CT_REG_A_MSK) 1573 1574/* GM_PHY_ADDR 16 bit r/w GPHY Address Register */ 1575enum { 1576 GM_PAR_MIB_CLR = 1<<5, /* Bit 5: Set MIB Clear Counter Mode */ 1577 GM_PAR_MIB_TST = 1<<4, /* Bit 4: MIB Load Counter (Test Mode) */ 1578}; 1579 1580/* Receive Frame Status Encoding */ 1581enum { 1582 GMR_FS_LEN = 0xffff<<16, /* Bit 31..16: Rx Frame Length */ 1583 GMR_FS_VLAN = 1<<13, /* VLAN Packet */ 1584 GMR_FS_JABBER = 1<<12, /* Jabber Packet */ 1585 GMR_FS_UN_SIZE = 1<<11, /* Undersize Packet */ 1586 GMR_FS_MC = 1<<10, /* Multicast Packet */ 1587 GMR_FS_BC = 1<<9, /* Broadcast Packet */ 1588 GMR_FS_RX_OK = 1<<8, /* Receive OK (Good Packet) */ 1589 GMR_FS_GOOD_FC = 1<<7, /* Good Flow-Control Packet */ 1590 GMR_FS_BAD_FC = 1<<6, /* Bad Flow-Control Packet */ 1591 GMR_FS_MII_ERR = 1<<5, /* MII Error */ 1592 GMR_FS_LONG_ERR = 1<<4, /* Too Long Packet */ 1593 GMR_FS_FRAGMENT = 1<<3, /* Fragment */ 1594 1595 GMR_FS_CRC_ERR = 1<<1, /* CRC Error */ 1596 GMR_FS_RX_FF_OV = 1<<0, /* Rx FIFO Overflow */ 1597 1598 GMR_FS_ANY_ERR = GMR_FS_RX_FF_OV | GMR_FS_CRC_ERR | 1599 GMR_FS_FRAGMENT | GMR_FS_LONG_ERR | 1600 GMR_FS_MII_ERR | GMR_FS_BAD_FC | 1601 GMR_FS_UN_SIZE | GMR_FS_JABBER, 1602}; 1603 1604/* RX_GMF_CTRL_T 32 bit Rx GMAC FIFO Control/Test */ 1605enum { 1606 RX_TRUNC_ON = 1<<27, /* enable packet truncation */ 1607 RX_TRUNC_OFF = 1<<26, /* disable packet truncation */ 1608 RX_VLAN_STRIP_ON = 1<<25, /* enable VLAN stripping */ 1609 RX_VLAN_STRIP_OFF = 1<<24, /* disable VLAN stripping */ 1610 1611 GMF_WP_TST_ON = 1<<14, /* Write Pointer Test On */ 1612 GMF_WP_TST_OFF = 1<<13, /* Write Pointer Test Off */ 1613 GMF_WP_STEP = 1<<12, /* Write Pointer Step/Increment */ 1614 1615 GMF_RP_TST_ON = 1<<10, /* Read Pointer Test On */ 1616 GMF_RP_TST_OFF = 1<<9, /* Read Pointer Test Off */ 1617 GMF_RP_STEP = 1<<8, /* Read Pointer Step/Increment */ 1618 GMF_RX_F_FL_ON = 1<<7, /* Rx FIFO Flush Mode On */ 1619 GMF_RX_F_FL_OFF = 1<<6, /* Rx FIFO Flush Mode Off */ 1620 GMF_CLI_RX_FO = 1<<5, /* Clear IRQ Rx FIFO Overrun */ 1621 GMF_CLI_RX_C = 1<<4, /* Clear IRQ Rx Frame Complete */ 1622 1623 GMF_OPER_ON = 1<<3, /* Operational Mode On */ 1624 GMF_OPER_OFF = 1<<2, /* Operational Mode Off */ 1625 GMF_RST_CLR = 1<<1, /* Clear GMAC FIFO Reset */ 1626 GMF_RST_SET = 1<<0, /* Set GMAC FIFO Reset */ 1627 1628 RX_GMF_FL_THR_DEF = 0xa, /* flush threshold (default) */ 1629 1630 GMF_RX_CTRL_DEF = GMF_OPER_ON | GMF_RX_F_FL_ON, 1631}; 1632 1633 1634/* TX_GMF_CTRL_T 32 bit Tx GMAC FIFO Control/Test */ 1635enum { 1636 TX_STFW_DIS = 1<<31,/* Disable Store & Forward (Yukon-EC Ultra) */ 1637 TX_STFW_ENA = 1<<30,/* Enable Store & Forward (Yukon-EC Ultra) */ 1638 1639 TX_VLAN_TAG_ON = 1<<25,/* enable VLAN tagging */ 1640 TX_VLAN_TAG_OFF = 1<<24,/* disable VLAN tagging */ 1641 1642 TX_JUMBO_ENA = 1<<23,/* PCI Jumbo Mode enable (Yukon-EC Ultra) */ 1643 TX_JUMBO_DIS = 1<<22,/* PCI Jumbo Mode enable (Yukon-EC Ultra) */ 1644 1645 GMF_WSP_TST_ON = 1<<18,/* Write Shadow Pointer Test On */ 1646 GMF_WSP_TST_OFF = 1<<17,/* Write Shadow Pointer Test Off */ 1647 GMF_WSP_STEP = 1<<16,/* Write Shadow Pointer Step/Increment */ 1648 1649 GMF_CLI_TX_FU = 1<<6, /* Clear IRQ Tx FIFO Underrun */ 1650 GMF_CLI_TX_FC = 1<<5, /* Clear IRQ Tx Frame Complete */ 1651 GMF_CLI_TX_PE = 1<<4, /* Clear IRQ Tx Parity Error */ 1652}; 1653 1654/* GMAC_TI_ST_CTRL 8 bit Time Stamp Timer Ctrl Reg (YUKON only) */ 1655enum { 1656 GMT_ST_START = 1<<2, /* Start Time Stamp Timer */ 1657 GMT_ST_STOP = 1<<1, /* Stop Time Stamp Timer */ 1658 GMT_ST_CLR_IRQ = 1<<0, /* Clear Time Stamp Timer IRQ */ 1659}; 1660 1661/* B28_Y2_ASF_STAT_CMD 32 bit ASF Status and Command Reg */ 1662enum { 1663 Y2_ASF_OS_PRES = 1<<4, /* ASF operation system present */ 1664 Y2_ASF_RESET = 1<<3, /* ASF system in reset state */ 1665 Y2_ASF_RUNNING = 1<<2, /* ASF system operational */ 1666 Y2_ASF_CLR_HSTI = 1<<1, /* Clear ASF IRQ */ 1667 Y2_ASF_IRQ = 1<<0, /* Issue an IRQ to ASF system */ 1668 1669 Y2_ASF_UC_STATE = 3<<2, /* ASF uC State */ 1670 Y2_ASF_CLK_HALT = 0, /* ASF system clock stopped */ 1671}; 1672 1673/* B28_Y2_ASF_HOST_COM 32 bit ASF Host Communication Reg */ 1674enum { 1675 Y2_ASF_CLR_ASFI = 1<<1, /* Clear host IRQ */ 1676 Y2_ASF_HOST_IRQ = 1<<0, /* Issue an IRQ to HOST system */ 1677}; 1678/* HCU_CCSR CPU Control and Status Register */ 1679enum { 1680 HCU_CCSR_SMBALERT_MONITOR= 1<<27, /* SMBALERT pin monitor */ 1681 HCU_CCSR_CPU_SLEEP = 1<<26, /* CPU sleep status */ 1682 /* Clock Stretching Timeout */ 1683 HCU_CCSR_CS_TO = 1<<25, 1684 HCU_CCSR_WDOG = 1<<24, /* Watchdog Reset */ 1685 1686 HCU_CCSR_CLR_IRQ_HOST = 1<<17, /* Clear IRQ_HOST */ 1687 HCU_CCSR_SET_IRQ_HCU = 1<<16, /* Set IRQ_HCU */ 1688 1689 HCU_CCSR_AHB_RST = 1<<9, /* Reset AHB bridge */ 1690 HCU_CCSR_CPU_RST_MODE = 1<<8, /* CPU Reset Mode */ 1691 1692 HCU_CCSR_SET_SYNC_CPU = 1<<5, 1693 HCU_CCSR_CPU_CLK_DIVIDE_MSK = 3<<3,/* CPU Clock Divide */ 1694 HCU_CCSR_CPU_CLK_DIVIDE_BASE= 1<<3, 1695 HCU_CCSR_OS_PRSNT = 1<<2, /* ASF OS Present */ 1696/* Microcontroller State */ 1697 HCU_CCSR_UC_STATE_MSK = 3, 1698 HCU_CCSR_UC_STATE_BASE = 1<<0, 1699 HCU_CCSR_ASF_RESET = 0, 1700 HCU_CCSR_ASF_HALTED = 1<<1, 1701 HCU_CCSR_ASF_RUNNING = 1<<0, 1702}; 1703 1704/* HCU_HCSR Host Control and Status Register */ 1705enum { 1706 HCU_HCSR_SET_IRQ_CPU = 1<<16, /* Set IRQ_CPU */ 1707 1708 HCU_HCSR_CLR_IRQ_HCU = 1<<1, /* Clear IRQ_HCU */ 1709 HCU_HCSR_SET_IRQ_HOST = 1<<0, /* Set IRQ_HOST */ 1710}; 1711 1712/* STAT_CTRL 32 bit Status BMU control register (Yukon-2 only) */ 1713enum { 1714 SC_STAT_CLR_IRQ = 1<<4, /* Status Burst IRQ clear */ 1715 SC_STAT_OP_ON = 1<<3, /* Operational Mode On */ 1716 SC_STAT_OP_OFF = 1<<2, /* Operational Mode Off */ 1717 SC_STAT_RST_CLR = 1<<1, /* Clear Status Unit Reset (Enable) */ 1718 SC_STAT_RST_SET = 1<<0, /* Set Status Unit Reset */ 1719}; 1720 1721/* GMAC_CTRL 32 bit GMAC Control Reg (YUKON only) */ 1722enum { 1723 GMC_H_BURST_ON = 1<<7, /* Half Duplex Burst Mode On */ 1724 GMC_H_BURST_OFF = 1<<6, /* Half Duplex Burst Mode Off */ 1725 GMC_F_LOOPB_ON = 1<<5, /* FIFO Loopback On */ 1726 GMC_F_LOOPB_OFF = 1<<4, /* FIFO Loopback Off */ 1727 GMC_PAUSE_ON = 1<<3, /* Pause On */ 1728 GMC_PAUSE_OFF = 1<<2, /* Pause Off */ 1729 GMC_RST_CLR = 1<<1, /* Clear GMAC Reset */ 1730 GMC_RST_SET = 1<<0, /* Set GMAC Reset */ 1731}; 1732 1733/* GPHY_CTRL 32 bit GPHY Control Reg (YUKON only) */ 1734enum { 1735 GPC_RST_CLR = 1<<1, /* Clear GPHY Reset */ 1736 GPC_RST_SET = 1<<0, /* Set GPHY Reset */ 1737}; 1738 1739/* GMAC_IRQ_SRC 8 bit GMAC Interrupt Source Reg (YUKON only) */ 1740/* GMAC_IRQ_MSK 8 bit GMAC Interrupt Mask Reg (YUKON only) */ 1741enum { 1742 GM_IS_TX_CO_OV = 1<<5, /* Transmit Counter Overflow IRQ */ 1743 GM_IS_RX_CO_OV = 1<<4, /* Receive Counter Overflow IRQ */ 1744 GM_IS_TX_FF_UR = 1<<3, /* Transmit FIFO Underrun */ 1745 GM_IS_TX_COMPL = 1<<2, /* Frame Transmission Complete */ 1746 GM_IS_RX_FF_OR = 1<<1, /* Receive FIFO Overrun */ 1747 GM_IS_RX_COMPL = 1<<0, /* Frame Reception Complete */ 1748 1749#define GMAC_DEF_MSK GM_IS_TX_FF_UR 1750}; 1751 1752/* GMAC_LINK_CTRL 16 bit GMAC Link Control Reg (YUKON only) */ 1753enum { /* Bits 15.. 2: reserved */ 1754 GMLC_RST_CLR = 1<<1, /* Clear GMAC Link Reset */ 1755 GMLC_RST_SET = 1<<0, /* Set GMAC Link Reset */ 1756}; 1757 1758 1759/* WOL_CTRL_STAT 16 bit WOL Control/Status Reg */ 1760enum { 1761 WOL_CTL_LINK_CHG_OCC = 1<<15, 1762 WOL_CTL_MAGIC_PKT_OCC = 1<<14, 1763 WOL_CTL_PATTERN_OCC = 1<<13, 1764 WOL_CTL_CLEAR_RESULT = 1<<12, 1765 WOL_CTL_ENA_PME_ON_LINK_CHG = 1<<11, 1766 WOL_CTL_DIS_PME_ON_LINK_CHG = 1<<10, 1767 WOL_CTL_ENA_PME_ON_MAGIC_PKT = 1<<9, 1768 WOL_CTL_DIS_PME_ON_MAGIC_PKT = 1<<8, 1769 WOL_CTL_ENA_PME_ON_PATTERN = 1<<7, 1770 WOL_CTL_DIS_PME_ON_PATTERN = 1<<6, 1771 WOL_CTL_ENA_LINK_CHG_UNIT = 1<<5, 1772 WOL_CTL_DIS_LINK_CHG_UNIT = 1<<4, 1773 WOL_CTL_ENA_MAGIC_PKT_UNIT = 1<<3, 1774 WOL_CTL_DIS_MAGIC_PKT_UNIT = 1<<2, 1775 WOL_CTL_ENA_PATTERN_UNIT = 1<<1, 1776 WOL_CTL_DIS_PATTERN_UNIT = 1<<0, 1777}; 1778 1779 1780/* Control flags */ 1781enum { 1782 UDPTCP = 1<<0, 1783 CALSUM = 1<<1, 1784 WR_SUM = 1<<2, 1785 INIT_SUM= 1<<3, 1786 LOCK_SUM= 1<<4, 1787 INS_VLAN= 1<<5, 1788 EOP = 1<<7, 1789}; 1790 1791enum { 1792 HW_OWNER = 1<<7, 1793 OP_TCPWRITE = 0x11, 1794 OP_TCPSTART = 0x12, 1795 OP_TCPINIT = 0x14, 1796 OP_TCPLCK = 0x18, 1797 OP_TCPCHKSUM = OP_TCPSTART, 1798 OP_TCPIS = OP_TCPINIT | OP_TCPSTART, 1799 OP_TCPLW = OP_TCPLCK | OP_TCPWRITE, 1800 OP_TCPLSW = OP_TCPLCK | OP_TCPSTART | OP_TCPWRITE, 1801 OP_TCPLISW = OP_TCPLCK | OP_TCPINIT | OP_TCPSTART | OP_TCPWRITE, 1802 1803 OP_ADDR64 = 0x21, 1804 OP_VLAN = 0x22, 1805 OP_ADDR64VLAN = OP_ADDR64 | OP_VLAN, 1806 OP_LRGLEN = 0x24, 1807 OP_LRGLENVLAN = OP_LRGLEN | OP_VLAN, 1808 OP_BUFFER = 0x40, 1809 OP_PACKET = 0x41, 1810 OP_LARGESEND = 0x43, 1811 1812/* YUKON-2 STATUS opcodes defines */ 1813 OP_RXSTAT = 0x60, 1814 OP_RXTIMESTAMP = 0x61, 1815 OP_RXVLAN = 0x62, 1816 OP_RXCHKS = 0x64, 1817 OP_RXCHKSVLAN = OP_RXCHKS | OP_RXVLAN, 1818 OP_RXTIMEVLAN = OP_RXTIMESTAMP | OP_RXVLAN, 1819 OP_RSS_HASH = 0x65, 1820 OP_TXINDEXLE = 0x68, 1821}; 1822 1823/* Yukon 2 hardware interface */ 1824struct sky2_tx_le { 1825 __le32 addr; 1826 __le16 length; /* also vlan tag or checksum start */ 1827 u8 ctrl; 1828 u8 opcode; 1829} __attribute((packed)); 1830 1831struct sky2_rx_le { 1832 __le32 addr; 1833 __le16 length; 1834 u8 ctrl; 1835 u8 opcode; 1836} __attribute((packed)); 1837 1838struct sky2_status_le { 1839 __le32 status; /* also checksum */ 1840 __le16 length; /* also vlan tag */ 1841 u8 link; 1842 u8 opcode; 1843} __attribute((packed)); 1844 1845struct tx_ring_info { 1846 struct sk_buff *skb; 1847 DECLARE_PCI_UNMAP_ADDR(mapaddr); 1848 DECLARE_PCI_UNMAP_ADDR(maplen); 1849}; 1850 1851struct rx_ring_info { 1852 struct sk_buff *skb; 1853 dma_addr_t data_addr; 1854 DECLARE_PCI_UNMAP_ADDR(data_size); 1855 dma_addr_t frag_addr[ETH_JUMBO_MTU >> PAGE_SHIFT]; 1856}; 1857 1858enum flow_control { 1859 FC_NONE = 0, 1860 FC_TX = 1, 1861 FC_RX = 2, 1862 FC_BOTH = 3, 1863}; 1864 1865struct sky2_port { 1866 struct sky2_hw *hw; 1867 struct net_device *netdev; 1868 unsigned port; 1869 u32 msg_enable; 1870 spinlock_t phy_lock; 1871 1872 struct tx_ring_info *tx_ring; 1873 struct sky2_tx_le *tx_le; 1874 u16 tx_cons; /* next le to check */ 1875 u16 tx_prod; /* next le to use */ 1876 u32 tx_addr64; 1877 u16 tx_pending; 1878 u16 tx_last_mss; 1879 u32 tx_tcpsum; 1880 1881 struct rx_ring_info *rx_ring ____cacheline_aligned_in_smp; 1882 struct sky2_rx_le *rx_le; 1883 u32 rx_addr64; 1884 u16 rx_next; /* next re to check */ 1885 u16 rx_put; /* next le index to use */ 1886 u16 rx_pending; 1887 u16 rx_data_size; 1888 u16 rx_nfrags; 1889 1890#ifdef SKY2_VLAN_TAG_USED 1891 u16 rx_tag; 1892 struct vlan_group *vlgrp; 1893#endif 1894 1895 dma_addr_t rx_le_map; 1896 dma_addr_t tx_le_map; 1897 u16 advertising; /* ADVERTISED_ bits */ 1898 u16 speed; /* SPEED_1000, SPEED_100, ... */ 1899 u8 autoneg; /* AUTONEG_ENABLE, AUTONEG_DISABLE */ 1900 u8 duplex; /* DUPLEX_HALF, DUPLEX_FULL */ 1901 u8 rx_csum; 1902 u8 wol; 1903 enum flow_control flow_mode; 1904 enum flow_control flow_status; 1905 1906 struct net_device_stats net_stats; 1907 1908}; 1909 1910struct sky2_hw { 1911 void __iomem *regs; 1912 struct pci_dev *pdev; 1913 struct net_device *dev[2]; 1914 1915 u8 chip_id; 1916 u8 chip_rev; 1917 u8 pmd_type; 1918 u8 ports; 1919 1920 struct sky2_status_le *st_le; 1921 u32 st_idx; 1922 dma_addr_t st_dma; 1923 1924 struct timer_list idle_timer; 1925 struct work_struct restart_work; 1926 int msi; 1927 wait_queue_head_t msi_wait; 1928}; 1929 1930static inline int sky2_is_copper(const struct sky2_hw *hw) 1931{ 1932 return !(hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P'); 1933} 1934 1935/* Register accessor for memory mapped device */ 1936static inline u32 sky2_read32(const struct sky2_hw *hw, unsigned reg) 1937{ 1938 return readl(hw->regs + reg); 1939} 1940 1941static inline u16 sky2_read16(const struct sky2_hw *hw, unsigned reg) 1942{ 1943 return readw(hw->regs + reg); 1944} 1945 1946static inline u8 sky2_read8(const struct sky2_hw *hw, unsigned reg) 1947{ 1948 return readb(hw->regs + reg); 1949} 1950 1951static inline void sky2_write32(const struct sky2_hw *hw, unsigned reg, u32 val) 1952{ 1953 writel(val, hw->regs + reg); 1954} 1955 1956static inline void sky2_write16(const struct sky2_hw *hw, unsigned reg, u16 val) 1957{ 1958 writew(val, hw->regs + reg); 1959} 1960 1961static inline void sky2_write8(const struct sky2_hw *hw, unsigned reg, u8 val) 1962{ 1963 writeb(val, hw->regs + reg); 1964} 1965 1966/* Yukon PHY related registers */ 1967#define SK_GMAC_REG(port,reg) \ 1968 (BASE_GMAC_1 + (port) * (BASE_GMAC_2-BASE_GMAC_1) + (reg)) 1969#define GM_PHY_RETRIES 100 1970 1971static inline u16 gma_read16(const struct sky2_hw *hw, unsigned port, unsigned reg) 1972{ 1973 return sky2_read16(hw, SK_GMAC_REG(port,reg)); 1974} 1975 1976static inline u32 gma_read32(struct sky2_hw *hw, unsigned port, unsigned reg) 1977{ 1978 unsigned base = SK_GMAC_REG(port, reg); 1979 return (u32) sky2_read16(hw, base) 1980 | (u32) sky2_read16(hw, base+4) << 16; 1981} 1982 1983static inline void gma_write16(const struct sky2_hw *hw, unsigned port, int r, u16 v) 1984{ 1985 sky2_write16(hw, SK_GMAC_REG(port,r), v); 1986} 1987 1988static inline void gma_set_addr(struct sky2_hw *hw, unsigned port, unsigned reg, 1989 const u8 *addr) 1990{ 1991 gma_write16(hw, port, reg, (u16) addr[0] | ((u16) addr[1] << 8)); 1992 gma_write16(hw, port, reg+4,(u16) addr[2] | ((u16) addr[3] << 8)); 1993 gma_write16(hw, port, reg+8,(u16) addr[4] | ((u16) addr[5] << 8)); 1994} 1995 1996/* PCI config space access */ 1997static inline u32 sky2_pci_read32(const struct sky2_hw *hw, unsigned reg) 1998{ 1999 return sky2_read32(hw, Y2_CFG_SPC + reg); 2000} 2001 2002static inline u16 sky2_pci_read16(const struct sky2_hw *hw, unsigned reg) 2003{ 2004 return sky2_read16(hw, Y2_CFG_SPC + reg); 2005} 2006 2007static inline void sky2_pci_write32(struct sky2_hw *hw, unsigned reg, u32 val) 2008{ 2009 sky2_write32(hw, Y2_CFG_SPC + reg, val); 2010} 2011 2012static inline void sky2_pci_write16(struct sky2_hw *hw, unsigned reg, u16 val) 2013{ 2014 sky2_write16(hw, Y2_CFG_SPC + reg, val); 2015} 2016#endif 2017