1/****************************************************************************** 2 * 3 * Name: skgeinit.c 4 * Project: Gigabit Ethernet Adapters, Common Modules 5 * Version: $Revision: 1.1.1.1 $ 6 * Date: $Date: 2007/08/03 18:52:48 $ 7 * Purpose: Contains functions to initialize the adapter 8 * 9 ******************************************************************************/ 10 11/****************************************************************************** 12 * 13 * (C)Copyright 1998-2002 SysKonnect. 14 * (C)Copyright 2002-2003 Marvell. 15 * 16 * This program is free software; you can redistribute it and/or modify 17 * it under the terms of the GNU General Public License as published by 18 * the Free Software Foundation; either version 2 of the License, or 19 * (at your option) any later version. 20 * 21 * The information in this file is provided "AS IS" without warranty. 22 * 23 ******************************************************************************/ 24 25#include "h/skdrv1st.h" 26#include "h/skdrv2nd.h" 27 28/* global variables ***********************************************************/ 29 30/* local variables ************************************************************/ 31 32#if (defined(DEBUG) || (!defined(LINT) && !defined(SK_SLIM))) 33static const char SysKonnectFileId[] = 34 "@(#) $Id: skgeinit.c,v 1.1.1.1 2007/08/03 18:52:48 Exp $ (C) Marvell."; 35#endif 36 37struct s_QOffTab { 38 int RxQOff; /* Receive Queue Address Offset */ 39 int XsQOff; /* Sync Tx Queue Address Offset */ 40 int XaQOff; /* Async Tx Queue Address Offset */ 41}; 42static struct s_QOffTab QOffTab[] = { 43 {Q_R1, Q_XS1, Q_XA1}, {Q_R2, Q_XS2, Q_XA2} 44}; 45 46struct s_Config { 47 char ScanString[8]; 48 SK_U32 Value; 49}; 50 51static struct s_Config OemConfig = { 52 {'O','E','M','_','C','o','n','f'}, 53#ifdef SK_OEM_CONFIG 54 OEM_CONFIG_VALUE, 55#else 56 0, 57#endif 58}; 59 60/****************************************************************************** 61 * 62 * SkGePollTxD() - Enable / Disable Descriptor Polling of TxD Rings 63 * 64 * Description: 65 * Enable or disable the descriptor polling of the transmit descriptor 66 * ring(s) (TxD) for port 'Port'. 67 * The new configuration is *not* saved over any SkGeStopPort() and 68 * SkGeInitPort() calls. 69 * 70 * Returns: 71 * nothing 72 */ 73void SkGePollTxD( 74SK_AC *pAC, /* adapter context */ 75SK_IOC IoC, /* IO context */ 76int Port, /* Port Index (MAC_1 + n) */ 77SK_BOOL PollTxD) /* SK_TRUE (enable pol.), SK_FALSE (disable pol.) */ 78{ 79 SK_GEPORT *pPrt; 80 SK_U32 DWord; 81 82 pPrt = &pAC->GIni.GP[Port]; 83 84 DWord = (SK_U32)(PollTxD ? CSR_ENA_POL : CSR_DIS_POL); 85 86 if (pPrt->PXSQSize != 0) { 87 SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), DWord); 88 } 89 90 if (pPrt->PXAQSize != 0) { 91 SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), DWord); 92 } 93} /* SkGePollTxD */ 94 95 96/****************************************************************************** 97 * 98 * SkGeYellowLED() - Switch the yellow LED on or off. 99 * 100 * Description: 101 * Switch the yellow LED on or off. 102 * 103 * Note: 104 * This function may be called any time after SkGeInit(Level 1). 105 * 106 * Returns: 107 * nothing 108 */ 109void SkGeYellowLED( 110SK_AC *pAC, /* adapter context */ 111SK_IOC IoC, /* IO context */ 112int State) /* yellow LED state, 0 = OFF, 0 != ON */ 113{ 114 if (State == 0) { 115 /* Switch yellow LED OFF */ 116 SK_OUT8(IoC, B0_LED, LED_STAT_OFF); 117 } 118 else { 119 /* Switch yellow LED ON */ 120 SK_OUT8(IoC, B0_LED, LED_STAT_ON); 121 } 122} /* SkGeYellowLED */ 123 124 125#if (!defined(SK_SLIM) || defined(GENESIS)) 126/****************************************************************************** 127 * 128 * SkGeXmitLED() - Modify the Operational Mode of a transmission LED. 129 * 130 * Description: 131 * The Rx or Tx LED which is specified by 'Led' will be 132 * enabled, disabled or switched on in test mode. 133 * 134 * Note: 135 * 'Led' must contain the address offset of the LEDs INI register. 136 * 137 * Usage: 138 * SkGeXmitLED(pAC, IoC, MR_ADDR(Port, TX_LED_INI), SK_LED_ENA); 139 * 140 * Returns: 141 * nothing 142 */ 143void SkGeXmitLED( 144SK_AC *pAC, /* adapter context */ 145SK_IOC IoC, /* IO context */ 146int Led, /* offset to the LED Init Value register */ 147int Mode) /* Mode may be SK_LED_DIS, SK_LED_ENA, SK_LED_TST */ 148{ 149 SK_U32 LedIni; 150 151 switch (Mode) { 152 case SK_LED_ENA: 153 LedIni = SK_XMIT_DUR * (SK_U32)pAC->GIni.GIHstClkFact / 100; 154 SK_OUT32(IoC, Led + XMIT_LED_INI, LedIni); 155 SK_OUT8(IoC, Led + XMIT_LED_CTRL, LED_START); 156 break; 157 case SK_LED_TST: 158 SK_OUT8(IoC, Led + XMIT_LED_TST, LED_T_ON); 159 SK_OUT32(IoC, Led + XMIT_LED_CNT, 100); 160 SK_OUT8(IoC, Led + XMIT_LED_CTRL, LED_START); 161 break; 162 case SK_LED_DIS: 163 default: 164 /* 165 * Do NOT stop the LED Timer here. The LED might be 166 * in on state. But it needs to go off. 167 */ 168 SK_OUT32(IoC, Led + XMIT_LED_CNT, 0); 169 SK_OUT8(IoC, Led + XMIT_LED_TST, LED_T_OFF); 170 break; 171 } 172 173} /* SkGeXmitLED */ 174#endif /* !SK_SLIM || GENESIS */ 175 176 177/****************************************************************************** 178 * 179 * DoCalcAddr() - Calculates the start and the end address of a queue. 180 * 181 * Description: 182 * This function calculates the start and the end address of a queue. 183 * Afterwards the 'StartVal' is incremented to the next start position. 184 * If the port is already initialized the calculated values 185 * will be checked against the configured values and an 186 * error will be returned, if they are not equal. 187 * If the port is not initialized the values will be written to 188 * *StartAdr and *EndAddr. 189 * 190 * Returns: 191 * 0: success 192 * 1: configuration error 193 */ 194static int DoCalcAddr( 195SK_AC *pAC, /* adapter context */ 196SK_GEPORT SK_FAR *pPrt, /* port index */ 197int QuSize, /* size of the queue to configure in kB */ 198SK_U32 SK_FAR *StartVal, /* start value for address calculation */ 199SK_U32 SK_FAR *QuStartAddr,/* start addr to calculate */ 200SK_U32 SK_FAR *QuEndAddr) /* end address to calculate */ 201{ 202 SK_U32 EndVal; 203 SK_U32 NextStart; 204 int Rtv; 205 206 Rtv = 0; 207 if (QuSize == 0) { 208 EndVal = *StartVal; 209 NextStart = EndVal; 210 } 211 else { 212 EndVal = *StartVal + ((SK_U32)QuSize * 1024) - 1; 213 NextStart = EndVal + 1; 214 } 215 216 if (pPrt->PState >= SK_PRT_INIT) { 217 if (*StartVal != *QuStartAddr || EndVal != *QuEndAddr) { 218 Rtv = 1; 219 } 220 } 221 else { 222 *QuStartAddr = *StartVal; 223 *QuEndAddr = EndVal; 224 } 225 226 *StartVal = NextStart; 227 return(Rtv); 228} /* DoCalcAddr */ 229 230/****************************************************************************** 231 * 232 * SkGeInitAssignRamToQueues() - allocate default queue sizes 233 * 234 * Description: 235 * This function assigns the memory to the different queues and ports. 236 * When DualNet is set to SK_TRUE all ports get the same amount of memory. 237 * Otherwise the first port gets most of the memory and all the 238 * other ports just the required minimum. 239 * This function can only be called when pAC->GIni.GIRamSize and 240 * pAC->GIni.GIMacsFound have been initialized, usually this happens 241 * at init level 1 242 * 243 * Returns: 244 * 0 - ok 245 * 1 - invalid input values 246 * 2 - not enough memory 247 */ 248 249int SkGeInitAssignRamToQueues( 250SK_AC *pAC, /* Adapter context */ 251int ActivePort, /* Active Port in RLMT mode */ 252SK_BOOL DualNet) /* adapter context */ 253{ 254 int i; 255 int UsedKilobytes; /* memory already assigned */ 256 int ActivePortKilobytes; /* memory available for active port */ 257 SK_GEPORT *pGePort; 258 259 UsedKilobytes = 0; 260 261 if (ActivePort >= pAC->GIni.GIMacsFound) { 262 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT, 263 ("SkGeInitAssignRamToQueues: ActivePort (%d) invalid\n", 264 ActivePort)); 265 return(1); 266 } 267 if (((pAC->GIni.GIMacsFound * (SK_MIN_RXQ_SIZE + SK_MIN_TXQ_SIZE)) + 268 ((RAM_QUOTA_SYNC == 0) ? 0 : SK_MIN_TXQ_SIZE)) > pAC->GIni.GIRamSize) { 269 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT, 270 ("SkGeInitAssignRamToQueues: Not enough memory (%d)\n", 271 pAC->GIni.GIRamSize)); 272 return(2); 273 } 274 275 if (DualNet) { 276 /* every port gets the same amount of memory */ 277 ActivePortKilobytes = pAC->GIni.GIRamSize / pAC->GIni.GIMacsFound; 278 for (i = 0; i < pAC->GIni.GIMacsFound; i++) { 279 280 pGePort = &pAC->GIni.GP[i]; 281 282 /* take away the minimum memory for active queues */ 283 ActivePortKilobytes -= (SK_MIN_RXQ_SIZE + SK_MIN_TXQ_SIZE); 284 285 /* receive queue gets the minimum + 80% of the rest */ 286 pGePort->PRxQSize = (int) (ROUND_QUEUE_SIZE_KB(( 287 ActivePortKilobytes * (unsigned long) RAM_QUOTA_RX) / 100)) 288 + SK_MIN_RXQ_SIZE; 289 290 ActivePortKilobytes -= (pGePort->PRxQSize - SK_MIN_RXQ_SIZE); 291 292 /* synchronous transmit queue */ 293 pGePort->PXSQSize = 0; 294 295 /* asynchronous transmit queue */ 296 pGePort->PXAQSize = (int) ROUND_QUEUE_SIZE_KB(ActivePortKilobytes + 297 SK_MIN_TXQ_SIZE); 298 } 299 } 300 else { 301 /* Rlmt Mode or single link adapter */ 302 303 /* Set standby queue size defaults for all standby ports */ 304 for (i = 0; i < pAC->GIni.GIMacsFound; i++) { 305 306 if (i != ActivePort) { 307 pGePort = &pAC->GIni.GP[i]; 308 309 pGePort->PRxQSize = SK_MIN_RXQ_SIZE; 310 pGePort->PXAQSize = SK_MIN_TXQ_SIZE; 311 pGePort->PXSQSize = 0; 312 313 /* Count used RAM */ 314 UsedKilobytes += pGePort->PRxQSize + pGePort->PXAQSize; 315 } 316 } 317 /* what's left? */ 318 ActivePortKilobytes = pAC->GIni.GIRamSize - UsedKilobytes; 319 320 /* assign it to the active port */ 321 /* first take away the minimum memory */ 322 ActivePortKilobytes -= (SK_MIN_RXQ_SIZE + SK_MIN_TXQ_SIZE); 323 pGePort = &pAC->GIni.GP[ActivePort]; 324 325 /* receive queue get's the minimum + 80% of the rest */ 326 pGePort->PRxQSize = (int) (ROUND_QUEUE_SIZE_KB((ActivePortKilobytes * 327 (unsigned long) RAM_QUOTA_RX) / 100)) + SK_MIN_RXQ_SIZE; 328 329 ActivePortKilobytes -= (pGePort->PRxQSize - SK_MIN_RXQ_SIZE); 330 331 /* synchronous transmit queue */ 332 pGePort->PXSQSize = 0; 333 334 /* asynchronous transmit queue */ 335 pGePort->PXAQSize = (int) ROUND_QUEUE_SIZE_KB(ActivePortKilobytes) + 336 SK_MIN_TXQ_SIZE; 337 } 338#ifdef VCPU 339 VCPUprintf(0, "PRxQSize=%u, PXSQSize=%u, PXAQSize=%u\n", 340 pGePort->PRxQSize, pGePort->PXSQSize, pGePort->PXAQSize); 341#endif /* VCPU */ 342 343 return(0); 344} /* SkGeInitAssignRamToQueues */ 345 346/****************************************************************************** 347 * 348 * SkGeCheckQSize() - Checks the Adapters Queue Size Configuration 349 * 350 * Description: 351 * This function verifies the Queue Size Configuration specified 352 * in the variables PRxQSize, PXSQSize, and PXAQSize of all 353 * used ports. 354 * This requirements must be fullfilled to have a valid configuration: 355 * - The size of all queues must not exceed GIRamSize. 356 * - The queue sizes must be specified in units of 8 kB. 357 * - The size of Rx queues of available ports must not be 358 * smaller than 16 kB. 359 * - The size of at least one Tx queue (synch. or asynch.) 360 * of available ports must not be smaller than 16 kB 361 * when Jumbo Frames are used. 362 * - The RAM start and end addresses must not be changed 363 * for ports which are already initialized. 364 * Furthermore SkGeCheckQSize() defines the Start and End Addresses 365 * of all ports and stores them into the HWAC port structure. 366 * 367 * Returns: 368 * 0: Queue Size Configuration valid 369 * 1: Queue Size Configuration invalid 370 */ 371static int SkGeCheckQSize( 372SK_AC *pAC, /* adapter context */ 373int Port) /* port index */ 374{ 375 SK_GEPORT *pPrt; 376 int i; 377 int Rtv; 378 int Rtv2; 379 SK_U32 StartAddr; 380#ifndef SK_SLIM 381 int UsedMem; /* total memory used (max. found ports) */ 382#endif 383 384 Rtv = 0; 385 386#ifndef SK_SLIM 387 388 UsedMem = 0; 389 for (i = 0; i < pAC->GIni.GIMacsFound; i++) { 390 pPrt = &pAC->GIni.GP[i]; 391 392 if ((pPrt->PRxQSize & QZ_UNITS) != 0 || 393 (pPrt->PXSQSize & QZ_UNITS) != 0 || 394 (pPrt->PXAQSize & QZ_UNITS) != 0) { 395 396 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E012, SKERR_HWI_E012MSG); 397 return(1); 398 } 399 400 if (i == Port && pPrt->PRxQSize < SK_MIN_RXQ_SIZE) { 401 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E011, SKERR_HWI_E011MSG); 402 return(1); 403 } 404 405 /* 406 * the size of at least one Tx queue (synch. or asynch.) has to be > 0. 407 * if Jumbo Frames are used, this size has to be >= 16 kB. 408 */ 409 if ((i == Port && pPrt->PXSQSize == 0 && pPrt->PXAQSize == 0) || 410 (pAC->GIni.GIPortUsage == SK_JUMBO_LINK && 411 ((pPrt->PXSQSize > 0 && pPrt->PXSQSize < SK_MIN_TXQ_SIZE) || 412 (pPrt->PXAQSize > 0 && pPrt->PXAQSize < SK_MIN_TXQ_SIZE)))) { 413 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E023, SKERR_HWI_E023MSG); 414 return(1); 415 } 416 417 UsedMem += pPrt->PRxQSize + pPrt->PXSQSize + pPrt->PXAQSize; 418 } 419 420 if (UsedMem > pAC->GIni.GIRamSize) { 421 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E012, SKERR_HWI_E012MSG); 422 return(1); 423 } 424#endif /* !SK_SLIM */ 425 426 /* Now start address calculation */ 427 StartAddr = pAC->GIni.GIRamOffs; 428 for (i = 0; i < pAC->GIni.GIMacsFound; i++) { 429 pPrt = &pAC->GIni.GP[i]; 430 431 /* Calculate/Check values for the receive queue */ 432 Rtv2 = DoCalcAddr(pAC, pPrt, pPrt->PRxQSize, &StartAddr, 433 &pPrt->PRxQRamStart, &pPrt->PRxQRamEnd); 434 Rtv |= Rtv2; 435 436 /* Calculate/Check values for the synchronous Tx queue */ 437 Rtv2 = DoCalcAddr(pAC, pPrt, pPrt->PXSQSize, &StartAddr, 438 &pPrt->PXsQRamStart, &pPrt->PXsQRamEnd); 439 Rtv |= Rtv2; 440 441 /* Calculate/Check values for the asynchronous Tx queue */ 442 Rtv2 = DoCalcAddr(pAC, pPrt, pPrt->PXAQSize, &StartAddr, 443 &pPrt->PXaQRamStart, &pPrt->PXaQRamEnd); 444 Rtv |= Rtv2; 445 446 if (Rtv) { 447 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E013, SKERR_HWI_E013MSG); 448 return(1); 449 } 450 } 451 452 return(0); 453} /* SkGeCheckQSize */ 454 455 456#ifdef GENESIS 457/****************************************************************************** 458 * 459 * SkGeInitMacArb() - Initialize the MAC Arbiter 460 * 461 * Description: 462 * This function initializes the MAC Arbiter. 463 * It must not be called if there is still an 464 * initialized or active port. 465 * 466 * Returns: 467 * nothing 468 */ 469static void SkGeInitMacArb( 470SK_AC *pAC, /* adapter context */ 471SK_IOC IoC) /* IO context */ 472{ 473 /* release local reset */ 474 SK_OUT16(IoC, B3_MA_TO_CTRL, MA_RST_CLR); 475 476 /* configure timeout values */ 477 SK_OUT8(IoC, B3_MA_TOINI_RX1, SK_MAC_TO_53); 478 SK_OUT8(IoC, B3_MA_TOINI_RX2, SK_MAC_TO_53); 479 SK_OUT8(IoC, B3_MA_TOINI_TX1, SK_MAC_TO_53); 480 SK_OUT8(IoC, B3_MA_TOINI_TX2, SK_MAC_TO_53); 481 482 SK_OUT8(IoC, B3_MA_RCINI_RX1, 0); 483 SK_OUT8(IoC, B3_MA_RCINI_RX2, 0); 484 SK_OUT8(IoC, B3_MA_RCINI_TX1, 0); 485 SK_OUT8(IoC, B3_MA_RCINI_TX2, 0); 486 487 /* recovery values are needed for XMAC II Rev. B2 only */ 488 /* Fast Output Enable Mode was intended to use with Rev. B2, but now? */ 489 490 /* 491 * There is no start or enable button to push, therefore 492 * the MAC arbiter is configured and enabled now. 493 */ 494} /* SkGeInitMacArb */ 495 496 497/****************************************************************************** 498 * 499 * SkGeInitPktArb() - Initialize the Packet Arbiter 500 * 501 * Description: 502 * This function initializes the Packet Arbiter. 503 * It must not be called if there is still an 504 * initialized or active port. 505 * 506 * Returns: 507 * nothing 508 */ 509static void SkGeInitPktArb( 510SK_AC *pAC, /* adapter context */ 511SK_IOC IoC) /* IO context */ 512{ 513 /* release local reset */ 514 SK_OUT16(IoC, B3_PA_CTRL, PA_RST_CLR); 515 516 /* configure timeout values */ 517 SK_OUT16(IoC, B3_PA_TOINI_RX1, SK_PKT_TO_MAX); 518 SK_OUT16(IoC, B3_PA_TOINI_RX2, SK_PKT_TO_MAX); 519 SK_OUT16(IoC, B3_PA_TOINI_TX1, SK_PKT_TO_MAX); 520 SK_OUT16(IoC, B3_PA_TOINI_TX2, SK_PKT_TO_MAX); 521 522 if (pAC->GIni.GIPortUsage != SK_JUMBO_LINK) { 523 if (pAC->GIni.GIMacsFound == 1) { 524 SK_OUT16(IoC, B3_PA_CTRL, PA_ENA_TO_TX1); 525 } 526 else { 527 SK_OUT16(IoC, B3_PA_CTRL, PA_ENA_TO_TX1 | PA_ENA_TO_TX2); 528 } 529 } 530} /* SkGeInitPktArb */ 531#endif /* GENESIS */ 532 533 534/****************************************************************************** 535 * 536 * SkGeInitMacFifo() - Initialize the MAC FIFOs 537 * 538 * Description: 539 * Initialize all MAC FIFOs of the specified port 540 * 541 * Returns: 542 * nothing 543 */ 544static void SkGeInitMacFifo( 545SK_AC *pAC, /* adapter context */ 546SK_IOC IoC, /* IO context */ 547int Port) /* Port Index (MAC_1 + n) */ 548{ 549 SK_U16 Word; 550#ifdef VCPU 551 SK_U32 DWord; 552#endif /* VCPU */ 553 /* 554 * For each FIFO: 555 * - release local reset 556 * - use default value for MAC FIFO size 557 * - setup defaults for the control register 558 * - enable the FIFO 559 */ 560 561#ifdef GENESIS 562 if (pAC->GIni.GIGenesis) { 563 /* Configure Rx MAC FIFO */ 564 SK_OUT8(IoC, MR_ADDR(Port, RX_MFF_CTRL2), MFF_RST_CLR); 565 SK_OUT16(IoC, MR_ADDR(Port, RX_MFF_CTRL1), MFF_RX_CTRL_DEF); 566 SK_OUT8(IoC, MR_ADDR(Port, RX_MFF_CTRL2), MFF_ENA_OP_MD); 567 568 /* Configure Tx MAC FIFO */ 569 SK_OUT8(IoC, MR_ADDR(Port, TX_MFF_CTRL2), MFF_RST_CLR); 570 SK_OUT16(IoC, MR_ADDR(Port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF); 571 SK_OUT8(IoC, MR_ADDR(Port, TX_MFF_CTRL2), MFF_ENA_OP_MD); 572 573 /* Enable frame flushing if jumbo frames used */ 574 if (pAC->GIni.GIPortUsage == SK_JUMBO_LINK) { 575 SK_OUT16(IoC, MR_ADDR(Port, RX_MFF_CTRL1), MFF_ENA_FLUSH); 576 } 577 } 578#endif /* GENESIS */ 579 580#ifdef YUKON 581 if (pAC->GIni.GIYukon) { 582 /* set Rx GMAC FIFO Flush Mask */ 583 SK_OUT16(IoC, MR_ADDR(Port, RX_GMF_FL_MSK), (SK_U16)RX_FF_FL_DEF_MSK); 584 585 Word = (SK_U16)GMF_RX_CTRL_DEF; 586 587 /* disable Rx GMAC FIFO Flush for YUKON-Lite Rev. A0 only */ 588 if (pAC->GIni.GIYukonLite && pAC->GIni.GIChipId == CHIP_ID_YUKON) { 589 590 Word &= ~GMF_RX_F_FL_ON; 591 } 592 593 /* Configure Rx MAC FIFO */ 594 SK_OUT8(IoC, MR_ADDR(Port, RX_GMF_CTRL_T), (SK_U8)GMF_RST_CLR); 595 SK_OUT16(IoC, MR_ADDR(Port, RX_GMF_CTRL_T), Word); 596 597 /* set Rx GMAC FIFO Flush Threshold (default: 0x0a -> 56 bytes) */ 598 SK_OUT16(IoC, MR_ADDR(Port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF); 599 600 /* Configure Tx MAC FIFO */ 601 SK_OUT8(IoC, MR_ADDR(Port, TX_GMF_CTRL_T), (SK_U8)GMF_RST_CLR); 602 SK_OUT16(IoC, MR_ADDR(Port, TX_GMF_CTRL_T), (SK_U16)GMF_TX_CTRL_DEF); 603 604#ifdef VCPU 605 SK_IN32(IoC, MR_ADDR(Port, RX_GMF_AF_THR), &DWord); 606 SK_IN32(IoC, MR_ADDR(Port, TX_GMF_AE_THR), &DWord); 607#endif /* VCPU */ 608 609 /* set Tx GMAC FIFO Almost Empty Threshold */ 610/* SK_OUT32(IoC, MR_ADDR(Port, TX_GMF_AE_THR), 0); */ 611 } 612#endif /* YUKON */ 613 614} /* SkGeInitMacFifo */ 615 616#ifdef SK_LNK_SYNC_CNT 617/****************************************************************************** 618 * 619 * SkGeLoadLnkSyncCnt() - Load the Link Sync Counter and starts counting 620 * 621 * Description: 622 * This function starts the Link Sync Counter of the specified 623 * port and enables the generation of an Link Sync IRQ. 624 * The Link Sync Counter may be used to detect an active link, 625 * if autonegotiation is not used. 626 * 627 * Note: 628 * o To ensure receiving the Link Sync Event the LinkSyncCounter 629 * should be initialized BEFORE clearing the XMAC's reset! 630 * o Enable IS_LNK_SYNC_M1 and IS_LNK_SYNC_M2 after calling this 631 * function. 632 * 633 * Returns: 634 * nothing 635 */ 636void SkGeLoadLnkSyncCnt( 637SK_AC *pAC, /* adapter context */ 638SK_IOC IoC, /* IO context */ 639int Port, /* Port Index (MAC_1 + n) */ 640SK_U32 CntVal) /* Counter value */ 641{ 642 SK_U32 OrgIMsk; 643 SK_U32 NewIMsk; 644 SK_U32 ISrc; 645 SK_BOOL IrqPend; 646 647 /* stop counter */ 648 SK_OUT8(IoC, MR_ADDR(Port, LNK_SYNC_CTRL), LED_STOP); 649 650 IrqPend = SK_FALSE; 651 SK_IN32(IoC, B0_ISRC, &ISrc); 652 SK_IN32(IoC, B0_IMSK, &OrgIMsk); 653 if (Port == MAC_1) { 654 NewIMsk = OrgIMsk & ~IS_LNK_SYNC_M1; 655 if ((ISrc & IS_LNK_SYNC_M1) != 0) { 656 IrqPend = SK_TRUE; 657 } 658 } 659 else { 660 NewIMsk = OrgIMsk & ~IS_LNK_SYNC_M2; 661 if ((ISrc & IS_LNK_SYNC_M2) != 0) { 662 IrqPend = SK_TRUE; 663 } 664 } 665 if (!IrqPend) { 666 SK_OUT32(IoC, B0_IMSK, NewIMsk); 667 } 668 669 /* load counter */ 670 SK_OUT32(IoC, MR_ADDR(Port, LNK_SYNC_INI), CntVal); 671 672 /* start counter */ 673 SK_OUT8(IoC, MR_ADDR(Port, LNK_SYNC_CTRL), LED_START); 674 675 if (!IrqPend) { 676 /* clear the unexpected IRQ, and restore the interrupt mask */ 677 SK_OUT8(IoC, MR_ADDR(Port, LNK_SYNC_CTRL), LED_CLR_IRQ); 678 SK_OUT32(IoC, B0_IMSK, OrgIMsk); 679 } 680} /* SkGeLoadLnkSyncCnt*/ 681#endif /* SK_LNK_SYNC_CNT */ 682 683#if defined(SK_DIAG) || defined(SK_CFG_SYNC) 684/****************************************************************************** 685 * 686 * SkGeCfgSync() - Configure synchronous bandwidth for this port. 687 * 688 * Description: 689 * This function may be used to configure synchronous bandwidth 690 * to the specified port. This may be done any time after 691 * initializing the port. The configuration values are NOT saved 692 * in the HWAC port structure and will be overwritten any 693 * time when stopping and starting the port. 694 * Any values for the synchronous configuration will be ignored 695 * if the size of the synchronous queue is zero! 696 * 697 * The default configuration for the synchronous service is 698 * TXA_ENA_FSYNC. This means if the size of 699 * the synchronous queue is unequal zero but no specific 700 * synchronous bandwidth is configured, the synchronous queue 701 * will always have the 'unlimited' transmit priority! 702 * 703 * This mode will be restored if the synchronous bandwidth is 704 * deallocated ('IntTime' = 0 and 'LimCount' = 0). 705 * 706 * Returns: 707 * 0: success 708 * 1: parameter configuration error 709 * 2: try to configure quality of service although no 710 * synchronous queue is configured 711 */ 712int SkGeCfgSync( 713SK_AC *pAC, /* adapter context */ 714SK_IOC IoC, /* IO context */ 715int Port, /* Port Index (MAC_1 + n) */ 716SK_U32 IntTime, /* Interval Timer Value in units of 8ns */ 717SK_U32 LimCount, /* Number of bytes to transfer during IntTime */ 718int SyncMode) /* Sync Mode: TXA_ENA_ALLOC | TXA_DIS_ALLOC | 0 */ 719{ 720 int Rtv; 721 722 Rtv = 0; 723 724 /* check the parameters */ 725 if (LimCount > IntTime || 726 (LimCount == 0 && IntTime != 0) || 727 (LimCount != 0 && IntTime == 0)) { 728 729 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E010, SKERR_HWI_E010MSG); 730 return(1); 731 } 732 733 if (pAC->GIni.GP[Port].PXSQSize == 0) { 734 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E009, SKERR_HWI_E009MSG); 735 return(2); 736 } 737 738 /* calculate register values */ 739 IntTime = (IntTime / 2) * pAC->GIni.GIHstClkFact / 100; 740 LimCount = LimCount / 8; 741 742 if (IntTime > TXA_MAX_VAL || LimCount > TXA_MAX_VAL) { 743 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E010, SKERR_HWI_E010MSG); 744 return(1); 745 } 746 747 /* 748 * - Enable 'Force Sync' to ensure the synchronous queue 749 * has the priority while configuring the new values. 750 * - Also 'disable alloc' to ensure the settings complies 751 * to the SyncMode parameter. 752 * - Disable 'Rate Control' to configure the new values. 753 * - write IntTime and LimCount 754 * - start 'Rate Control' and disable 'Force Sync' 755 * if Interval Timer or Limit Counter not zero. 756 */ 757 SK_OUT8(IoC, MR_ADDR(Port, TXA_CTRL), 758 TXA_ENA_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC); 759 760 SK_OUT32(IoC, MR_ADDR(Port, TXA_ITI_INI), IntTime); 761 SK_OUT32(IoC, MR_ADDR(Port, TXA_LIM_INI), LimCount); 762 763 SK_OUT8(IoC, MR_ADDR(Port, TXA_CTRL), 764 (SK_U8)(SyncMode & (TXA_ENA_ALLOC | TXA_DIS_ALLOC))); 765 766 if (IntTime != 0 || LimCount != 0) { 767 SK_OUT8(IoC, MR_ADDR(Port, TXA_CTRL), TXA_DIS_FSYNC | TXA_START_RC); 768 } 769 770 return(0); 771} /* SkGeCfgSync */ 772#endif /* SK_DIAG || SK_CFG_SYNC*/ 773 774 775/****************************************************************************** 776 * 777 * DoInitRamQueue() - Initialize the RAM Buffer Address of a single Queue 778 * 779 * Desccription: 780 * If the queue is used, enable and initialize it. 781 * Make sure the queue is still reset, if it is not used. 782 * 783 * Returns: 784 * nothing 785 */ 786static void DoInitRamQueue( 787SK_AC *pAC, /* adapter context */ 788SK_IOC IoC, /* IO context */ 789int QuIoOffs, /* Queue IO Address Offset */ 790SK_U32 QuStartAddr, /* Queue Start Address */ 791SK_U32 QuEndAddr, /* Queue End Address */ 792int QuType) /* Queue Type (SK_RX_SRAM_Q|SK_RX_BRAM_Q|SK_TX_RAM_Q) */ 793{ 794 SK_U32 RxUpThresVal; 795 SK_U32 RxLoThresVal; 796 797 if (QuStartAddr != QuEndAddr) { 798 /* calculate thresholds, assume we have a big Rx queue */ 799 RxUpThresVal = (QuEndAddr + 1 - QuStartAddr - SK_RB_ULPP) / 8; 800 RxLoThresVal = (QuEndAddr + 1 - QuStartAddr - SK_RB_LLPP_B)/8; 801 802 /* build HW address format */ 803 QuStartAddr = QuStartAddr / 8; 804 QuEndAddr = QuEndAddr / 8; 805 806 /* release local reset */ 807 SK_OUT8(IoC, RB_ADDR(QuIoOffs, RB_CTRL), RB_RST_CLR); 808 809 /* configure addresses */ 810 SK_OUT32(IoC, RB_ADDR(QuIoOffs, RB_START), QuStartAddr); 811 SK_OUT32(IoC, RB_ADDR(QuIoOffs, RB_END), QuEndAddr); 812 SK_OUT32(IoC, RB_ADDR(QuIoOffs, RB_WP), QuStartAddr); 813 SK_OUT32(IoC, RB_ADDR(QuIoOffs, RB_RP), QuStartAddr); 814 815 switch (QuType) { 816 case SK_RX_SRAM_Q: 817 /* configure threshold for small Rx Queue */ 818 RxLoThresVal += (SK_RB_LLPP_B - SK_RB_LLPP_S) / 8; 819 820 /* continue with SK_RX_BRAM_Q */ 821 case SK_RX_BRAM_Q: 822 /* write threshold for Rx Queue */ 823 824 SK_OUT32(IoC, RB_ADDR(QuIoOffs, RB_RX_UTPP), RxUpThresVal); 825 SK_OUT32(IoC, RB_ADDR(QuIoOffs, RB_RX_LTPP), RxLoThresVal); 826 827 /* the high priority threshold not used */ 828 break; 829 case SK_TX_RAM_Q: 830 /* 831 * Do NOT use Store & Forward under normal operation due to 832 * performance optimization (GENESIS only). 833 * But if Jumbo Frames are configured (XMAC Tx FIFO is only 4 kB) 834 * or YUKON is used ((GMAC Tx FIFO is only 1 kB) 835 * we NEED Store & Forward of the RAM buffer. 836 */ 837 if (pAC->GIni.GIPortUsage == SK_JUMBO_LINK || 838 pAC->GIni.GIYukon) { 839 /* enable Store & Forward Mode for the Tx Side */ 840 SK_OUT8(IoC, RB_ADDR(QuIoOffs, RB_CTRL), RB_ENA_STFWD); 841 } 842 break; 843 } 844 845 /* set queue operational */ 846 SK_OUT8(IoC, RB_ADDR(QuIoOffs, RB_CTRL), RB_ENA_OP_MD); 847 } 848 else { 849 /* ensure the queue is still disabled */ 850 SK_OUT8(IoC, RB_ADDR(QuIoOffs, RB_CTRL), RB_RST_SET); 851 } 852} /* DoInitRamQueue */ 853 854 855/****************************************************************************** 856 * 857 * SkGeInitRamBufs() - Initialize the RAM Buffer Queues 858 * 859 * Description: 860 * Initialize all RAM Buffer Queues of the specified port 861 * 862 * Returns: 863 * nothing 864 */ 865static void SkGeInitRamBufs( 866SK_AC *pAC, /* adapter context */ 867SK_IOC IoC, /* IO context */ 868int Port) /* Port Index (MAC_1 + n) */ 869{ 870 SK_GEPORT *pPrt; 871 int RxQType; 872 873 pPrt = &pAC->GIni.GP[Port]; 874 875 if (pPrt->PRxQSize == SK_MIN_RXQ_SIZE) { 876 RxQType = SK_RX_SRAM_Q; /* small Rx Queue */ 877 } 878 else { 879 RxQType = SK_RX_BRAM_Q; /* big Rx Queue */ 880 } 881 882 DoInitRamQueue(pAC, IoC, pPrt->PRxQOff, pPrt->PRxQRamStart, 883 pPrt->PRxQRamEnd, RxQType); 884 885 DoInitRamQueue(pAC, IoC, pPrt->PXsQOff, pPrt->PXsQRamStart, 886 pPrt->PXsQRamEnd, SK_TX_RAM_Q); 887 888 DoInitRamQueue(pAC, IoC, pPrt->PXaQOff, pPrt->PXaQRamStart, 889 pPrt->PXaQRamEnd, SK_TX_RAM_Q); 890 891} /* SkGeInitRamBufs */ 892 893 894/****************************************************************************** 895 * 896 * SkGeInitRamIface() - Initialize the RAM Interface 897 * 898 * Description: 899 * This function initializes the Adapters RAM Interface. 900 * 901 * Note: 902 * This function is used in the diagnostics. 903 * 904 * Returns: 905 * nothing 906 */ 907static void SkGeInitRamIface( 908SK_AC *pAC, /* adapter context */ 909SK_IOC IoC) /* IO context */ 910{ 911 /* release local reset */ 912 SK_OUT16(IoC, B3_RI_CTRL, RI_RST_CLR); 913 914 /* configure timeout values */ 915 SK_OUT8(IoC, B3_RI_WTO_R1, SK_RI_TO_53); 916 SK_OUT8(IoC, B3_RI_WTO_XA1, SK_RI_TO_53); 917 SK_OUT8(IoC, B3_RI_WTO_XS1, SK_RI_TO_53); 918 SK_OUT8(IoC, B3_RI_RTO_R1, SK_RI_TO_53); 919 SK_OUT8(IoC, B3_RI_RTO_XA1, SK_RI_TO_53); 920 SK_OUT8(IoC, B3_RI_RTO_XS1, SK_RI_TO_53); 921 SK_OUT8(IoC, B3_RI_WTO_R2, SK_RI_TO_53); 922 SK_OUT8(IoC, B3_RI_WTO_XA2, SK_RI_TO_53); 923 SK_OUT8(IoC, B3_RI_WTO_XS2, SK_RI_TO_53); 924 SK_OUT8(IoC, B3_RI_RTO_R2, SK_RI_TO_53); 925 SK_OUT8(IoC, B3_RI_RTO_XA2, SK_RI_TO_53); 926 SK_OUT8(IoC, B3_RI_RTO_XS2, SK_RI_TO_53); 927 928} /* SkGeInitRamIface */ 929 930 931/****************************************************************************** 932 * 933 * SkGeInitBmu() - Initialize the BMU state machines 934 * 935 * Description: 936 * Initialize all BMU state machines of the specified port 937 * 938 * Returns: 939 * nothing 940 */ 941static void SkGeInitBmu( 942SK_AC *pAC, /* adapter context */ 943SK_IOC IoC, /* IO context */ 944int Port) /* Port Index (MAC_1 + n) */ 945{ 946 SK_GEPORT *pPrt; 947 SK_U32 RxWm; 948 SK_U32 TxWm; 949 950 pPrt = &pAC->GIni.GP[Port]; 951 952 RxWm = SK_BMU_RX_WM; 953 TxWm = SK_BMU_TX_WM; 954 955 if (!pAC->GIni.GIPciSlot64 && !pAC->GIni.GIPciClock66) { 956 /* for better performance */ 957 RxWm /= 2; 958 TxWm /= 2; 959 } 960 961 /* Rx Queue: Release all local resets and set the watermark */ 962 SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_CSR), CSR_CLR_RESET); 963 SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_F), RxWm); 964 965 /* 966 * Tx Queue: Release all local resets if the queue is used ! 967 * set watermark 968 */ 969 if (pPrt->PXSQSize != 0) { 970 SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), CSR_CLR_RESET); 971 SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_F), TxWm); 972 } 973 974 if (pPrt->PXAQSize != 0) { 975 SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), CSR_CLR_RESET); 976 SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_F), TxWm); 977 } 978 /* 979 * Do NOT enable the descriptor poll timers here, because 980 * the descriptor addresses are not specified yet. 981 */ 982} /* SkGeInitBmu */ 983 984 985/****************************************************************************** 986 * 987 * TestStopBit() - Test the stop bit of the queue 988 * 989 * Description: 990 * Stopping a queue is not as simple as it seems to be. 991 * If descriptor polling is enabled, it may happen 992 * that RX/TX stop is done and SV idle is NOT set. 993 * In this case we have to issue another stop command. 994 * 995 * Returns: 996 * The queues control status register 997 */ 998static SK_U32 TestStopBit( 999SK_AC *pAC, /* Adapter Context */ 1000SK_IOC IoC, /* IO Context */ 1001int QuIoOffs) /* Queue IO Address Offset */ 1002{ 1003 SK_U32 QuCsr; /* CSR contents */ 1004 1005 SK_IN32(IoC, Q_ADDR(QuIoOffs, Q_CSR), &QuCsr); 1006 1007 if ((QuCsr & (CSR_STOP | CSR_SV_IDLE)) == 0) { 1008 /* Stop Descriptor overridden by start command */ 1009 SK_OUT32(IoC, Q_ADDR(QuIoOffs, Q_CSR), CSR_STOP); 1010 1011 SK_IN32(IoC, Q_ADDR(QuIoOffs, Q_CSR), &QuCsr); 1012 } 1013 1014 return(QuCsr); 1015} /* TestStopBit */ 1016 1017 1018void SkGeStopPort( 1019SK_AC *pAC, /* adapter context */ 1020SK_IOC IoC, /* I/O context */ 1021int Port, /* port to stop (MAC_1 + n) */ 1022int Dir, /* Direction to Stop (SK_STOP_RX, SK_STOP_TX, SK_STOP_ALL) */ 1023int RstMode)/* Reset Mode (SK_SOFT_RST, SK_HARD_RST) */ 1024{ 1025#ifndef SK_DIAG 1026 SK_EVPARA Para; 1027#endif /* !SK_DIAG */ 1028 SK_GEPORT *pPrt; 1029 SK_U32 DWord; 1030 SK_U32 XsCsr; 1031 SK_U32 XaCsr; 1032 SK_U64 ToutStart; 1033 int i; 1034 int ToutCnt; 1035 1036 pPrt = &pAC->GIni.GP[Port]; 1037 1038 if ((Dir & SK_STOP_TX) != 0) { 1039 /* disable receiver and transmitter */ 1040 SkMacRxTxDisable(pAC, IoC, Port); 1041 1042 /* stop both transmit queues */ 1043 /* 1044 * If the BMU is in the reset state CSR_STOP will terminate 1045 * immediately. 1046 */ 1047 SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), CSR_STOP); 1048 SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), CSR_STOP); 1049 1050 ToutStart = SkOsGetTime(pAC); 1051 ToutCnt = 0; 1052 do { 1053 /* 1054 * Clear packet arbiter timeout to make sure 1055 * this loop will terminate. 1056 */ 1057 SK_OUT16(IoC, B3_PA_CTRL, (SK_U16)((Port == MAC_1) ? 1058 PA_CLR_TO_TX1 : PA_CLR_TO_TX2)); 1059 1060 /* 1061 * If the transfer stucks at the MAC the STOP command will not 1062 * terminate if we don't flush the XMAC's transmit FIFO ! 1063 */ 1064 SkMacFlushTxFifo(pAC, IoC, Port); 1065 1066 XsCsr = TestStopBit(pAC, IoC, pPrt->PXsQOff); 1067 XaCsr = TestStopBit(pAC, IoC, pPrt->PXaQOff); 1068 1069 if (SkOsGetTime(pAC) - ToutStart > (SK_TICKS_PER_SEC / 18)) { 1070 /* 1071 * Timeout of 1/18 second reached. 1072 * This needs to be checked at 1/18 sec only. 1073 */ 1074 ToutCnt++; 1075 if (ToutCnt > 1) { 1076 1077 /* Fatal Error, Loop aborted */ 1078 SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_HWI_E018, 1079 SKERR_HWI_E018MSG); 1080#ifndef SK_DIAG 1081 Para.Para64 = Port; 1082 SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_FAIL, Para); 1083#endif /* !SK_DIAG */ 1084 return; 1085 } 1086 ToutStart = SkOsGetTime(pAC); 1087 1088 if ((XsCsr & CSR_STOP) != 0) { 1089 SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), CSR_START); 1090 } 1091 if ((XaCsr & CSR_STOP) != 0) { 1092 SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), CSR_START); 1093 } 1094 } 1095 1096 /* 1097 * Because of the ASIC problem report entry from 21.08.1998 it is 1098 * required to wait until CSR_STOP is reset and CSR_SV_IDLE is set. 1099 */ 1100 } while ((XsCsr & (CSR_STOP | CSR_SV_IDLE)) != CSR_SV_IDLE || 1101 (XaCsr & (CSR_STOP | CSR_SV_IDLE)) != CSR_SV_IDLE); 1102 1103 /* Reset the MAC depending on the RstMode */ 1104 if (RstMode == SK_SOFT_RST) { 1105 SkMacSoftRst(pAC, IoC, Port); 1106 } 1107 else { 1108 SkMacHardRst(pAC, IoC, Port); 1109 } 1110 1111 /* Disable Force Sync bit and Enable Alloc bit */ 1112 SK_OUT8(IoC, MR_ADDR(Port, TXA_CTRL), 1113 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC); 1114 1115 /* Stop Interval Timer and Limit Counter of Tx Arbiter */ 1116 SK_OUT32(IoC, MR_ADDR(Port, TXA_ITI_INI), 0L); 1117 SK_OUT32(IoC, MR_ADDR(Port, TXA_LIM_INI), 0L); 1118 1119 /* Perform a local reset of the port's Tx path */ 1120 1121 /* Reset the PCI FIFO of the async Tx queue */ 1122 SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), CSR_SET_RESET); 1123 /* Reset the PCI FIFO of the sync Tx queue */ 1124 SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), CSR_SET_RESET); 1125 /* Reset the RAM Buffer async Tx queue */ 1126 SK_OUT8(IoC, RB_ADDR(pPrt->PXaQOff, RB_CTRL), RB_RST_SET); 1127 /* Reset the RAM Buffer sync Tx queue */ 1128 SK_OUT8(IoC, RB_ADDR(pPrt->PXsQOff, RB_CTRL), RB_RST_SET); 1129 1130 /* Reset Tx MAC FIFO */ 1131#ifdef GENESIS 1132 if (pAC->GIni.GIGenesis) { 1133 /* Note: MFF_RST_SET does NOT reset the XMAC ! */ 1134 SK_OUT8(IoC, MR_ADDR(Port, TX_MFF_CTRL2), MFF_RST_SET); 1135 1136 /* switch Link and Tx LED off, stop the LED counters */ 1137 /* Link LED is switched off by the RLMT and the Diag itself */ 1138 SkGeXmitLED(pAC, IoC, MR_ADDR(Port, TX_LED_INI), SK_LED_DIS); 1139 } 1140#endif /* GENESIS */ 1141 1142#ifdef YUKON 1143 if (pAC->GIni.GIYukon) { 1144 /* Reset TX MAC FIFO */ 1145 SK_OUT8(IoC, MR_ADDR(Port, TX_GMF_CTRL_T), (SK_U8)GMF_RST_SET); 1146 } 1147#endif /* YUKON */ 1148 } 1149 1150 if ((Dir & SK_STOP_RX) != 0) { 1151 /* 1152 * The RX Stop Command will not terminate if no buffers 1153 * are queued in the RxD ring. But it will always reach 1154 * the Idle state. Therefore we can use this feature to 1155 * stop the transfer of received packets. 1156 */ 1157 /* stop the port's receive queue */ 1158 SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_CSR), CSR_STOP); 1159 1160 i = 100; 1161 do { 1162 /* 1163 * Clear packet arbiter timeout to make sure 1164 * this loop will terminate 1165 */ 1166 SK_OUT16(IoC, B3_PA_CTRL, (SK_U16)((Port == MAC_1) ? 1167 PA_CLR_TO_RX1 : PA_CLR_TO_RX2)); 1168 1169 DWord = TestStopBit(pAC, IoC, pPrt->PRxQOff); 1170 1171 /* timeout if i==0 (bug fix for #10748) */ 1172 if (--i == 0) { 1173 SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_HWI_E024, 1174 SKERR_HWI_E024MSG); 1175 break; 1176 } 1177 /* 1178 * because of the ASIC problem report entry from 21.08.98 1179 * it is required to wait until CSR_STOP is reset and 1180 * CSR_SV_IDLE is set. 1181 */ 1182 } while ((DWord & (CSR_STOP | CSR_SV_IDLE)) != CSR_SV_IDLE); 1183 1184 /* The path data transfer activity is fully stopped now */ 1185 1186 /* Perform a local reset of the port's Rx path */ 1187 1188 /* Reset the PCI FIFO of the Rx queue */ 1189 SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_CSR), CSR_SET_RESET); 1190 /* Reset the RAM Buffer receive queue */ 1191 SK_OUT8(IoC, RB_ADDR(pPrt->PRxQOff, RB_CTRL), RB_RST_SET); 1192 1193 /* Reset Rx MAC FIFO */ 1194#ifdef GENESIS 1195 if (pAC->GIni.GIGenesis) { 1196 1197 SK_OUT8(IoC, MR_ADDR(Port, RX_MFF_CTRL2), MFF_RST_SET); 1198 1199 /* switch Rx LED off, stop the LED counter */ 1200 SkGeXmitLED(pAC, IoC, MR_ADDR(Port, RX_LED_INI), SK_LED_DIS); 1201 } 1202#endif /* GENESIS */ 1203 1204#ifdef YUKON 1205 if (pAC->GIni.GIYukon) { 1206 /* Reset Rx MAC FIFO */ 1207 SK_OUT8(IoC, MR_ADDR(Port, RX_GMF_CTRL_T), (SK_U8)GMF_RST_SET); 1208 } 1209#endif /* YUKON */ 1210 } 1211} /* SkGeStopPort */ 1212 1213 1214/****************************************************************************** 1215 * 1216 * SkGeInit0() - Level 0 Initialization 1217 * 1218 * Description: 1219 * - Initialize the BMU address offsets 1220 * 1221 * Returns: 1222 * nothing 1223 */ 1224static void SkGeInit0( 1225SK_AC *pAC, /* adapter context */ 1226SK_IOC IoC) /* IO context */ 1227{ 1228 int i; 1229 SK_GEPORT *pPrt; 1230 1231 for (i = 0; i < SK_MAX_MACS; i++) { 1232 pPrt = &pAC->GIni.GP[i]; 1233 1234 pPrt->PState = SK_PRT_RESET; 1235 pPrt->PRxQOff = QOffTab[i].RxQOff; 1236 pPrt->PXsQOff = QOffTab[i].XsQOff; 1237 pPrt->PXaQOff = QOffTab[i].XaQOff; 1238 pPrt->PCheckPar = SK_FALSE; 1239 pPrt->PIsave = 0; 1240 pPrt->PPrevShorts = 0; 1241 pPrt->PLinkResCt = 0; 1242 pPrt->PAutoNegTOCt = 0; 1243 pPrt->PPrevRx = 0; 1244 pPrt->PPrevFcs = 0; 1245 pPrt->PRxLim = SK_DEF_RX_WA_LIM; 1246 pPrt->PLinkMode = (SK_U8)SK_LMODE_AUTOFULL; 1247 pPrt->PLinkSpeedCap = (SK_U8)SK_LSPEED_CAP_1000MBPS; 1248 pPrt->PLinkSpeed = (SK_U8)SK_LSPEED_1000MBPS; 1249 pPrt->PLinkSpeedUsed = (SK_U8)SK_LSPEED_STAT_UNKNOWN; 1250 pPrt->PLinkModeConf = (SK_U8)SK_LMODE_AUTOSENSE; 1251 pPrt->PFlowCtrlMode = (SK_U8)SK_FLOW_MODE_SYM_OR_REM; 1252 pPrt->PLinkCap = (SK_U8)(SK_LMODE_CAP_HALF | SK_LMODE_CAP_FULL | 1253 SK_LMODE_CAP_AUTOHALF | SK_LMODE_CAP_AUTOFULL); 1254 pPrt->PLinkModeStatus = (SK_U8)SK_LMODE_STAT_UNKNOWN; 1255 pPrt->PFlowCtrlCap = (SK_U8)SK_FLOW_MODE_SYM_OR_REM; 1256 pPrt->PFlowCtrlStatus = (SK_U8)SK_FLOW_STAT_NONE; 1257 pPrt->PMSCap = 0; 1258 pPrt->PMSMode = (SK_U8)SK_MS_MODE_AUTO; 1259 pPrt->PMSStatus = (SK_U8)SK_MS_STAT_UNSET; 1260 pPrt->PLipaAutoNeg = (SK_U8)SK_LIPA_UNKNOWN; 1261 pPrt->PAutoNegFail = SK_FALSE; 1262 pPrt->PHWLinkUp = SK_FALSE; 1263 pPrt->PLinkBroken = SK_TRUE; /* See WA code */ 1264 pPrt->PPhyPowerState = PHY_PM_OPERATIONAL_MODE; 1265 pPrt->PMacColThres = TX_COL_DEF; 1266 pPrt->PMacJamLen = TX_JAM_LEN_DEF; 1267 pPrt->PMacJamIpgVal = TX_JAM_IPG_DEF; 1268 pPrt->PMacJamIpgData = TX_IPG_JAM_DEF; 1269 pPrt->PMacIpgData = IPG_DATA_DEF; 1270 pPrt->PMacLimit4 = SK_FALSE; 1271 } 1272 1273 pAC->GIni.GIPortUsage = SK_RED_LINK; 1274 pAC->GIni.GILedBlinkCtrl = (SK_U16)OemConfig.Value; 1275 pAC->GIni.GIValIrqMask = IS_ALL_MSK; 1276 1277} /* SkGeInit0*/ 1278 1279 1280/****************************************************************************** 1281 * 1282 * SkGeInit1() - Level 1 Initialization 1283 * 1284 * Description: 1285 * o Do a software reset. 1286 * o Clear all reset bits. 1287 * o Verify that the detected hardware is present. 1288 * Return an error if not. 1289 * o Get the hardware configuration 1290 * + Read the number of MACs/Ports. 1291 * + Read the RAM size. 1292 * + Read the PCI Revision Id. 1293 * + Find out the adapters host clock speed 1294 * + Read and check the PHY type 1295 * 1296 * Returns: 1297 * 0: success 1298 * 5: Unexpected PHY type detected 1299 * 6: HW self test failed 1300 */ 1301static int SkGeInit1( 1302SK_AC *pAC, /* adapter context */ 1303SK_IOC IoC) /* IO context */ 1304{ 1305 SK_U8 Byte; 1306 SK_U16 Word; 1307 SK_U16 CtrlStat; 1308 SK_U32 DWord; 1309 int RetVal; 1310 int i; 1311 1312 RetVal = 0; 1313 1314 /* save CLK_RUN bits (YUKON-Lite) */ 1315 SK_IN16(IoC, B0_CTST, &CtrlStat); 1316 1317 /* do the SW-reset */ 1318 SK_OUT8(IoC, B0_CTST, CS_RST_SET); 1319 1320 /* release the SW-reset */ 1321 SK_OUT8(IoC, B0_CTST, CS_RST_CLR); 1322 1323 /* reset all error bits in the PCI STATUS register */ 1324 /* 1325 * Note: PCI Cfg cycles cannot be used, because they are not 1326 * available on some platforms after 'boot time'. 1327 */ 1328 SK_IN16(IoC, PCI_C(PCI_STATUS), &Word); 1329 1330 SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_ON); 1331 SK_OUT16(IoC, PCI_C(PCI_STATUS), (SK_U16)(Word | PCI_ERRBITS)); 1332 SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 1333 1334 /* release Master Reset */ 1335 SK_OUT8(IoC, B0_CTST, CS_MRST_CLR); 1336 1337#ifdef CLK_RUN 1338 CtrlStat |= CS_CLK_RUN_ENA; 1339#endif /* CLK_RUN */ 1340 1341 /* restore CLK_RUN bits */ 1342 SK_OUT16(IoC, B0_CTST, (SK_U16)(CtrlStat & 1343 (CS_CLK_RUN_HOT | CS_CLK_RUN_RST | CS_CLK_RUN_ENA))); 1344 1345 /* read Chip Identification Number */ 1346 SK_IN8(IoC, B2_CHIP_ID, &Byte); 1347 pAC->GIni.GIChipId = Byte; 1348 1349 /* read number of MACs */ 1350 SK_IN8(IoC, B2_MAC_CFG, &Byte); 1351 pAC->GIni.GIMacsFound = (Byte & CFG_SNG_MAC) ? 1 : 2; 1352 1353 /* get Chip Revision Number */ 1354 pAC->GIni.GIChipRev = (SK_U8)((Byte & CFG_CHIP_R_MSK) >> 4); 1355 1356 /* get diff. PCI parameters */ 1357 SK_IN16(IoC, B0_CTST, &CtrlStat); 1358 1359 /* read the adapters RAM size */ 1360 SK_IN8(IoC, B2_E_0, &Byte); 1361 1362 pAC->GIni.GIGenesis = SK_FALSE; 1363 pAC->GIni.GIYukon = SK_FALSE; 1364 pAC->GIni.GIYukonLite = SK_FALSE; 1365 1366#ifdef GENESIS 1367 if (pAC->GIni.GIChipId == CHIP_ID_GENESIS) { 1368 1369 pAC->GIni.GIGenesis = SK_TRUE; 1370 1371 if (Byte == (SK_U8)3) { 1372 /* special case: 4 x 64k x 36, offset = 0x80000 */ 1373 pAC->GIni.GIRamSize = 1024; 1374 pAC->GIni.GIRamOffs = (SK_U32)512 * 1024; 1375 } 1376 else { 1377 pAC->GIni.GIRamSize = (int)Byte * 512; 1378 pAC->GIni.GIRamOffs = 0; 1379 } 1380 /* all GE adapters work with 53.125 MHz host clock */ 1381 pAC->GIni.GIHstClkFact = SK_FACT_53; 1382 1383 /* set Descr. Poll Timer Init Value to 250 ms */ 1384 pAC->GIni.GIPollTimerVal = 1385 SK_DPOLL_DEF * (SK_U32)pAC->GIni.GIHstClkFact / 100; 1386 } 1387#endif /* GENESIS */ 1388 1389#ifdef YUKON 1390 if (pAC->GIni.GIChipId != CHIP_ID_GENESIS) { 1391 1392 pAC->GIni.GIYukon = SK_TRUE; 1393 1394 pAC->GIni.GIRamSize = (Byte == (SK_U8)0) ? 128 : (int)Byte * 4; 1395 1396 pAC->GIni.GIRamOffs = 0; 1397 1398 /* WA for chip Rev. A */ 1399 pAC->GIni.GIWolOffs = (pAC->GIni.GIChipId == CHIP_ID_YUKON && 1400 pAC->GIni.GIChipRev == 0) ? WOL_REG_OFFS : 0; 1401 1402 /* get PM Capabilities of PCI config space */ 1403 SK_IN16(IoC, PCI_C(PCI_PM_CAP_REG), &Word); 1404 1405 /* check if VAUX is available */ 1406 if (((CtrlStat & CS_VAUX_AVAIL) != 0) && 1407 /* check also if PME from D3cold is set */ 1408 ((Word & PCI_PME_D3C_SUP) != 0)) { 1409 /* set entry in GE init struct */ 1410 pAC->GIni.GIVauxAvail = SK_TRUE; 1411 } 1412 1413 if (pAC->GIni.GIChipId == CHIP_ID_YUKON_LITE) { 1414 /* this is Rev. A1 */ 1415 pAC->GIni.GIYukonLite = SK_TRUE; 1416 } 1417 else { 1418 /* save Flash-Address Register */ 1419 SK_IN32(IoC, B2_FAR, &DWord); 1420 1421 /* test Flash-Address Register */ 1422 SK_OUT8(IoC, B2_FAR + 3, 0xff); 1423 SK_IN8(IoC, B2_FAR + 3, &Byte); 1424 1425 if (Byte != 0) { 1426 /* this is Rev. A0 */ 1427 pAC->GIni.GIYukonLite = SK_TRUE; 1428 1429 /* restore Flash-Address Register */ 1430 SK_OUT32(IoC, B2_FAR, DWord); 1431 } 1432 } 1433 1434 /* switch power to VCC (WA for VAUX problem) */ 1435 SK_OUT8(IoC, B0_POWER_CTRL, (SK_U8)(PC_VAUX_ENA | PC_VCC_ENA | 1436 PC_VAUX_OFF | PC_VCC_ON)); 1437 1438 /* read the Interrupt source */ 1439 SK_IN32(IoC, B0_ISRC, &DWord); 1440 1441 if ((DWord & IS_HW_ERR) != 0) { 1442 /* read the HW Error Interrupt source */ 1443 SK_IN32(IoC, B0_HWE_ISRC, &DWord); 1444 1445 if ((DWord & IS_IRQ_SENSOR) != 0) { 1446 /* disable HW Error IRQ */ 1447 pAC->GIni.GIValIrqMask &= ~IS_HW_ERR; 1448 } 1449 } 1450 1451 for (i = 0; i < pAC->GIni.GIMacsFound; i++) { 1452 /* set GMAC Link Control reset */ 1453 SK_OUT16(IoC, MR_ADDR(i, GMAC_LINK_CTRL), GMLC_RST_SET); 1454 1455 /* clear GMAC Link Control reset */ 1456 SK_OUT16(IoC, MR_ADDR(i, GMAC_LINK_CTRL), GMLC_RST_CLR); 1457 } 1458 /* all YU chips work with 78.125 MHz host clock */ 1459 pAC->GIni.GIHstClkFact = SK_FACT_78; 1460 1461 pAC->GIni.GIPollTimerVal = SK_DPOLL_MAX; /* 215 ms */ 1462 } 1463#endif /* YUKON */ 1464 1465 /* check if 64-bit PCI Slot is present */ 1466 pAC->GIni.GIPciSlot64 = (SK_BOOL)((CtrlStat & CS_BUS_SLOT_SZ) != 0); 1467 1468 /* check if 66 MHz PCI Clock is active */ 1469 pAC->GIni.GIPciClock66 = (SK_BOOL)((CtrlStat & CS_BUS_CLOCK) != 0); 1470 1471 /* read PCI HW Revision Id. */ 1472 SK_IN8(IoC, PCI_C(PCI_REV_ID), &Byte); 1473 pAC->GIni.GIPciHwRev = Byte; 1474 1475 /* read the PMD type */ 1476 SK_IN8(IoC, B2_PMD_TYP, &Byte); 1477 pAC->GIni.GICopperType = (SK_U8)(Byte == 'T'); 1478 1479 /* read the PHY type */ 1480 SK_IN8(IoC, B2_E_1, &Byte); 1481 1482 Byte &= 0x0f; /* the PHY type is stored in the lower nibble */ 1483 for (i = 0; i < pAC->GIni.GIMacsFound; i++) { 1484 1485#ifdef GENESIS 1486 if (pAC->GIni.GIGenesis) { 1487 switch (Byte) { 1488 case SK_PHY_XMAC: 1489 pAC->GIni.GP[i].PhyAddr = PHY_ADDR_XMAC; 1490 break; 1491 case SK_PHY_BCOM: 1492 pAC->GIni.GP[i].PhyAddr = PHY_ADDR_BCOM; 1493 pAC->GIni.GP[i].PMSCap = (SK_U8)(SK_MS_CAP_AUTO | 1494 SK_MS_CAP_MASTER | SK_MS_CAP_SLAVE); 1495 break; 1496#ifdef OTHER_PHY 1497 case SK_PHY_LONE: 1498 pAC->GIni.GP[i].PhyAddr = PHY_ADDR_LONE; 1499 break; 1500 case SK_PHY_NAT: 1501 pAC->GIni.GP[i].PhyAddr = PHY_ADDR_NAT; 1502 break; 1503#endif /* OTHER_PHY */ 1504 default: 1505 /* ERROR: unexpected PHY type detected */ 1506 RetVal = 5; 1507 break; 1508 } 1509 } 1510#endif /* GENESIS */ 1511 1512#ifdef YUKON 1513 if (pAC->GIni.GIYukon) { 1514 1515 if (Byte < (SK_U8)SK_PHY_MARV_COPPER) { 1516 /* if this field is not initialized */ 1517 Byte = (SK_U8)SK_PHY_MARV_COPPER; 1518 1519 pAC->GIni.GICopperType = SK_TRUE; 1520 } 1521 1522 pAC->GIni.GP[i].PhyAddr = PHY_ADDR_MARV; 1523 1524 if (pAC->GIni.GICopperType) { 1525 1526 pAC->GIni.GP[i].PLinkSpeedCap = (SK_U8)(SK_LSPEED_CAP_AUTO | 1527 SK_LSPEED_CAP_10MBPS | SK_LSPEED_CAP_100MBPS | 1528 SK_LSPEED_CAP_1000MBPS); 1529 1530 pAC->GIni.GP[i].PLinkSpeed = (SK_U8)SK_LSPEED_AUTO; 1531 1532 pAC->GIni.GP[i].PMSCap = (SK_U8)(SK_MS_CAP_AUTO | 1533 SK_MS_CAP_MASTER | SK_MS_CAP_SLAVE); 1534 } 1535 else { 1536 Byte = (SK_U8)SK_PHY_MARV_FIBER; 1537 } 1538 } 1539#endif /* YUKON */ 1540 1541 pAC->GIni.GP[i].PhyType = (int)Byte; 1542 1543 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT, 1544 ("PHY type: %d PHY addr: %04x\n", Byte, 1545 pAC->GIni.GP[i].PhyAddr)); 1546 } 1547 1548 /* get MAC Type & set function pointers dependent on */ 1549#ifdef GENESIS 1550 if (pAC->GIni.GIGenesis) { 1551 1552 pAC->GIni.GIMacType = SK_MAC_XMAC; 1553 1554 pAC->GIni.GIFunc.pFnMacUpdateStats = SkXmUpdateStats; 1555 pAC->GIni.GIFunc.pFnMacStatistic = SkXmMacStatistic; 1556 pAC->GIni.GIFunc.pFnMacResetCounter = SkXmResetCounter; 1557 pAC->GIni.GIFunc.pFnMacOverflow = SkXmOverflowStatus; 1558 } 1559#endif /* GENESIS */ 1560 1561#ifdef YUKON 1562 if (pAC->GIni.GIYukon) { 1563 1564 pAC->GIni.GIMacType = SK_MAC_GMAC; 1565 1566 pAC->GIni.GIFunc.pFnMacUpdateStats = SkGmUpdateStats; 1567 pAC->GIni.GIFunc.pFnMacStatistic = SkGmMacStatistic; 1568 pAC->GIni.GIFunc.pFnMacResetCounter = SkGmResetCounter; 1569 pAC->GIni.GIFunc.pFnMacOverflow = SkGmOverflowStatus; 1570 1571#ifdef SPECIAL_HANDLING 1572 if (pAC->GIni.GIChipId == CHIP_ID_YUKON) { 1573 /* check HW self test result */ 1574 SK_IN8(IoC, B2_E_3, &Byte); 1575 if (Byte & B2_E3_RES_MASK) { 1576 RetVal = 6; 1577 } 1578 } 1579#endif 1580 } 1581#endif /* YUKON */ 1582 1583 return(RetVal); 1584} /* SkGeInit1 */ 1585 1586 1587/****************************************************************************** 1588 * 1589 * SkGeInit2() - Level 2 Initialization 1590 * 1591 * Description: 1592 * - start the Blink Source Counter 1593 * - start the Descriptor Poll Timer 1594 * - configure the MAC-Arbiter 1595 * - configure the Packet-Arbiter 1596 * - enable the Tx Arbiters 1597 * - enable the RAM Interface Arbiter 1598 * 1599 * Returns: 1600 * nothing 1601 */ 1602static void SkGeInit2( 1603SK_AC *pAC, /* adapter context */ 1604SK_IOC IoC) /* IO context */ 1605{ 1606#ifdef GENESIS 1607 SK_U32 DWord; 1608#endif /* GENESIS */ 1609 int i; 1610 1611 /* start the Descriptor Poll Timer */ 1612 if (pAC->GIni.GIPollTimerVal != 0) { 1613 if (pAC->GIni.GIPollTimerVal > SK_DPOLL_MAX) { 1614 pAC->GIni.GIPollTimerVal = SK_DPOLL_MAX; 1615 1616 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E017, SKERR_HWI_E017MSG); 1617 } 1618 SK_OUT32(IoC, B28_DPT_INI, pAC->GIni.GIPollTimerVal); 1619 SK_OUT8(IoC, B28_DPT_CTRL, DPT_START); 1620 } 1621 1622#ifdef GENESIS 1623 if (pAC->GIni.GIGenesis) { 1624 /* start the Blink Source Counter */ 1625 DWord = SK_BLK_DUR * (SK_U32)pAC->GIni.GIHstClkFact / 100; 1626 1627 SK_OUT32(IoC, B2_BSC_INI, DWord); 1628 SK_OUT8(IoC, B2_BSC_CTRL, BSC_START); 1629 1630 /* 1631 * Configure the MAC Arbiter and the Packet Arbiter. 1632 * They will be started once and never be stopped. 1633 */ 1634 SkGeInitMacArb(pAC, IoC); 1635 1636 SkGeInitPktArb(pAC, IoC); 1637 } 1638#endif /* GENESIS */ 1639 1640#ifdef YUKON 1641 if (pAC->GIni.GIYukon) { 1642 /* start Time Stamp Timer */ 1643 SK_OUT8(IoC, GMAC_TI_ST_CTRL, (SK_U8)GMT_ST_START); 1644 } 1645#endif /* YUKON */ 1646 1647 /* enable the Tx Arbiters */ 1648 for (i = 0; i < pAC->GIni.GIMacsFound; i++) { 1649 SK_OUT8(IoC, MR_ADDR(i, TXA_CTRL), TXA_ENA_ARB); 1650 } 1651 1652 /* enable the RAM Interface Arbiter */ 1653 SkGeInitRamIface(pAC, IoC); 1654 1655} /* SkGeInit2 */ 1656 1657/****************************************************************************** 1658 * 1659 * SkGeInit() - Initialize the GE Adapter with the specified level. 1660 * 1661 * Description: 1662 * Level 0: Initialize the Module structures. 1663 * Level 1: Generic Hardware Initialization. The IOP/MemBase pointer has 1664 * to be set before calling this level. 1665 * 1666 * o Do a software reset. 1667 * o Clear all reset bits. 1668 * o Verify that the detected hardware is present. 1669 * Return an error if not. 1670 * o Get the hardware configuration 1671 * + Set GIMacsFound with the number of MACs. 1672 * + Store the RAM size in GIRamSize. 1673 * + Save the PCI Revision ID in GIPciHwRev. 1674 * o return an error 1675 * if Number of MACs > SK_MAX_MACS 1676 * 1677 * After returning from Level 0 the adapter 1678 * may be accessed with IO operations. 1679 * 1680 * Level 2: start the Blink Source Counter 1681 * 1682 * Returns: 1683 * 0: success 1684 * 1: Number of MACs exceeds SK_MAX_MACS (after level 1) 1685 * 2: Adapter not present or not accessible 1686 * 3: Illegal initialization level 1687 * 4: Initialization Level 1 Call missing 1688 * 5: Unexpected PHY type detected 1689 * 6: HW self test failed 1690 */ 1691int SkGeInit( 1692SK_AC *pAC, /* adapter context */ 1693SK_IOC IoC, /* IO context */ 1694int Level) /* initialization level */ 1695{ 1696 int RetVal; /* return value */ 1697 SK_U32 DWord; 1698 1699 RetVal = 0; 1700 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT, 1701 ("SkGeInit(Level %d)\n", Level)); 1702 1703 switch (Level) { 1704 case SK_INIT_DATA: 1705 /* Initialization Level 0 */ 1706 SkGeInit0(pAC, IoC); 1707 pAC->GIni.GILevel = SK_INIT_DATA; 1708 break; 1709 1710 case SK_INIT_IO: 1711 /* Initialization Level 1 */ 1712 RetVal = SkGeInit1(pAC, IoC); 1713 if (RetVal != 0) { 1714 break; 1715 } 1716 1717 /* check if the adapter seems to be accessible */ 1718 SK_OUT32(IoC, B2_IRQM_INI, SK_TEST_VAL); 1719 SK_IN32(IoC, B2_IRQM_INI, &DWord); 1720 SK_OUT32(IoC, B2_IRQM_INI, 0L); 1721 1722 if (DWord != SK_TEST_VAL) { 1723 RetVal = 2; 1724 break; 1725 } 1726 1727 /* check if the number of GIMacsFound matches SK_MAX_MACS */ 1728 if (pAC->GIni.GIMacsFound > SK_MAX_MACS) { 1729 RetVal = 1; 1730 break; 1731 } 1732 1733 /* Level 1 successfully passed */ 1734 pAC->GIni.GILevel = SK_INIT_IO; 1735 break; 1736 1737 case SK_INIT_RUN: 1738 /* Initialization Level 2 */ 1739 if (pAC->GIni.GILevel != SK_INIT_IO) { 1740#ifndef SK_DIAG 1741 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E002, SKERR_HWI_E002MSG); 1742#endif /* !SK_DIAG */ 1743 RetVal = 4; 1744 break; 1745 } 1746 SkGeInit2(pAC, IoC); 1747 1748 /* Level 2 successfully passed */ 1749 pAC->GIni.GILevel = SK_INIT_RUN; 1750 break; 1751 1752 default: 1753 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E003, SKERR_HWI_E003MSG); 1754 RetVal = 3; 1755 break; 1756 } 1757 1758 return(RetVal); 1759} /* SkGeInit */ 1760 1761 1762/****************************************************************************** 1763 * 1764 * SkGeDeInit() - Deinitialize the adapter 1765 * 1766 * Description: 1767 * All ports of the adapter will be stopped if not already done. 1768 * Do a software reset and switch off all LEDs. 1769 * 1770 * Returns: 1771 * nothing 1772 */ 1773void SkGeDeInit( 1774SK_AC *pAC, /* adapter context */ 1775SK_IOC IoC) /* IO context */ 1776{ 1777 int i; 1778 SK_U16 Word; 1779 1780#if (!defined(SK_SLIM) && !defined(VCPU)) 1781 /* ensure I2C is ready */ 1782 SkI2cWaitIrq(pAC, IoC); 1783#endif 1784 1785 /* stop all current transfer activity */ 1786 for (i = 0; i < pAC->GIni.GIMacsFound; i++) { 1787 if (pAC->GIni.GP[i].PState != SK_PRT_STOP && 1788 pAC->GIni.GP[i].PState != SK_PRT_RESET) { 1789 1790 SkGeStopPort(pAC, IoC, i, SK_STOP_ALL, SK_HARD_RST); 1791 } 1792 } 1793 1794 /* Reset all bits in the PCI STATUS register */ 1795 /* 1796 * Note: PCI Cfg cycles cannot be used, because they are not 1797 * available on some platforms after 'boot time'. 1798 */ 1799 SK_IN16(IoC, PCI_C(PCI_STATUS), &Word); 1800 1801 SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_ON); 1802 SK_OUT16(IoC, PCI_C(PCI_STATUS), (SK_U16)(Word | PCI_ERRBITS)); 1803 SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 1804 1805 /* do the reset, all LEDs are switched off now */ 1806 SK_OUT8(IoC, B0_CTST, CS_RST_SET); 1807 1808 pAC->GIni.GILevel = SK_INIT_DATA; 1809} /* SkGeDeInit */ 1810 1811 1812/****************************************************************************** 1813 * 1814 * SkGeInitPort() Initialize the specified port. 1815 * 1816 * Description: 1817 * PRxQSize, PXSQSize, and PXAQSize has to be 1818 * configured for the specified port before calling this function. 1819 * The descriptor rings has to be initialized too. 1820 * 1821 * o (Re)configure queues of the specified port. 1822 * o configure the MAC of the specified port. 1823 * o put ASIC and MAC(s) in operational mode. 1824 * o initialize Rx/Tx and Sync LED 1825 * o initialize RAM Buffers and MAC FIFOs 1826 * 1827 * The port is ready to connect when returning. 1828 * 1829 * Note: 1830 * The MAC's Rx and Tx state machine is still disabled when returning. 1831 * 1832 * Returns: 1833 * 0: success 1834 * 1: Queue size initialization error. The configured values 1835 * for PRxQSize, PXSQSize, or PXAQSize are invalid for one 1836 * or more queues. The specified port was NOT initialized. 1837 * An error log entry was generated. 1838 * 2: The port has to be stopped before it can be initialized again. 1839 */ 1840int SkGeInitPort( 1841SK_AC *pAC, /* adapter context */ 1842SK_IOC IoC, /* IO context */ 1843int Port) /* Port to configure */ 1844{ 1845 SK_GEPORT *pPrt; 1846 1847 pPrt = &pAC->GIni.GP[Port]; 1848 1849 if (SkGeCheckQSize(pAC, Port) != 0) { 1850 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E004, SKERR_HWI_E004MSG); 1851 return(1); 1852 } 1853 1854 if (pPrt->PState == SK_PRT_INIT || pPrt->PState == SK_PRT_RUN) { 1855 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E005, SKERR_HWI_E005MSG); 1856 return(2); 1857 } 1858 1859 /* configuration ok, initialize the Port now */ 1860 1861#ifdef GENESIS 1862 if (pAC->GIni.GIGenesis) { 1863 /* initialize Rx, Tx and Link LED */ 1864 /* 1865 * If 1000BT Phy needs LED initialization than swap 1866 * LED and XMAC initialization order 1867 */ 1868 SkGeXmitLED(pAC, IoC, MR_ADDR(Port, TX_LED_INI), SK_LED_ENA); 1869 SkGeXmitLED(pAC, IoC, MR_ADDR(Port, RX_LED_INI), SK_LED_ENA); 1870 /* The Link LED is initialized by RLMT or Diagnostics itself */ 1871 1872 SkXmInitMac(pAC, IoC, Port); 1873 } 1874#endif /* GENESIS */ 1875 1876#ifdef YUKON 1877 if (pAC->GIni.GIYukon) { 1878 1879 SkGmInitMac(pAC, IoC, Port); 1880 } 1881#endif /* YUKON */ 1882 1883 /* do NOT initialize the Link Sync Counter */ 1884 1885 SkGeInitMacFifo(pAC, IoC, Port); 1886 1887 SkGeInitRamBufs(pAC, IoC, Port); 1888 1889 if (pPrt->PXSQSize != 0) { 1890 /* enable Force Sync bit if synchronous queue available */ 1891 SK_OUT8(IoC, MR_ADDR(Port, TXA_CTRL), TXA_ENA_FSYNC); 1892 } 1893 1894 SkGeInitBmu(pAC, IoC, Port); 1895 1896 /* mark port as initialized */ 1897 pPrt->PState = SK_PRT_INIT; 1898 1899 return(0); 1900} /* SkGeInitPort */ 1901