1/* 2 * drivers/net/phy/qsemi.c 3 * 4 * Driver for Quality Semiconductor PHYs 5 * 6 * Author: Andy Fleming 7 * 8 * Copyright (c) 2004 Freescale Semiconductor, Inc. 9 * 10 * This program is free software; you can redistribute it and/or modify it 11 * under the terms of the GNU General Public License as published by the 12 * Free Software Foundation; either version 2 of the License, or (at your 13 * option) any later version. 14 * 15 */ 16#include <linux/kernel.h> 17#include <linux/string.h> 18#include <linux/errno.h> 19#include <linux/unistd.h> 20#include <linux/slab.h> 21#include <linux/interrupt.h> 22#include <linux/init.h> 23#include <linux/delay.h> 24#include <linux/netdevice.h> 25#include <linux/etherdevice.h> 26#include <linux/skbuff.h> 27#include <linux/spinlock.h> 28#include <linux/mm.h> 29#include <linux/module.h> 30#include <linux/mii.h> 31#include <linux/ethtool.h> 32#include <linux/phy.h> 33 34#include <asm/io.h> 35#include <asm/irq.h> 36#include <asm/uaccess.h> 37 38/* ------------------------------------------------------------------------- */ 39/* The Quality Semiconductor QS6612 is used on the RPX CLLF */ 40 41/* register definitions */ 42 43#define MII_QS6612_MCR 17 /* Mode Control Register */ 44#define MII_QS6612_FTR 27 /* Factory Test Register */ 45#define MII_QS6612_MCO 28 /* Misc. Control Register */ 46#define MII_QS6612_ISR 29 /* Interrupt Source Register */ 47#define MII_QS6612_IMR 30 /* Interrupt Mask Register */ 48#define MII_QS6612_IMR_INIT 0x003a 49#define MII_QS6612_PCR 31 /* 100BaseTx PHY Control Reg. */ 50 51#define QS6612_PCR_AN_COMPLETE 0x1000 52#define QS6612_PCR_RLBEN 0x0200 53#define QS6612_PCR_DCREN 0x0100 54#define QS6612_PCR_4B5BEN 0x0040 55#define QS6612_PCR_TX_ISOLATE 0x0020 56#define QS6612_PCR_MLT3_DIS 0x0002 57#define QS6612_PCR_SCRM_DESCRM 0x0001 58 59MODULE_DESCRIPTION("Quality Semiconductor PHY driver"); 60MODULE_AUTHOR("Andy Fleming"); 61MODULE_LICENSE("GPL"); 62 63/* Returns 0, unless there's a write error */ 64static int qs6612_config_init(struct phy_device *phydev) 65{ 66 return phy_write(phydev, MII_QS6612_PCR, 0x0dc0); 67} 68 69static int qs6612_ack_interrupt(struct phy_device *phydev) 70{ 71 int err; 72 73 err = phy_read(phydev, MII_QS6612_ISR); 74 75 if (err < 0) 76 return err; 77 78 err = phy_read(phydev, MII_BMSR); 79 80 if (err < 0) 81 return err; 82 83 err = phy_read(phydev, MII_EXPANSION); 84 85 if (err < 0) 86 return err; 87 88 return 0; 89} 90 91static int qs6612_config_intr(struct phy_device *phydev) 92{ 93 int err; 94 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) 95 err = phy_write(phydev, MII_QS6612_IMR, 96 MII_QS6612_IMR_INIT); 97 else 98 err = phy_write(phydev, MII_QS6612_IMR, 0); 99 100 return err; 101 102} 103 104static struct phy_driver qs6612_driver = { 105 .phy_id = 0x00181440, 106 .name = "QS6612", 107 .phy_id_mask = 0xfffffff0, 108 .features = PHY_BASIC_FEATURES, 109 .flags = PHY_HAS_INTERRUPT, 110 .config_init = qs6612_config_init, 111 .config_aneg = genphy_config_aneg, 112 .read_status = genphy_read_status, 113 .ack_interrupt = qs6612_ack_interrupt, 114 .config_intr = qs6612_config_intr, 115 .driver = { .owner = THIS_MODULE,}, 116}; 117 118static int __init qs6612_init(void) 119{ 120 return phy_driver_register(&qs6612_driver); 121} 122 123static void __exit qs6612_exit(void) 124{ 125 phy_driver_unregister(&qs6612_driver); 126} 127 128module_init(qs6612_init); 129module_exit(qs6612_exit); 130