1/******************************************************************************* 2 3 Intel PRO/10GbE Linux driver 4 Copyright(c) 1999 - 2006 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 Linux NICS <linux.nics@intel.com> 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 26 27*******************************************************************************/ 28 29/* ixgb_hw.c 30 * Shared functions for accessing and configuring the adapter 31 */ 32 33#include "ixgb_hw.h" 34#include "ixgb_ids.h" 35 36/* Local function prototypes */ 37 38static uint32_t ixgb_hash_mc_addr(struct ixgb_hw *hw, uint8_t * mc_addr); 39 40static void ixgb_mta_set(struct ixgb_hw *hw, uint32_t hash_value); 41 42static void ixgb_get_bus_info(struct ixgb_hw *hw); 43 44static boolean_t ixgb_link_reset(struct ixgb_hw *hw); 45 46static void ixgb_optics_reset(struct ixgb_hw *hw); 47 48static ixgb_phy_type ixgb_identify_phy(struct ixgb_hw *hw); 49 50static void ixgb_clear_hw_cntrs(struct ixgb_hw *hw); 51 52static void ixgb_clear_vfta(struct ixgb_hw *hw); 53 54static void ixgb_init_rx_addrs(struct ixgb_hw *hw); 55 56static uint16_t ixgb_read_phy_reg(struct ixgb_hw *hw, 57 uint32_t reg_address, 58 uint32_t phy_address, 59 uint32_t device_type); 60 61static boolean_t ixgb_setup_fc(struct ixgb_hw *hw); 62 63static boolean_t mac_addr_valid(uint8_t *mac_addr); 64 65static uint32_t ixgb_mac_reset(struct ixgb_hw *hw) 66{ 67 uint32_t ctrl_reg; 68 69 ctrl_reg = IXGB_CTRL0_RST | 70 IXGB_CTRL0_SDP3_DIR | /* All pins are Output=1 */ 71 IXGB_CTRL0_SDP2_DIR | 72 IXGB_CTRL0_SDP1_DIR | 73 IXGB_CTRL0_SDP0_DIR | 74 IXGB_CTRL0_SDP3 | /* Initial value 1101 */ 75 IXGB_CTRL0_SDP2 | 76 IXGB_CTRL0_SDP0; 77 78#ifdef HP_ZX1 79 IXGB_WRITE_REG_IO(hw, CTRL0, ctrl_reg); 80#else 81 IXGB_WRITE_REG(hw, CTRL0, ctrl_reg); 82#endif 83 84 /* Delay a few ms just to allow the reset to complete */ 85 msleep(IXGB_DELAY_AFTER_RESET); 86 ctrl_reg = IXGB_READ_REG(hw, CTRL0); 87#ifdef DBG 88 /* Make sure the self-clearing global reset bit did self clear */ 89 ASSERT(!(ctrl_reg & IXGB_CTRL0_RST)); 90#endif 91 92 if (hw->phy_type == ixgb_phy_type_txn17401) { 93 ixgb_optics_reset(hw); 94 } 95 96 return ctrl_reg; 97} 98 99/****************************************************************************** 100 * Reset the transmit and receive units; mask and clear all interrupts. 101 * 102 * hw - Struct containing variables accessed by shared code 103 *****************************************************************************/ 104boolean_t 105ixgb_adapter_stop(struct ixgb_hw *hw) 106{ 107 uint32_t ctrl_reg; 108 uint32_t icr_reg; 109 110 DEBUGFUNC("ixgb_adapter_stop"); 111 112 /* If we are stopped or resetting exit gracefully and wait to be 113 * started again before accessing the hardware. 114 */ 115 if(hw->adapter_stopped) { 116 DEBUGOUT("Exiting because the adapter is already stopped!!!\n"); 117 return FALSE; 118 } 119 120 /* Set the Adapter Stopped flag so other driver functions stop 121 * touching the Hardware. 122 */ 123 hw->adapter_stopped = TRUE; 124 125 /* Clear interrupt mask to stop board from generating interrupts */ 126 DEBUGOUT("Masking off all interrupts\n"); 127 IXGB_WRITE_REG(hw, IMC, 0xFFFFFFFF); 128 129 /* Disable the Transmit and Receive units. Then delay to allow 130 * any pending transactions to complete before we hit the MAC with 131 * the global reset. 132 */ 133 IXGB_WRITE_REG(hw, RCTL, IXGB_READ_REG(hw, RCTL) & ~IXGB_RCTL_RXEN); 134 IXGB_WRITE_REG(hw, TCTL, IXGB_READ_REG(hw, TCTL) & ~IXGB_TCTL_TXEN); 135 msleep(IXGB_DELAY_BEFORE_RESET); 136 137 /* Issue a global reset to the MAC. This will reset the chip's 138 * transmit, receive, DMA, and link units. It will not effect 139 * the current PCI configuration. The global reset bit is self- 140 * clearing, and should clear within a microsecond. 141 */ 142 DEBUGOUT("Issuing a global reset to MAC\n"); 143 144 ctrl_reg = ixgb_mac_reset(hw); 145 146 /* Clear interrupt mask to stop board from generating interrupts */ 147 DEBUGOUT("Masking off all interrupts\n"); 148 IXGB_WRITE_REG(hw, IMC, 0xffffffff); 149 150 /* Clear any pending interrupt events. */ 151 icr_reg = IXGB_READ_REG(hw, ICR); 152 153 return (ctrl_reg & IXGB_CTRL0_RST); 154} 155 156 157/****************************************************************************** 158 * Identifies the vendor of the optics module on the adapter. The SR adapters 159 * support two different types of XPAK optics, so it is necessary to determine 160 * which optics are present before applying any optics-specific workarounds. 161 * 162 * hw - Struct containing variables accessed by shared code. 163 * 164 * Returns: the vendor of the XPAK optics module. 165 *****************************************************************************/ 166static ixgb_xpak_vendor 167ixgb_identify_xpak_vendor(struct ixgb_hw *hw) 168{ 169 uint32_t i; 170 uint16_t vendor_name[5]; 171 ixgb_xpak_vendor xpak_vendor; 172 173 DEBUGFUNC("ixgb_identify_xpak_vendor"); 174 175 /* Read the first few bytes of the vendor string from the XPAK NVR 176 * registers. These are standard XENPAK/XPAK registers, so all XPAK 177 * devices should implement them. */ 178 for (i = 0; i < 5; i++) { 179 vendor_name[i] = ixgb_read_phy_reg(hw, 180 MDIO_PMA_PMD_XPAK_VENDOR_NAME 181 + i, IXGB_PHY_ADDRESS, 182 MDIO_PMA_PMD_DID); 183 } 184 185 /* Determine the actual vendor */ 186 if (vendor_name[0] == 'I' && 187 vendor_name[1] == 'N' && 188 vendor_name[2] == 'T' && 189 vendor_name[3] == 'E' && vendor_name[4] == 'L') { 190 xpak_vendor = ixgb_xpak_vendor_intel; 191 } else { 192 xpak_vendor = ixgb_xpak_vendor_infineon; 193 } 194 195 return (xpak_vendor); 196} 197 198/****************************************************************************** 199 * Determine the physical layer module on the adapter. 200 * 201 * hw - Struct containing variables accessed by shared code. The device_id 202 * field must be (correctly) populated before calling this routine. 203 * 204 * Returns: the phy type of the adapter. 205 *****************************************************************************/ 206static ixgb_phy_type 207ixgb_identify_phy(struct ixgb_hw *hw) 208{ 209 ixgb_phy_type phy_type; 210 ixgb_xpak_vendor xpak_vendor; 211 212 DEBUGFUNC("ixgb_identify_phy"); 213 214 /* Infer the transceiver/phy type from the device id */ 215 switch (hw->device_id) { 216 case IXGB_DEVICE_ID_82597EX: 217 DEBUGOUT("Identified TXN17401 optics\n"); 218 phy_type = ixgb_phy_type_txn17401; 219 break; 220 221 case IXGB_DEVICE_ID_82597EX_SR: 222 /* The SR adapters carry two different types of XPAK optics 223 * modules; read the vendor identifier to determine the exact 224 * type of optics. */ 225 xpak_vendor = ixgb_identify_xpak_vendor(hw); 226 if (xpak_vendor == ixgb_xpak_vendor_intel) { 227 DEBUGOUT("Identified TXN17201 optics\n"); 228 phy_type = ixgb_phy_type_txn17201; 229 } else { 230 DEBUGOUT("Identified G6005 optics\n"); 231 phy_type = ixgb_phy_type_g6005; 232 } 233 break; 234 case IXGB_DEVICE_ID_82597EX_LR: 235 DEBUGOUT("Identified G6104 optics\n"); 236 phy_type = ixgb_phy_type_g6104; 237 break; 238 case IXGB_DEVICE_ID_82597EX_CX4: 239 DEBUGOUT("Identified CX4\n"); 240 xpak_vendor = ixgb_identify_xpak_vendor(hw); 241 if (xpak_vendor == ixgb_xpak_vendor_intel) { 242 DEBUGOUT("Identified TXN17201 optics\n"); 243 phy_type = ixgb_phy_type_txn17201; 244 } else { 245 DEBUGOUT("Identified G6005 optics\n"); 246 phy_type = ixgb_phy_type_g6005; 247 } 248 break; 249 default: 250 DEBUGOUT("Unknown physical layer module\n"); 251 phy_type = ixgb_phy_type_unknown; 252 break; 253 } 254 255 return (phy_type); 256} 257 258/****************************************************************************** 259 * Performs basic configuration of the adapter. 260 * 261 * hw - Struct containing variables accessed by shared code 262 * 263 * Resets the controller. 264 * Reads and validates the EEPROM. 265 * Initializes the receive address registers. 266 * Initializes the multicast table. 267 * Clears all on-chip counters. 268 * Calls routine to setup flow control settings. 269 * Leaves the transmit and receive units disabled and uninitialized. 270 * 271 * Returns: 272 * TRUE if successful, 273 * FALSE if unrecoverable problems were encountered. 274 *****************************************************************************/ 275boolean_t 276ixgb_init_hw(struct ixgb_hw *hw) 277{ 278 uint32_t i; 279 uint32_t ctrl_reg; 280 boolean_t status; 281 282 DEBUGFUNC("ixgb_init_hw"); 283 284 /* Issue a global reset to the MAC. This will reset the chip's 285 * transmit, receive, DMA, and link units. It will not effect 286 * the current PCI configuration. The global reset bit is self- 287 * clearing, and should clear within a microsecond. 288 */ 289 DEBUGOUT("Issuing a global reset to MAC\n"); 290 291 ctrl_reg = ixgb_mac_reset(hw); 292 293 DEBUGOUT("Issuing an EE reset to MAC\n"); 294#ifdef HP_ZX1 295 IXGB_WRITE_REG_IO(hw, CTRL1, IXGB_CTRL1_EE_RST); 296#else 297 IXGB_WRITE_REG(hw, CTRL1, IXGB_CTRL1_EE_RST); 298#endif 299 300 /* Delay a few ms just to allow the reset to complete */ 301 msleep(IXGB_DELAY_AFTER_EE_RESET); 302 303 if (ixgb_get_eeprom_data(hw) == FALSE) { 304 return(FALSE); 305 } 306 307 /* Use the device id to determine the type of phy/transceiver. */ 308 hw->device_id = ixgb_get_ee_device_id(hw); 309 hw->phy_type = ixgb_identify_phy(hw); 310 311 /* Setup the receive addresses. 312 * Receive Address Registers (RARs 0 - 15). 313 */ 314 ixgb_init_rx_addrs(hw); 315 316 /* 317 * Check that a valid MAC address has been set. 318 * If it is not valid, we fail hardware init. 319 */ 320 if (!mac_addr_valid(hw->curr_mac_addr)) { 321 DEBUGOUT("MAC address invalid after ixgb_init_rx_addrs\n"); 322 return(FALSE); 323 } 324 325 /* tell the routines in this file they can access hardware again */ 326 hw->adapter_stopped = FALSE; 327 328 /* Fill in the bus_info structure */ 329 ixgb_get_bus_info(hw); 330 331 /* Zero out the Multicast HASH table */ 332 DEBUGOUT("Zeroing the MTA\n"); 333 for(i = 0; i < IXGB_MC_TBL_SIZE; i++) 334 IXGB_WRITE_REG_ARRAY(hw, MTA, i, 0); 335 336 /* Zero out the VLAN Filter Table Array */ 337 ixgb_clear_vfta(hw); 338 339 /* Zero all of the hardware counters */ 340 ixgb_clear_hw_cntrs(hw); 341 342 /* Call a subroutine to setup flow control. */ 343 status = ixgb_setup_fc(hw); 344 345 /* 82597EX errata: Call check-for-link in case lane deskew is locked */ 346 ixgb_check_for_link(hw); 347 348 return (status); 349} 350 351/****************************************************************************** 352 * Initializes receive address filters. 353 * 354 * hw - Struct containing variables accessed by shared code 355 * 356 * Places the MAC address in receive address register 0 and clears the rest 357 * of the receive addresss registers. Clears the multicast table. Assumes 358 * the receiver is in reset when the routine is called. 359 *****************************************************************************/ 360static void 361ixgb_init_rx_addrs(struct ixgb_hw *hw) 362{ 363 uint32_t i; 364 365 DEBUGFUNC("ixgb_init_rx_addrs"); 366 367 /* 368 * If the current mac address is valid, assume it is a software override 369 * to the permanent address. 370 * Otherwise, use the permanent address from the eeprom. 371 */ 372 if (!mac_addr_valid(hw->curr_mac_addr)) { 373 374 /* Get the MAC address from the eeprom for later reference */ 375 ixgb_get_ee_mac_addr(hw, hw->curr_mac_addr); 376 377 DEBUGOUT3(" Keeping Permanent MAC Addr =%.2X %.2X %.2X ", 378 hw->curr_mac_addr[0], 379 hw->curr_mac_addr[1], hw->curr_mac_addr[2]); 380 DEBUGOUT3("%.2X %.2X %.2X\n", 381 hw->curr_mac_addr[3], 382 hw->curr_mac_addr[4], hw->curr_mac_addr[5]); 383 } else { 384 385 /* Setup the receive address. */ 386 DEBUGOUT("Overriding MAC Address in RAR[0]\n"); 387 DEBUGOUT3(" New MAC Addr =%.2X %.2X %.2X ", 388 hw->curr_mac_addr[0], 389 hw->curr_mac_addr[1], hw->curr_mac_addr[2]); 390 DEBUGOUT3("%.2X %.2X %.2X\n", 391 hw->curr_mac_addr[3], 392 hw->curr_mac_addr[4], hw->curr_mac_addr[5]); 393 394 ixgb_rar_set(hw, hw->curr_mac_addr, 0); 395 } 396 397 /* Zero out the other 15 receive addresses. */ 398 DEBUGOUT("Clearing RAR[1-15]\n"); 399 for(i = 1; i < IXGB_RAR_ENTRIES; i++) { 400 /* Write high reg first to disable the AV bit first */ 401 IXGB_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); 402 IXGB_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); 403 } 404 405 return; 406} 407 408/****************************************************************************** 409 * Updates the MAC's list of multicast addresses. 410 * 411 * hw - Struct containing variables accessed by shared code 412 * mc_addr_list - the list of new multicast addresses 413 * mc_addr_count - number of addresses 414 * pad - number of bytes between addresses in the list 415 * 416 * The given list replaces any existing list. Clears the last 15 receive 417 * address registers and the multicast table. Uses receive address registers 418 * for the first 15 multicast addresses, and hashes the rest into the 419 * multicast table. 420 *****************************************************************************/ 421void 422ixgb_mc_addr_list_update(struct ixgb_hw *hw, 423 uint8_t *mc_addr_list, 424 uint32_t mc_addr_count, 425 uint32_t pad) 426{ 427 uint32_t hash_value; 428 uint32_t i; 429 uint32_t rar_used_count = 1; /* RAR[0] is used for our MAC address */ 430 431 DEBUGFUNC("ixgb_mc_addr_list_update"); 432 433 /* Set the new number of MC addresses that we are being requested to use. */ 434 hw->num_mc_addrs = mc_addr_count; 435 436 /* Clear RAR[1-15] */ 437 DEBUGOUT(" Clearing RAR[1-15]\n"); 438 for(i = rar_used_count; i < IXGB_RAR_ENTRIES; i++) { 439 IXGB_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); 440 IXGB_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); 441 } 442 443 /* Clear the MTA */ 444 DEBUGOUT(" Clearing MTA\n"); 445 for(i = 0; i < IXGB_MC_TBL_SIZE; i++) { 446 IXGB_WRITE_REG_ARRAY(hw, MTA, i, 0); 447 } 448 449 /* Add the new addresses */ 450 for(i = 0; i < mc_addr_count; i++) { 451 DEBUGOUT(" Adding the multicast addresses:\n"); 452 DEBUGOUT7(" MC Addr #%d =%.2X %.2X %.2X %.2X %.2X %.2X\n", i, 453 mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad)], 454 mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad) + 455 1], 456 mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad) + 457 2], 458 mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad) + 459 3], 460 mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad) + 461 4], 462 mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad) + 463 5]); 464 465 /* Place this multicast address in the RAR if there is room, * 466 * else put it in the MTA 467 */ 468 if(rar_used_count < IXGB_RAR_ENTRIES) { 469 ixgb_rar_set(hw, 470 mc_addr_list + 471 (i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad)), 472 rar_used_count); 473 DEBUGOUT1("Added a multicast address to RAR[%d]\n", i); 474 rar_used_count++; 475 } else { 476 hash_value = ixgb_hash_mc_addr(hw, 477 mc_addr_list + 478 (i * 479 (IXGB_ETH_LENGTH_OF_ADDRESS 480 + pad))); 481 482 DEBUGOUT1(" Hash value = 0x%03X\n", hash_value); 483 484 ixgb_mta_set(hw, hash_value); 485 } 486 } 487 488 DEBUGOUT("MC Update Complete\n"); 489 return; 490} 491 492/****************************************************************************** 493 * Hashes an address to determine its location in the multicast table 494 * 495 * hw - Struct containing variables accessed by shared code 496 * mc_addr - the multicast address to hash 497 * 498 * Returns: 499 * The hash value 500 *****************************************************************************/ 501static uint32_t 502ixgb_hash_mc_addr(struct ixgb_hw *hw, 503 uint8_t *mc_addr) 504{ 505 uint32_t hash_value = 0; 506 507 DEBUGFUNC("ixgb_hash_mc_addr"); 508 509 /* The portion of the address that is used for the hash table is 510 * determined by the mc_filter_type setting. 511 */ 512 switch (hw->mc_filter_type) { 513 /* [0] [1] [2] [3] [4] [5] 514 * 01 AA 00 12 34 56 515 * LSB MSB - According to H/W docs */ 516 case 0: 517 /* [47:36] i.e. 0x563 for above example address */ 518 hash_value = 519 ((mc_addr[4] >> 4) | (((uint16_t) mc_addr[5]) << 4)); 520 break; 521 case 1: /* [46:35] i.e. 0xAC6 for above example address */ 522 hash_value = 523 ((mc_addr[4] >> 3) | (((uint16_t) mc_addr[5]) << 5)); 524 break; 525 case 2: /* [45:34] i.e. 0x5D8 for above example address */ 526 hash_value = 527 ((mc_addr[4] >> 2) | (((uint16_t) mc_addr[5]) << 6)); 528 break; 529 case 3: /* [43:32] i.e. 0x634 for above example address */ 530 hash_value = ((mc_addr[4]) | (((uint16_t) mc_addr[5]) << 8)); 531 break; 532 default: 533 /* Invalid mc_filter_type, what should we do? */ 534 DEBUGOUT("MC filter type param set incorrectly\n"); 535 ASSERT(0); 536 break; 537 } 538 539 hash_value &= 0xFFF; 540 return (hash_value); 541} 542 543/****************************************************************************** 544 * Sets the bit in the multicast table corresponding to the hash value. 545 * 546 * hw - Struct containing variables accessed by shared code 547 * hash_value - Multicast address hash value 548 *****************************************************************************/ 549static void 550ixgb_mta_set(struct ixgb_hw *hw, 551 uint32_t hash_value) 552{ 553 uint32_t hash_bit, hash_reg; 554 uint32_t mta_reg; 555 556 /* The MTA is a register array of 128 32-bit registers. 557 * It is treated like an array of 4096 bits. We want to set 558 * bit BitArray[hash_value]. So we figure out what register 559 * the bit is in, read it, OR in the new bit, then write 560 * back the new value. The register is determined by the 561 * upper 7 bits of the hash value and the bit within that 562 * register are determined by the lower 5 bits of the value. 563 */ 564 hash_reg = (hash_value >> 5) & 0x7F; 565 hash_bit = hash_value & 0x1F; 566 567 mta_reg = IXGB_READ_REG_ARRAY(hw, MTA, hash_reg); 568 569 mta_reg |= (1 << hash_bit); 570 571 IXGB_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta_reg); 572 573 return; 574} 575 576/****************************************************************************** 577 * Puts an ethernet address into a receive address register. 578 * 579 * hw - Struct containing variables accessed by shared code 580 * addr - Address to put into receive address register 581 * index - Receive address register to write 582 *****************************************************************************/ 583void 584ixgb_rar_set(struct ixgb_hw *hw, 585 uint8_t *addr, 586 uint32_t index) 587{ 588 uint32_t rar_low, rar_high; 589 590 DEBUGFUNC("ixgb_rar_set"); 591 592 /* HW expects these in little endian so we reverse the byte order 593 * from network order (big endian) to little endian 594 */ 595 rar_low = ((uint32_t) addr[0] | 596 ((uint32_t)addr[1] << 8) | 597 ((uint32_t)addr[2] << 16) | 598 ((uint32_t)addr[3] << 24)); 599 600 rar_high = ((uint32_t) addr[4] | 601 ((uint32_t)addr[5] << 8) | 602 IXGB_RAH_AV); 603 604 IXGB_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low); 605 IXGB_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high); 606 return; 607} 608 609/****************************************************************************** 610 * Writes a value to the specified offset in the VLAN filter table. 611 * 612 * hw - Struct containing variables accessed by shared code 613 * offset - Offset in VLAN filer table to write 614 * value - Value to write into VLAN filter table 615 *****************************************************************************/ 616void 617ixgb_write_vfta(struct ixgb_hw *hw, 618 uint32_t offset, 619 uint32_t value) 620{ 621 IXGB_WRITE_REG_ARRAY(hw, VFTA, offset, value); 622 return; 623} 624 625/****************************************************************************** 626 * Clears the VLAN filer table 627 * 628 * hw - Struct containing variables accessed by shared code 629 *****************************************************************************/ 630static void 631ixgb_clear_vfta(struct ixgb_hw *hw) 632{ 633 uint32_t offset; 634 635 for(offset = 0; offset < IXGB_VLAN_FILTER_TBL_SIZE; offset++) 636 IXGB_WRITE_REG_ARRAY(hw, VFTA, offset, 0); 637 return; 638} 639 640/****************************************************************************** 641 * Configures the flow control settings based on SW configuration. 642 * 643 * hw - Struct containing variables accessed by shared code 644 *****************************************************************************/ 645 646static boolean_t 647ixgb_setup_fc(struct ixgb_hw *hw) 648{ 649 uint32_t ctrl_reg; 650 uint32_t pap_reg = 0; /* by default, assume no pause time */ 651 boolean_t status = TRUE; 652 653 DEBUGFUNC("ixgb_setup_fc"); 654 655 /* Get the current control reg 0 settings */ 656 ctrl_reg = IXGB_READ_REG(hw, CTRL0); 657 658 /* Clear the Receive Pause Enable and Transmit Pause Enable bits */ 659 ctrl_reg &= ~(IXGB_CTRL0_RPE | IXGB_CTRL0_TPE); 660 661 /* The possible values of the "flow_control" parameter are: 662 * 0: Flow control is completely disabled 663 * 1: Rx flow control is enabled (we can receive pause frames 664 * but not send pause frames). 665 * 2: Tx flow control is enabled (we can send pause frames 666 * but we do not support receiving pause frames). 667 * 3: Both Rx and TX flow control (symmetric) are enabled. 668 * other: Invalid. 669 */ 670 switch (hw->fc.type) { 671 case ixgb_fc_none: /* 0 */ 672 /* Set CMDC bit to disable Rx Flow control */ 673 ctrl_reg |= (IXGB_CTRL0_CMDC); 674 break; 675 case ixgb_fc_rx_pause: /* 1 */ 676 /* RX Flow control is enabled, and TX Flow control is 677 * disabled. 678 */ 679 ctrl_reg |= (IXGB_CTRL0_RPE); 680 break; 681 case ixgb_fc_tx_pause: /* 2 */ 682 /* TX Flow control is enabled, and RX Flow control is 683 * disabled, by a software over-ride. 684 */ 685 ctrl_reg |= (IXGB_CTRL0_TPE); 686 pap_reg = hw->fc.pause_time; 687 break; 688 case ixgb_fc_full: /* 3 */ 689 /* Flow control (both RX and TX) is enabled by a software 690 * over-ride. 691 */ 692 ctrl_reg |= (IXGB_CTRL0_RPE | IXGB_CTRL0_TPE); 693 pap_reg = hw->fc.pause_time; 694 break; 695 default: 696 /* We should never get here. The value should be 0-3. */ 697 DEBUGOUT("Flow control param set incorrectly\n"); 698 ASSERT(0); 699 break; 700 } 701 702 /* Write the new settings */ 703 IXGB_WRITE_REG(hw, CTRL0, ctrl_reg); 704 705 if (pap_reg != 0) { 706 IXGB_WRITE_REG(hw, PAP, pap_reg); 707 } 708 709 /* Set the flow control receive threshold registers. Normally, 710 * these registers will be set to a default threshold that may be 711 * adjusted later by the driver's runtime code. However, if the 712 * ability to transmit pause frames in not enabled, then these 713 * registers will be set to 0. 714 */ 715 if(!(hw->fc.type & ixgb_fc_tx_pause)) { 716 IXGB_WRITE_REG(hw, FCRTL, 0); 717 IXGB_WRITE_REG(hw, FCRTH, 0); 718 } else { 719 /* We need to set up the Receive Threshold high and low water 720 * marks as well as (optionally) enabling the transmission of XON 721 * frames. */ 722 if(hw->fc.send_xon) { 723 IXGB_WRITE_REG(hw, FCRTL, 724 (hw->fc.low_water | IXGB_FCRTL_XONE)); 725 } else { 726 IXGB_WRITE_REG(hw, FCRTL, hw->fc.low_water); 727 } 728 IXGB_WRITE_REG(hw, FCRTH, hw->fc.high_water); 729 } 730 return (status); 731} 732 733/****************************************************************************** 734 * Reads a word from a device over the Management Data Interface (MDI) bus. 735 * This interface is used to manage Physical layer devices. 736 * 737 * hw - Struct containing variables accessed by hw code 738 * reg_address - Offset of device register being read. 739 * phy_address - Address of device on MDI. 740 * 741 * Returns: Data word (16 bits) from MDI device. 742 * 743 * The 82597EX has support for several MDI access methods. This routine 744 * uses the new protocol MDI Single Command and Address Operation. 745 * This requires that first an address cycle command is sent, followed by a 746 * read command. 747 *****************************************************************************/ 748static uint16_t 749ixgb_read_phy_reg(struct ixgb_hw *hw, 750 uint32_t reg_address, 751 uint32_t phy_address, 752 uint32_t device_type) 753{ 754 uint32_t i; 755 uint32_t data; 756 uint32_t command = 0; 757 758 ASSERT(reg_address <= IXGB_MAX_PHY_REG_ADDRESS); 759 ASSERT(phy_address <= IXGB_MAX_PHY_ADDRESS); 760 ASSERT(device_type <= IXGB_MAX_PHY_DEV_TYPE); 761 762 /* Setup and write the address cycle command */ 763 command = ((reg_address << IXGB_MSCA_NP_ADDR_SHIFT) | 764 (device_type << IXGB_MSCA_DEV_TYPE_SHIFT) | 765 (phy_address << IXGB_MSCA_PHY_ADDR_SHIFT) | 766 (IXGB_MSCA_ADDR_CYCLE | IXGB_MSCA_MDI_COMMAND)); 767 768 IXGB_WRITE_REG(hw, MSCA, command); 769 770 /************************************************************** 771 ** Check every 10 usec to see if the address cycle completed 772 ** The COMMAND bit will clear when the operation is complete. 773 ** This may take as long as 64 usecs (we'll wait 100 usecs max) 774 ** from the CPU Write to the Ready bit assertion. 775 **************************************************************/ 776 777 for(i = 0; i < 10; i++) 778 { 779 udelay(10); 780 781 command = IXGB_READ_REG(hw, MSCA); 782 783 if ((command & IXGB_MSCA_MDI_COMMAND) == 0) 784 break; 785 } 786 787 ASSERT((command & IXGB_MSCA_MDI_COMMAND) == 0); 788 789 /* Address cycle complete, setup and write the read command */ 790 command = ((reg_address << IXGB_MSCA_NP_ADDR_SHIFT) | 791 (device_type << IXGB_MSCA_DEV_TYPE_SHIFT) | 792 (phy_address << IXGB_MSCA_PHY_ADDR_SHIFT) | 793 (IXGB_MSCA_READ | IXGB_MSCA_MDI_COMMAND)); 794 795 IXGB_WRITE_REG(hw, MSCA, command); 796 797 /************************************************************** 798 ** Check every 10 usec to see if the read command completed 799 ** The COMMAND bit will clear when the operation is complete. 800 ** The read may take as long as 64 usecs (we'll wait 100 usecs max) 801 ** from the CPU Write to the Ready bit assertion. 802 **************************************************************/ 803 804 for(i = 0; i < 10; i++) 805 { 806 udelay(10); 807 808 command = IXGB_READ_REG(hw, MSCA); 809 810 if ((command & IXGB_MSCA_MDI_COMMAND) == 0) 811 break; 812 } 813 814 ASSERT((command & IXGB_MSCA_MDI_COMMAND) == 0); 815 816 /* Operation is complete, get the data from the MDIO Read/Write Data 817 * register and return. 818 */ 819 data = IXGB_READ_REG(hw, MSRWD); 820 data >>= IXGB_MSRWD_READ_DATA_SHIFT; 821 return((uint16_t) data); 822} 823 824/****************************************************************************** 825 * Writes a word to a device over the Management Data Interface (MDI) bus. 826 * This interface is used to manage Physical layer devices. 827 * 828 * hw - Struct containing variables accessed by hw code 829 * reg_address - Offset of device register being read. 830 * phy_address - Address of device on MDI. 831 * device_type - Also known as the Device ID or DID. 832 * data - 16-bit value to be written 833 * 834 * Returns: void. 835 * 836 * The 82597EX has support for several MDI access methods. This routine 837 * uses the new protocol MDI Single Command and Address Operation. 838 * This requires that first an address cycle command is sent, followed by a 839 * write command. 840 *****************************************************************************/ 841static void 842ixgb_write_phy_reg(struct ixgb_hw *hw, 843 uint32_t reg_address, 844 uint32_t phy_address, 845 uint32_t device_type, 846 uint16_t data) 847{ 848 uint32_t i; 849 uint32_t command = 0; 850 851 ASSERT(reg_address <= IXGB_MAX_PHY_REG_ADDRESS); 852 ASSERT(phy_address <= IXGB_MAX_PHY_ADDRESS); 853 ASSERT(device_type <= IXGB_MAX_PHY_DEV_TYPE); 854 855 /* Put the data in the MDIO Read/Write Data register */ 856 IXGB_WRITE_REG(hw, MSRWD, (uint32_t)data); 857 858 /* Setup and write the address cycle command */ 859 command = ((reg_address << IXGB_MSCA_NP_ADDR_SHIFT) | 860 (device_type << IXGB_MSCA_DEV_TYPE_SHIFT) | 861 (phy_address << IXGB_MSCA_PHY_ADDR_SHIFT) | 862 (IXGB_MSCA_ADDR_CYCLE | IXGB_MSCA_MDI_COMMAND)); 863 864 IXGB_WRITE_REG(hw, MSCA, command); 865 866 /************************************************************** 867 ** Check every 10 usec to see if the address cycle completed 868 ** The COMMAND bit will clear when the operation is complete. 869 ** This may take as long as 64 usecs (we'll wait 100 usecs max) 870 ** from the CPU Write to the Ready bit assertion. 871 **************************************************************/ 872 873 for(i = 0; i < 10; i++) 874 { 875 udelay(10); 876 877 command = IXGB_READ_REG(hw, MSCA); 878 879 if ((command & IXGB_MSCA_MDI_COMMAND) == 0) 880 break; 881 } 882 883 ASSERT((command & IXGB_MSCA_MDI_COMMAND) == 0); 884 885 /* Address cycle complete, setup and write the write command */ 886 command = ((reg_address << IXGB_MSCA_NP_ADDR_SHIFT) | 887 (device_type << IXGB_MSCA_DEV_TYPE_SHIFT) | 888 (phy_address << IXGB_MSCA_PHY_ADDR_SHIFT) | 889 (IXGB_MSCA_WRITE | IXGB_MSCA_MDI_COMMAND)); 890 891 IXGB_WRITE_REG(hw, MSCA, command); 892 893 /************************************************************** 894 ** Check every 10 usec to see if the read command completed 895 ** The COMMAND bit will clear when the operation is complete. 896 ** The write may take as long as 64 usecs (we'll wait 100 usecs max) 897 ** from the CPU Write to the Ready bit assertion. 898 **************************************************************/ 899 900 for(i = 0; i < 10; i++) 901 { 902 udelay(10); 903 904 command = IXGB_READ_REG(hw, MSCA); 905 906 if ((command & IXGB_MSCA_MDI_COMMAND) == 0) 907 break; 908 } 909 910 ASSERT((command & IXGB_MSCA_MDI_COMMAND) == 0); 911 912 /* Operation is complete, return. */ 913} 914 915/****************************************************************************** 916 * Checks to see if the link status of the hardware has changed. 917 * 918 * hw - Struct containing variables accessed by hw code 919 * 920 * Called by any function that needs to check the link status of the adapter. 921 *****************************************************************************/ 922void 923ixgb_check_for_link(struct ixgb_hw *hw) 924{ 925 uint32_t status_reg; 926 uint32_t xpcss_reg; 927 928 DEBUGFUNC("ixgb_check_for_link"); 929 930 xpcss_reg = IXGB_READ_REG(hw, XPCSS); 931 status_reg = IXGB_READ_REG(hw, STATUS); 932 933 if ((xpcss_reg & IXGB_XPCSS_ALIGN_STATUS) && 934 (status_reg & IXGB_STATUS_LU)) { 935 hw->link_up = TRUE; 936 } else if (!(xpcss_reg & IXGB_XPCSS_ALIGN_STATUS) && 937 (status_reg & IXGB_STATUS_LU)) { 938 DEBUGOUT("XPCSS Not Aligned while Status:LU is set.\n"); 939 hw->link_up = ixgb_link_reset(hw); 940 } else { 941 /* 942 * 82597EX errata. Since the lane deskew problem may prevent 943 * link, reset the link before reporting link down. 944 */ 945 hw->link_up = ixgb_link_reset(hw); 946 } 947 /* Anything else for 10 Gig?? */ 948} 949 950/****************************************************************************** 951 * Check for a bad link condition that may have occured. 952 * The indication is that the RFC / LFC registers may be incrementing 953 * continually. A full adapter reset is required to recover. 954 * 955 * hw - Struct containing variables accessed by hw code 956 * 957 * Called by any function that needs to check the link status of the adapter. 958 *****************************************************************************/ 959boolean_t ixgb_check_for_bad_link(struct ixgb_hw *hw) 960{ 961 uint32_t newLFC, newRFC; 962 boolean_t bad_link_returncode = FALSE; 963 964 if (hw->phy_type == ixgb_phy_type_txn17401) { 965 newLFC = IXGB_READ_REG(hw, LFC); 966 newRFC = IXGB_READ_REG(hw, RFC); 967 if ((hw->lastLFC + 250 < newLFC) 968 || (hw->lastRFC + 250 < newRFC)) { 969 DEBUGOUT 970 ("BAD LINK! too many LFC/RFC since last check\n"); 971 bad_link_returncode = TRUE; 972 } 973 hw->lastLFC = newLFC; 974 hw->lastRFC = newRFC; 975 } 976 977 return bad_link_returncode; 978} 979 980/****************************************************************************** 981 * Clears all hardware statistics counters. 982 * 983 * hw - Struct containing variables accessed by shared code 984 *****************************************************************************/ 985static void 986ixgb_clear_hw_cntrs(struct ixgb_hw *hw) 987{ 988 volatile uint32_t temp_reg; 989 990 DEBUGFUNC("ixgb_clear_hw_cntrs"); 991 992 /* if we are stopped or resetting exit gracefully */ 993 if(hw->adapter_stopped) { 994 DEBUGOUT("Exiting because the adapter is stopped!!!\n"); 995 return; 996 } 997 998 temp_reg = IXGB_READ_REG(hw, TPRL); 999 temp_reg = IXGB_READ_REG(hw, TPRH); 1000 temp_reg = IXGB_READ_REG(hw, GPRCL); 1001 temp_reg = IXGB_READ_REG(hw, GPRCH); 1002 temp_reg = IXGB_READ_REG(hw, BPRCL); 1003 temp_reg = IXGB_READ_REG(hw, BPRCH); 1004 temp_reg = IXGB_READ_REG(hw, MPRCL); 1005 temp_reg = IXGB_READ_REG(hw, MPRCH); 1006 temp_reg = IXGB_READ_REG(hw, UPRCL); 1007 temp_reg = IXGB_READ_REG(hw, UPRCH); 1008 temp_reg = IXGB_READ_REG(hw, VPRCL); 1009 temp_reg = IXGB_READ_REG(hw, VPRCH); 1010 temp_reg = IXGB_READ_REG(hw, JPRCL); 1011 temp_reg = IXGB_READ_REG(hw, JPRCH); 1012 temp_reg = IXGB_READ_REG(hw, GORCL); 1013 temp_reg = IXGB_READ_REG(hw, GORCH); 1014 temp_reg = IXGB_READ_REG(hw, TORL); 1015 temp_reg = IXGB_READ_REG(hw, TORH); 1016 temp_reg = IXGB_READ_REG(hw, RNBC); 1017 temp_reg = IXGB_READ_REG(hw, RUC); 1018 temp_reg = IXGB_READ_REG(hw, ROC); 1019 temp_reg = IXGB_READ_REG(hw, RLEC); 1020 temp_reg = IXGB_READ_REG(hw, CRCERRS); 1021 temp_reg = IXGB_READ_REG(hw, ICBC); 1022 temp_reg = IXGB_READ_REG(hw, ECBC); 1023 temp_reg = IXGB_READ_REG(hw, MPC); 1024 temp_reg = IXGB_READ_REG(hw, TPTL); 1025 temp_reg = IXGB_READ_REG(hw, TPTH); 1026 temp_reg = IXGB_READ_REG(hw, GPTCL); 1027 temp_reg = IXGB_READ_REG(hw, GPTCH); 1028 temp_reg = IXGB_READ_REG(hw, BPTCL); 1029 temp_reg = IXGB_READ_REG(hw, BPTCH); 1030 temp_reg = IXGB_READ_REG(hw, MPTCL); 1031 temp_reg = IXGB_READ_REG(hw, MPTCH); 1032 temp_reg = IXGB_READ_REG(hw, UPTCL); 1033 temp_reg = IXGB_READ_REG(hw, UPTCH); 1034 temp_reg = IXGB_READ_REG(hw, VPTCL); 1035 temp_reg = IXGB_READ_REG(hw, VPTCH); 1036 temp_reg = IXGB_READ_REG(hw, JPTCL); 1037 temp_reg = IXGB_READ_REG(hw, JPTCH); 1038 temp_reg = IXGB_READ_REG(hw, GOTCL); 1039 temp_reg = IXGB_READ_REG(hw, GOTCH); 1040 temp_reg = IXGB_READ_REG(hw, TOTL); 1041 temp_reg = IXGB_READ_REG(hw, TOTH); 1042 temp_reg = IXGB_READ_REG(hw, DC); 1043 temp_reg = IXGB_READ_REG(hw, PLT64C); 1044 temp_reg = IXGB_READ_REG(hw, TSCTC); 1045 temp_reg = IXGB_READ_REG(hw, TSCTFC); 1046 temp_reg = IXGB_READ_REG(hw, IBIC); 1047 temp_reg = IXGB_READ_REG(hw, RFC); 1048 temp_reg = IXGB_READ_REG(hw, LFC); 1049 temp_reg = IXGB_READ_REG(hw, PFRC); 1050 temp_reg = IXGB_READ_REG(hw, PFTC); 1051 temp_reg = IXGB_READ_REG(hw, MCFRC); 1052 temp_reg = IXGB_READ_REG(hw, MCFTC); 1053 temp_reg = IXGB_READ_REG(hw, XONRXC); 1054 temp_reg = IXGB_READ_REG(hw, XONTXC); 1055 temp_reg = IXGB_READ_REG(hw, XOFFRXC); 1056 temp_reg = IXGB_READ_REG(hw, XOFFTXC); 1057 temp_reg = IXGB_READ_REG(hw, RJC); 1058 return; 1059} 1060 1061/****************************************************************************** 1062 * Turns on the software controllable LED 1063 * 1064 * hw - Struct containing variables accessed by shared code 1065 *****************************************************************************/ 1066void 1067ixgb_led_on(struct ixgb_hw *hw) 1068{ 1069 uint32_t ctrl0_reg = IXGB_READ_REG(hw, CTRL0); 1070 1071 /* To turn on the LED, clear software-definable pin 0 (SDP0). */ 1072 ctrl0_reg &= ~IXGB_CTRL0_SDP0; 1073 IXGB_WRITE_REG(hw, CTRL0, ctrl0_reg); 1074 return; 1075} 1076 1077/****************************************************************************** 1078 * Turns off the software controllable LED 1079 * 1080 * hw - Struct containing variables accessed by shared code 1081 *****************************************************************************/ 1082void 1083ixgb_led_off(struct ixgb_hw *hw) 1084{ 1085 uint32_t ctrl0_reg = IXGB_READ_REG(hw, CTRL0); 1086 1087 /* To turn off the LED, set software-definable pin 0 (SDP0). */ 1088 ctrl0_reg |= IXGB_CTRL0_SDP0; 1089 IXGB_WRITE_REG(hw, CTRL0, ctrl0_reg); 1090 return; 1091} 1092 1093/****************************************************************************** 1094 * Gets the current PCI bus type, speed, and width of the hardware 1095 * 1096 * hw - Struct containing variables accessed by shared code 1097 *****************************************************************************/ 1098static void 1099ixgb_get_bus_info(struct ixgb_hw *hw) 1100{ 1101 uint32_t status_reg; 1102 1103 status_reg = IXGB_READ_REG(hw, STATUS); 1104 1105 hw->bus.type = (status_reg & IXGB_STATUS_PCIX_MODE) ? 1106 ixgb_bus_type_pcix : ixgb_bus_type_pci; 1107 1108 if (hw->bus.type == ixgb_bus_type_pci) { 1109 hw->bus.speed = (status_reg & IXGB_STATUS_PCI_SPD) ? 1110 ixgb_bus_speed_66 : ixgb_bus_speed_33; 1111 } else { 1112 switch (status_reg & IXGB_STATUS_PCIX_SPD_MASK) { 1113 case IXGB_STATUS_PCIX_SPD_66: 1114 hw->bus.speed = ixgb_bus_speed_66; 1115 break; 1116 case IXGB_STATUS_PCIX_SPD_100: 1117 hw->bus.speed = ixgb_bus_speed_100; 1118 break; 1119 case IXGB_STATUS_PCIX_SPD_133: 1120 hw->bus.speed = ixgb_bus_speed_133; 1121 break; 1122 default: 1123 hw->bus.speed = ixgb_bus_speed_reserved; 1124 break; 1125 } 1126 } 1127 1128 hw->bus.width = (status_reg & IXGB_STATUS_BUS64) ? 1129 ixgb_bus_width_64 : ixgb_bus_width_32; 1130 1131 return; 1132} 1133 1134/****************************************************************************** 1135 * Tests a MAC address to ensure it is a valid Individual Address 1136 * 1137 * mac_addr - pointer to MAC address. 1138 * 1139 *****************************************************************************/ 1140static boolean_t 1141mac_addr_valid(uint8_t *mac_addr) 1142{ 1143 boolean_t is_valid = TRUE; 1144 DEBUGFUNC("mac_addr_valid"); 1145 1146 /* Make sure it is not a multicast address */ 1147 if (IS_MULTICAST(mac_addr)) { 1148 DEBUGOUT("MAC address is multicast\n"); 1149 is_valid = FALSE; 1150 } 1151 /* Not a broadcast address */ 1152 else if (IS_BROADCAST(mac_addr)) { 1153 DEBUGOUT("MAC address is broadcast\n"); 1154 is_valid = FALSE; 1155 } 1156 /* Reject the zero address */ 1157 else if (mac_addr[0] == 0 && 1158 mac_addr[1] == 0 && 1159 mac_addr[2] == 0 && 1160 mac_addr[3] == 0 && 1161 mac_addr[4] == 0 && 1162 mac_addr[5] == 0) { 1163 DEBUGOUT("MAC address is all zeros\n"); 1164 is_valid = FALSE; 1165 } 1166 return (is_valid); 1167} 1168 1169/****************************************************************************** 1170 * Resets the 10GbE link. Waits the settle time and returns the state of 1171 * the link. 1172 * 1173 * hw - Struct containing variables accessed by shared code 1174 *****************************************************************************/ 1175boolean_t 1176ixgb_link_reset(struct ixgb_hw *hw) 1177{ 1178 boolean_t link_status = FALSE; 1179 uint8_t wait_retries = MAX_RESET_ITERATIONS; 1180 uint8_t lrst_retries = MAX_RESET_ITERATIONS; 1181 1182 do { 1183 /* Reset the link */ 1184 IXGB_WRITE_REG(hw, CTRL0, 1185 IXGB_READ_REG(hw, CTRL0) | IXGB_CTRL0_LRST); 1186 1187 /* Wait for link-up and lane re-alignment */ 1188 do { 1189 udelay(IXGB_DELAY_USECS_AFTER_LINK_RESET); 1190 link_status = 1191 ((IXGB_READ_REG(hw, STATUS) & IXGB_STATUS_LU) 1192 && (IXGB_READ_REG(hw, XPCSS) & 1193 IXGB_XPCSS_ALIGN_STATUS)) ? TRUE : FALSE; 1194 } while (!link_status && --wait_retries); 1195 1196 } while (!link_status && --lrst_retries); 1197 1198 return link_status; 1199} 1200 1201/****************************************************************************** 1202 * Resets the 10GbE optics module. 1203 * 1204 * hw - Struct containing variables accessed by shared code 1205 *****************************************************************************/ 1206void 1207ixgb_optics_reset(struct ixgb_hw *hw) 1208{ 1209 if (hw->phy_type == ixgb_phy_type_txn17401) { 1210 uint16_t mdio_reg; 1211 1212 ixgb_write_phy_reg(hw, 1213 MDIO_PMA_PMD_CR1, 1214 IXGB_PHY_ADDRESS, 1215 MDIO_PMA_PMD_DID, 1216 MDIO_PMA_PMD_CR1_RESET); 1217 1218 mdio_reg = ixgb_read_phy_reg( hw, 1219 MDIO_PMA_PMD_CR1, 1220 IXGB_PHY_ADDRESS, 1221 MDIO_PMA_PMD_DID); 1222 } 1223 1224 return; 1225} 1226