1/********************************************************************* 2 * $Id: smsc-ircc2.c,v 1.1.1.1 2007/08/03 18:52:47 Exp $ 3 * 4 * Description: Driver for the SMC Infrared Communications Controller 5 * Status: Experimental. 6 * Author: Daniele Peri (peri@csai.unipa.it) 7 * Created at: 8 * Modified at: 9 * Modified by: 10 * 11 * Copyright (c) 2002 Daniele Peri 12 * All Rights Reserved. 13 * Copyright (c) 2002 Jean Tourrilhes 14 * Copyright (c) 2006 Linus Walleij 15 * 16 * 17 * Based on smc-ircc.c: 18 * 19 * Copyright (c) 2001 Stefani Seibold 20 * Copyright (c) 1999-2001 Dag Brattli 21 * Copyright (c) 1998-1999 Thomas Davis, 22 * 23 * and irport.c: 24 * 25 * Copyright (c) 1997, 1998, 1999-2000 Dag Brattli, All Rights Reserved. 26 * 27 * 28 * This program is free software; you can redistribute it and/or 29 * modify it under the terms of the GNU General Public License as 30 * published by the Free Software Foundation; either version 2 of 31 * the License, or (at your option) any later version. 32 * 33 * This program is distributed in the hope that it will be useful, 34 * but WITHOUT ANY WARRANTY; without even the implied warranty of 35 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 36 * GNU General Public License for more details. 37 * 38 * You should have received a copy of the GNU General Public License 39 * along with this program; if not, write to the Free Software 40 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 41 * MA 02111-1307 USA 42 * 43 ********************************************************************/ 44 45#include <linux/module.h> 46#include <linux/kernel.h> 47#include <linux/types.h> 48#include <linux/skbuff.h> 49#include <linux/netdevice.h> 50#include <linux/ioport.h> 51#include <linux/delay.h> 52#include <linux/slab.h> 53#include <linux/init.h> 54#include <linux/rtnetlink.h> 55#include <linux/serial_reg.h> 56#include <linux/dma-mapping.h> 57#include <linux/pnp.h> 58#include <linux/platform_device.h> 59 60#include <asm/io.h> 61#include <asm/dma.h> 62#include <asm/byteorder.h> 63 64#include <linux/spinlock.h> 65#include <linux/pm.h> 66#ifdef CONFIG_PCI 67#include <linux/pci.h> 68#endif 69 70#include <net/irda/wrapper.h> 71#include <net/irda/irda.h> 72#include <net/irda/irda_device.h> 73 74#include "smsc-ircc2.h" 75#include "smsc-sio.h" 76 77 78MODULE_AUTHOR("Daniele Peri <peri@csai.unipa.it>"); 79MODULE_DESCRIPTION("SMC IrCC SIR/FIR controller driver"); 80MODULE_LICENSE("GPL"); 81 82static int smsc_nopnp = 1; 83module_param_named(nopnp, smsc_nopnp, bool, 0); 84MODULE_PARM_DESC(nopnp, "Do not use PNP to detect controller settings"); 85 86#define DMA_INVAL 255 87static int ircc_dma = DMA_INVAL; 88module_param(ircc_dma, int, 0); 89MODULE_PARM_DESC(ircc_dma, "DMA channel"); 90 91#define IRQ_INVAL 255 92static int ircc_irq = IRQ_INVAL; 93module_param(ircc_irq, int, 0); 94MODULE_PARM_DESC(ircc_irq, "IRQ line"); 95 96static int ircc_fir; 97module_param(ircc_fir, int, 0); 98MODULE_PARM_DESC(ircc_fir, "FIR Base Address"); 99 100static int ircc_sir; 101module_param(ircc_sir, int, 0); 102MODULE_PARM_DESC(ircc_sir, "SIR Base Address"); 103 104static int ircc_cfg; 105module_param(ircc_cfg, int, 0); 106MODULE_PARM_DESC(ircc_cfg, "Configuration register base address"); 107 108static int ircc_transceiver; 109module_param(ircc_transceiver, int, 0); 110MODULE_PARM_DESC(ircc_transceiver, "Transceiver type"); 111 112/* Types */ 113 114#ifdef CONFIG_PCI 115struct smsc_ircc_subsystem_configuration { 116 unsigned short vendor; /* PCI vendor ID */ 117 unsigned short device; /* PCI vendor ID */ 118 unsigned short subvendor; /* PCI subsystem vendor ID */ 119 unsigned short subdevice; /* PCI sybsystem device ID */ 120 unsigned short sir_io; /* I/O port for SIR */ 121 unsigned short fir_io; /* I/O port for FIR */ 122 unsigned char fir_irq; /* FIR IRQ */ 123 unsigned char fir_dma; /* FIR DMA */ 124 unsigned short cfg_base; /* I/O port for chip configuration */ 125 int (*preconfigure)(struct pci_dev *dev, struct smsc_ircc_subsystem_configuration *conf); /* Preconfig function */ 126 const char *name; /* name shown as info */ 127}; 128#endif 129 130struct smsc_transceiver { 131 char *name; 132 void (*set_for_speed)(int fir_base, u32 speed); 133 int (*probe)(int fir_base); 134}; 135 136struct smsc_chip { 137 char *name; 138 #if 0 139 u8 type; 140 #endif 141 u16 flags; 142 u8 devid; 143 u8 rev; 144}; 145 146struct smsc_chip_address { 147 unsigned int cfg_base; 148 unsigned int type; 149}; 150 151/* Private data for each instance */ 152struct smsc_ircc_cb { 153 struct net_device *netdev; /* Yes! we are some kind of netdevice */ 154 struct net_device_stats stats; 155 struct irlap_cb *irlap; /* The link layer we are binded to */ 156 157 chipio_t io; /* IrDA controller information */ 158 iobuff_t tx_buff; /* Transmit buffer */ 159 iobuff_t rx_buff; /* Receive buffer */ 160 dma_addr_t tx_buff_dma; 161 dma_addr_t rx_buff_dma; 162 163 struct qos_info qos; /* QoS capabilities for this device */ 164 165 spinlock_t lock; /* For serializing operations */ 166 167 __u32 new_speed; 168 __u32 flags; /* Interface flags */ 169 170 int tx_buff_offsets[10]; /* Offsets between frames in tx_buff */ 171 int tx_len; /* Number of frames in tx_buff */ 172 173 int transceiver; 174 struct platform_device *pldev; 175}; 176 177/* Constants */ 178 179#define SMSC_IRCC2_DRIVER_NAME "smsc-ircc2" 180 181#define SMSC_IRCC2_C_IRDA_FALLBACK_SPEED 9600 182#define SMSC_IRCC2_C_DEFAULT_TRANSCEIVER 1 183#define SMSC_IRCC2_C_NET_TIMEOUT 0 184#define SMSC_IRCC2_C_SIR_STOP 0 185 186static const char *driver_name = SMSC_IRCC2_DRIVER_NAME; 187 188/* Prototypes */ 189 190static int smsc_ircc_open(unsigned int firbase, unsigned int sirbase, u8 dma, u8 irq); 191static int smsc_ircc_present(unsigned int fir_base, unsigned int sir_base); 192static void smsc_ircc_setup_io(struct smsc_ircc_cb *self, unsigned int fir_base, unsigned int sir_base, u8 dma, u8 irq); 193static void smsc_ircc_setup_qos(struct smsc_ircc_cb *self); 194static void smsc_ircc_init_chip(struct smsc_ircc_cb *self); 195static int __exit smsc_ircc_close(struct smsc_ircc_cb *self); 196static int smsc_ircc_dma_receive(struct smsc_ircc_cb *self); 197static void smsc_ircc_dma_receive_complete(struct smsc_ircc_cb *self); 198static void smsc_ircc_sir_receive(struct smsc_ircc_cb *self); 199static int smsc_ircc_hard_xmit_sir(struct sk_buff *skb, struct net_device *dev); 200static int smsc_ircc_hard_xmit_fir(struct sk_buff *skb, struct net_device *dev); 201static void smsc_ircc_dma_xmit(struct smsc_ircc_cb *self, int bofs); 202static void smsc_ircc_dma_xmit_complete(struct smsc_ircc_cb *self); 203static void smsc_ircc_change_speed(struct smsc_ircc_cb *self, u32 speed); 204static void smsc_ircc_set_sir_speed(struct smsc_ircc_cb *self, u32 speed); 205static irqreturn_t smsc_ircc_interrupt(int irq, void *dev_id); 206static irqreturn_t smsc_ircc_interrupt_sir(struct net_device *dev); 207static void smsc_ircc_sir_start(struct smsc_ircc_cb *self); 208#if SMSC_IRCC2_C_SIR_STOP 209static void smsc_ircc_sir_stop(struct smsc_ircc_cb *self); 210#endif 211static void smsc_ircc_sir_write_wakeup(struct smsc_ircc_cb *self); 212static int smsc_ircc_sir_write(int iobase, int fifo_size, __u8 *buf, int len); 213static int smsc_ircc_net_open(struct net_device *dev); 214static int smsc_ircc_net_close(struct net_device *dev); 215static int smsc_ircc_net_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); 216#if SMSC_IRCC2_C_NET_TIMEOUT 217static void smsc_ircc_timeout(struct net_device *dev); 218#endif 219static struct net_device_stats *smsc_ircc_net_get_stats(struct net_device *dev); 220static int smsc_ircc_is_receiving(struct smsc_ircc_cb *self); 221static void smsc_ircc_probe_transceiver(struct smsc_ircc_cb *self); 222static void smsc_ircc_set_transceiver_for_speed(struct smsc_ircc_cb *self, u32 speed); 223static void smsc_ircc_sir_wait_hw_transmitter_finish(struct smsc_ircc_cb *self); 224 225/* Probing */ 226static int __init smsc_ircc_look_for_chips(void); 227static const struct smsc_chip * __init smsc_ircc_probe(unsigned short cfg_base, u8 reg, const struct smsc_chip *chip, char *type); 228static int __init smsc_superio_flat(const struct smsc_chip *chips, unsigned short cfg_base, char *type); 229static int __init smsc_superio_paged(const struct smsc_chip *chips, unsigned short cfg_base, char *type); 230static int __init smsc_superio_fdc(unsigned short cfg_base); 231static int __init smsc_superio_lpc(unsigned short cfg_base); 232#ifdef CONFIG_PCI 233static int __init preconfigure_smsc_chip(struct smsc_ircc_subsystem_configuration *conf); 234static int __init preconfigure_through_82801(struct pci_dev *dev, struct smsc_ircc_subsystem_configuration *conf); 235static void __init preconfigure_ali_port(struct pci_dev *dev, 236 unsigned short port); 237static int __init preconfigure_through_ali(struct pci_dev *dev, struct smsc_ircc_subsystem_configuration *conf); 238static int __init smsc_ircc_preconfigure_subsystems(unsigned short ircc_cfg, 239 unsigned short ircc_fir, 240 unsigned short ircc_sir, 241 unsigned char ircc_dma, 242 unsigned char ircc_irq); 243#endif 244 245/* Transceivers specific functions */ 246 247static void smsc_ircc_set_transceiver_toshiba_sat1800(int fir_base, u32 speed); 248static int smsc_ircc_probe_transceiver_toshiba_sat1800(int fir_base); 249static void smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select(int fir_base, u32 speed); 250static int smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select(int fir_base); 251static void smsc_ircc_set_transceiver_smsc_ircc_atc(int fir_base, u32 speed); 252static int smsc_ircc_probe_transceiver_smsc_ircc_atc(int fir_base); 253 254/* Power Management */ 255 256static int smsc_ircc_suspend(struct platform_device *dev, pm_message_t state); 257static int smsc_ircc_resume(struct platform_device *dev); 258 259static struct platform_driver smsc_ircc_driver = { 260 .suspend = smsc_ircc_suspend, 261 .resume = smsc_ircc_resume, 262 .driver = { 263 .name = SMSC_IRCC2_DRIVER_NAME, 264 }, 265}; 266 267/* Transceivers for SMSC-ircc */ 268 269static struct smsc_transceiver smsc_transceivers[] = 270{ 271 { "Toshiba Satellite 1800 (GP data pin select)", smsc_ircc_set_transceiver_toshiba_sat1800, smsc_ircc_probe_transceiver_toshiba_sat1800 }, 272 { "Fast pin select", smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select, smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select }, 273 { "ATC IRMode", smsc_ircc_set_transceiver_smsc_ircc_atc, smsc_ircc_probe_transceiver_smsc_ircc_atc }, 274 { NULL, NULL } 275}; 276#define SMSC_IRCC2_C_NUMBER_OF_TRANSCEIVERS (ARRAY_SIZE(smsc_transceivers) - 1) 277 278/* SMC SuperIO chipsets definitions */ 279 280#define KEY55_1 0 /* SuperIO Configuration mode with Key <0x55> */ 281#define KEY55_2 1 /* SuperIO Configuration mode with Key <0x55,0x55> */ 282#define NoIRDA 2 /* SuperIO Chip has no IRDA Port */ 283#define SIR 0 /* SuperIO Chip has only slow IRDA */ 284#define FIR 4 /* SuperIO Chip has fast IRDA */ 285#define SERx4 8 /* SuperIO Chip supports 115,2 KBaud * 4=460,8 KBaud */ 286 287static struct smsc_chip __initdata fdc_chips_flat[] = 288{ 289 /* Base address 0x3f0 or 0x370 */ 290 { "37C44", KEY55_1|NoIRDA, 0x00, 0x00 }, /* This chip cannot be detected */ 291 { "37C665GT", KEY55_2|NoIRDA, 0x65, 0x01 }, 292 { "37C665GT", KEY55_2|NoIRDA, 0x66, 0x01 }, 293 { "37C669", KEY55_2|SIR|SERx4, 0x03, 0x02 }, 294 { "37C669", KEY55_2|SIR|SERx4, 0x04, 0x02 }, /* ID? */ 295 { "37C78", KEY55_2|NoIRDA, 0x78, 0x00 }, 296 { "37N769", KEY55_1|FIR|SERx4, 0x28, 0x00 }, 297 { "37N869", KEY55_1|FIR|SERx4, 0x29, 0x00 }, 298 { NULL } 299}; 300 301static struct smsc_chip __initdata fdc_chips_paged[] = 302{ 303 /* Base address 0x3f0 or 0x370 */ 304 { "37B72X", KEY55_1|SIR|SERx4, 0x4c, 0x00 }, 305 { "37B77X", KEY55_1|SIR|SERx4, 0x43, 0x00 }, 306 { "37B78X", KEY55_1|SIR|SERx4, 0x44, 0x00 }, 307 { "37B80X", KEY55_1|SIR|SERx4, 0x42, 0x00 }, 308 { "37C67X", KEY55_1|FIR|SERx4, 0x40, 0x00 }, 309 { "37C93X", KEY55_2|SIR|SERx4, 0x02, 0x01 }, 310 { "37C93XAPM", KEY55_1|SIR|SERx4, 0x30, 0x01 }, 311 { "37C93XFR", KEY55_2|FIR|SERx4, 0x03, 0x01 }, 312 { "37M707", KEY55_1|SIR|SERx4, 0x42, 0x00 }, 313 { "37M81X", KEY55_1|SIR|SERx4, 0x4d, 0x00 }, 314 { "37N958FR", KEY55_1|FIR|SERx4, 0x09, 0x04 }, 315 { "37N971", KEY55_1|FIR|SERx4, 0x0a, 0x00 }, 316 { "37N972", KEY55_1|FIR|SERx4, 0x0b, 0x00 }, 317 { NULL } 318}; 319 320static struct smsc_chip __initdata lpc_chips_flat[] = 321{ 322 /* Base address 0x2E or 0x4E */ 323 { "47N227", KEY55_1|FIR|SERx4, 0x5a, 0x00 }, 324 { "47N227", KEY55_1|FIR|SERx4, 0x7a, 0x00 }, 325 { "47N267", KEY55_1|FIR|SERx4, 0x5e, 0x00 }, 326 { NULL } 327}; 328 329static struct smsc_chip __initdata lpc_chips_paged[] = 330{ 331 /* Base address 0x2E or 0x4E */ 332 { "47B27X", KEY55_1|SIR|SERx4, 0x51, 0x00 }, 333 { "47B37X", KEY55_1|SIR|SERx4, 0x52, 0x00 }, 334 { "47M10X", KEY55_1|SIR|SERx4, 0x59, 0x00 }, 335 { "47M120", KEY55_1|NoIRDA|SERx4, 0x5c, 0x00 }, 336 { "47M13X", KEY55_1|SIR|SERx4, 0x59, 0x00 }, 337 { "47M14X", KEY55_1|SIR|SERx4, 0x5f, 0x00 }, 338 { "47N252", KEY55_1|FIR|SERx4, 0x0e, 0x00 }, 339 { "47S42X", KEY55_1|SIR|SERx4, 0x57, 0x00 }, 340 { NULL } 341}; 342 343#define SMSCSIO_TYPE_FDC 1 344#define SMSCSIO_TYPE_LPC 2 345#define SMSCSIO_TYPE_FLAT 4 346#define SMSCSIO_TYPE_PAGED 8 347 348static struct smsc_chip_address __initdata possible_addresses[] = 349{ 350 { 0x3f0, SMSCSIO_TYPE_FDC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED }, 351 { 0x370, SMSCSIO_TYPE_FDC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED }, 352 { 0xe0, SMSCSIO_TYPE_FDC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED }, 353 { 0x2e, SMSCSIO_TYPE_LPC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED }, 354 { 0x4e, SMSCSIO_TYPE_LPC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED }, 355 { 0, 0 } 356}; 357 358/* Globals */ 359 360static struct smsc_ircc_cb *dev_self[] = { NULL, NULL }; 361static unsigned short dev_count; 362 363static inline void register_bank(int iobase, int bank) 364{ 365 outb(((inb(iobase + IRCC_MASTER) & 0xf0) | (bank & 0x07)), 366 iobase + IRCC_MASTER); 367} 368 369/* PNP hotplug support */ 370static const struct pnp_device_id smsc_ircc_pnp_table[] = { 371 { .id = "SMCf010", .driver_data = 0 }, 372 /* and presumably others */ 373 { } 374}; 375MODULE_DEVICE_TABLE(pnp, smsc_ircc_pnp_table); 376 377static int pnp_driver_registered; 378 379static int __init smsc_ircc_pnp_probe(struct pnp_dev *dev, 380 const struct pnp_device_id *dev_id) 381{ 382 unsigned int firbase, sirbase; 383 u8 dma, irq; 384 385 if (!(pnp_port_valid(dev, 0) && pnp_port_valid(dev, 1) && 386 pnp_dma_valid(dev, 0) && pnp_irq_valid(dev, 0))) 387 return -EINVAL; 388 389 sirbase = pnp_port_start(dev, 0); 390 firbase = pnp_port_start(dev, 1); 391 dma = pnp_dma(dev, 0); 392 irq = pnp_irq(dev, 0); 393 394 if (smsc_ircc_open(firbase, sirbase, dma, irq)) 395 return -ENODEV; 396 397 return 0; 398} 399 400static struct pnp_driver smsc_ircc_pnp_driver = { 401 .name = "smsc-ircc2", 402 .id_table = smsc_ircc_pnp_table, 403 .probe = smsc_ircc_pnp_probe, 404}; 405 406 407/******************************************************************************* 408 * 409 * 410 * SMSC-ircc stuff 411 * 412 * 413 *******************************************************************************/ 414 415static int __init smsc_ircc_legacy_probe(void) 416{ 417 int ret = 0; 418 419#ifdef CONFIG_PCI 420 if (smsc_ircc_preconfigure_subsystems(ircc_cfg, ircc_fir, ircc_sir, ircc_dma, ircc_irq) < 0) { 421 /* Ignore errors from preconfiguration */ 422 IRDA_ERROR("%s, Preconfiguration failed !\n", driver_name); 423 } 424#endif 425 426 if (ircc_fir > 0 && ircc_sir > 0) { 427 IRDA_MESSAGE(" Overriding FIR address 0x%04x\n", ircc_fir); 428 IRDA_MESSAGE(" Overriding SIR address 0x%04x\n", ircc_sir); 429 430 if (smsc_ircc_open(ircc_fir, ircc_sir, ircc_dma, ircc_irq)) 431 ret = -ENODEV; 432 } else { 433 ret = -ENODEV; 434 435 /* try user provided configuration register base address */ 436 if (ircc_cfg > 0) { 437 IRDA_MESSAGE(" Overriding configuration address " 438 "0x%04x\n", ircc_cfg); 439 if (!smsc_superio_fdc(ircc_cfg)) 440 ret = 0; 441 if (!smsc_superio_lpc(ircc_cfg)) 442 ret = 0; 443 } 444 445 if (smsc_ircc_look_for_chips() > 0) 446 ret = 0; 447 } 448 return ret; 449} 450 451/* 452 * Function smsc_ircc_init () 453 * 454 * Initialize chip. Just try to find out how many chips we are dealing with 455 * and where they are 456 */ 457static int __init smsc_ircc_init(void) 458{ 459 int ret; 460 461 IRDA_DEBUG(1, "%s\n", __FUNCTION__); 462 463 ret = platform_driver_register(&smsc_ircc_driver); 464 if (ret) { 465 IRDA_ERROR("%s, Can't register driver!\n", driver_name); 466 return ret; 467 } 468 469 dev_count = 0; 470 471 if (smsc_nopnp || !pnp_platform_devices || 472 ircc_cfg || ircc_fir || ircc_sir || 473 ircc_dma != DMA_INVAL || ircc_irq != IRQ_INVAL) { 474 ret = smsc_ircc_legacy_probe(); 475 } else { 476 if (pnp_register_driver(&smsc_ircc_pnp_driver) == 0) 477 pnp_driver_registered = 1; 478 } 479 480 if (ret) { 481 if (pnp_driver_registered) 482 pnp_unregister_driver(&smsc_ircc_pnp_driver); 483 platform_driver_unregister(&smsc_ircc_driver); 484 } 485 486 return ret; 487} 488 489/* 490 * Function smsc_ircc_open (firbase, sirbase, dma, irq) 491 * 492 * Try to open driver instance 493 * 494 */ 495static int __init smsc_ircc_open(unsigned int fir_base, unsigned int sir_base, u8 dma, u8 irq) 496{ 497 struct smsc_ircc_cb *self; 498 struct net_device *dev; 499 int err; 500 501 IRDA_DEBUG(1, "%s\n", __FUNCTION__); 502 503 err = smsc_ircc_present(fir_base, sir_base); 504 if (err) 505 goto err_out; 506 507 err = -ENOMEM; 508 if (dev_count >= ARRAY_SIZE(dev_self)) { 509 IRDA_WARNING("%s(), too many devices!\n", __FUNCTION__); 510 goto err_out1; 511 } 512 513 /* 514 * Allocate new instance of the driver 515 */ 516 dev = alloc_irdadev(sizeof(struct smsc_ircc_cb)); 517 if (!dev) { 518 IRDA_WARNING("%s() can't allocate net device\n", __FUNCTION__); 519 goto err_out1; 520 } 521 522 SET_MODULE_OWNER(dev); 523 524 dev->hard_start_xmit = smsc_ircc_hard_xmit_sir; 525#if SMSC_IRCC2_C_NET_TIMEOUT 526 dev->tx_timeout = smsc_ircc_timeout; 527 dev->watchdog_timeo = HZ * 2; /* Allow enough time for speed change */ 528#endif 529 dev->open = smsc_ircc_net_open; 530 dev->stop = smsc_ircc_net_close; 531 dev->do_ioctl = smsc_ircc_net_ioctl; 532 dev->get_stats = smsc_ircc_net_get_stats; 533 534 self = netdev_priv(dev); 535 self->netdev = dev; 536 537 /* Make ifconfig display some details */ 538 dev->base_addr = self->io.fir_base = fir_base; 539 dev->irq = self->io.irq = irq; 540 541 /* Need to store self somewhere */ 542 dev_self[dev_count] = self; 543 spin_lock_init(&self->lock); 544 545 self->rx_buff.truesize = SMSC_IRCC2_RX_BUFF_TRUESIZE; 546 self->tx_buff.truesize = SMSC_IRCC2_TX_BUFF_TRUESIZE; 547 548 self->rx_buff.head = 549 dma_alloc_coherent(NULL, self->rx_buff.truesize, 550 &self->rx_buff_dma, GFP_KERNEL); 551 if (self->rx_buff.head == NULL) { 552 IRDA_ERROR("%s, Can't allocate memory for receive buffer!\n", 553 driver_name); 554 goto err_out2; 555 } 556 557 self->tx_buff.head = 558 dma_alloc_coherent(NULL, self->tx_buff.truesize, 559 &self->tx_buff_dma, GFP_KERNEL); 560 if (self->tx_buff.head == NULL) { 561 IRDA_ERROR("%s, Can't allocate memory for transmit buffer!\n", 562 driver_name); 563 goto err_out3; 564 } 565 566 memset(self->rx_buff.head, 0, self->rx_buff.truesize); 567 memset(self->tx_buff.head, 0, self->tx_buff.truesize); 568 569 self->rx_buff.in_frame = FALSE; 570 self->rx_buff.state = OUTSIDE_FRAME; 571 self->tx_buff.data = self->tx_buff.head; 572 self->rx_buff.data = self->rx_buff.head; 573 574 smsc_ircc_setup_io(self, fir_base, sir_base, dma, irq); 575 smsc_ircc_setup_qos(self); 576 smsc_ircc_init_chip(self); 577 578 if (ircc_transceiver > 0 && 579 ircc_transceiver < SMSC_IRCC2_C_NUMBER_OF_TRANSCEIVERS) 580 self->transceiver = ircc_transceiver; 581 else 582 smsc_ircc_probe_transceiver(self); 583 584 err = register_netdev(self->netdev); 585 if (err) { 586 IRDA_ERROR("%s, Network device registration failed!\n", 587 driver_name); 588 goto err_out4; 589 } 590 591 self->pldev = platform_device_register_simple(SMSC_IRCC2_DRIVER_NAME, 592 dev_count, NULL, 0); 593 if (IS_ERR(self->pldev)) { 594 err = PTR_ERR(self->pldev); 595 goto err_out5; 596 } 597 platform_set_drvdata(self->pldev, self); 598 599 IRDA_MESSAGE("IrDA: Registered device %s\n", dev->name); 600 dev_count++; 601 602 return 0; 603 604 err_out5: 605 unregister_netdev(self->netdev); 606 607 err_out4: 608 dma_free_coherent(NULL, self->tx_buff.truesize, 609 self->tx_buff.head, self->tx_buff_dma); 610 err_out3: 611 dma_free_coherent(NULL, self->rx_buff.truesize, 612 self->rx_buff.head, self->rx_buff_dma); 613 err_out2: 614 free_netdev(self->netdev); 615 dev_self[dev_count] = NULL; 616 err_out1: 617 release_region(fir_base, SMSC_IRCC2_FIR_CHIP_IO_EXTENT); 618 release_region(sir_base, SMSC_IRCC2_SIR_CHIP_IO_EXTENT); 619 err_out: 620 return err; 621} 622 623/* 624 * Function smsc_ircc_present(fir_base, sir_base) 625 * 626 * Check the smsc-ircc chip presence 627 * 628 */ 629static int smsc_ircc_present(unsigned int fir_base, unsigned int sir_base) 630{ 631 unsigned char low, high, chip, config, dma, irq, version; 632 633 if (!request_region(fir_base, SMSC_IRCC2_FIR_CHIP_IO_EXTENT, 634 driver_name)) { 635 IRDA_WARNING("%s: can't get fir_base of 0x%03x\n", 636 __FUNCTION__, fir_base); 637 goto out1; 638 } 639 640 if (!request_region(sir_base, SMSC_IRCC2_SIR_CHIP_IO_EXTENT, 641 driver_name)) { 642 IRDA_WARNING("%s: can't get sir_base of 0x%03x\n", 643 __FUNCTION__, sir_base); 644 goto out2; 645 } 646 647 register_bank(fir_base, 3); 648 649 high = inb(fir_base + IRCC_ID_HIGH); 650 low = inb(fir_base + IRCC_ID_LOW); 651 chip = inb(fir_base + IRCC_CHIP_ID); 652 version = inb(fir_base + IRCC_VERSION); 653 config = inb(fir_base + IRCC_INTERFACE); 654 dma = config & IRCC_INTERFACE_DMA_MASK; 655 irq = (config & IRCC_INTERFACE_IRQ_MASK) >> 4; 656 657 if (high != 0x10 || low != 0xb8 || (chip != 0xf1 && chip != 0xf2)) { 658 IRDA_WARNING("%s(), addr 0x%04x - no device found!\n", 659 __FUNCTION__, fir_base); 660 goto out3; 661 } 662 IRDA_MESSAGE("SMsC IrDA Controller found\n IrCC version %d.%d, " 663 "firport 0x%03x, sirport 0x%03x dma=%d, irq=%d\n", 664 chip & 0x0f, version, fir_base, sir_base, dma, irq); 665 666 return 0; 667 668 out3: 669 release_region(sir_base, SMSC_IRCC2_SIR_CHIP_IO_EXTENT); 670 out2: 671 release_region(fir_base, SMSC_IRCC2_FIR_CHIP_IO_EXTENT); 672 out1: 673 return -ENODEV; 674} 675 676/* 677 * Function smsc_ircc_setup_io(self, fir_base, sir_base, dma, irq) 678 * 679 * Setup I/O 680 * 681 */ 682static void smsc_ircc_setup_io(struct smsc_ircc_cb *self, 683 unsigned int fir_base, unsigned int sir_base, 684 u8 dma, u8 irq) 685{ 686 unsigned char config, chip_dma, chip_irq; 687 688 register_bank(fir_base, 3); 689 config = inb(fir_base + IRCC_INTERFACE); 690 chip_dma = config & IRCC_INTERFACE_DMA_MASK; 691 chip_irq = (config & IRCC_INTERFACE_IRQ_MASK) >> 4; 692 693 self->io.fir_base = fir_base; 694 self->io.sir_base = sir_base; 695 self->io.fir_ext = SMSC_IRCC2_FIR_CHIP_IO_EXTENT; 696 self->io.sir_ext = SMSC_IRCC2_SIR_CHIP_IO_EXTENT; 697 self->io.fifo_size = SMSC_IRCC2_FIFO_SIZE; 698 self->io.speed = SMSC_IRCC2_C_IRDA_FALLBACK_SPEED; 699 700 if (irq != IRQ_INVAL) { 701 if (irq != chip_irq) 702 IRDA_MESSAGE("%s, Overriding IRQ - chip says %d, using %d\n", 703 driver_name, chip_irq, irq); 704 self->io.irq = irq; 705 } else 706 self->io.irq = chip_irq; 707 708 if (dma != DMA_INVAL) { 709 if (dma != chip_dma) 710 IRDA_MESSAGE("%s, Overriding DMA - chip says %d, using %d\n", 711 driver_name, chip_dma, dma); 712 self->io.dma = dma; 713 } else 714 self->io.dma = chip_dma; 715 716} 717 718/* 719 * Function smsc_ircc_setup_qos(self) 720 * 721 * Setup qos 722 * 723 */ 724static void smsc_ircc_setup_qos(struct smsc_ircc_cb *self) 725{ 726 /* Initialize QoS for this device */ 727 irda_init_max_qos_capabilies(&self->qos); 728 729 self->qos.baud_rate.bits = IR_9600|IR_19200|IR_38400|IR_57600| 730 IR_115200|IR_576000|IR_1152000|(IR_4000000 << 8); 731 732 self->qos.min_turn_time.bits = SMSC_IRCC2_MIN_TURN_TIME; 733 self->qos.window_size.bits = SMSC_IRCC2_WINDOW_SIZE; 734 irda_qos_bits_to_value(&self->qos); 735} 736 737/* 738 * Function smsc_ircc_init_chip(self) 739 * 740 * Init chip 741 * 742 */ 743static void smsc_ircc_init_chip(struct smsc_ircc_cb *self) 744{ 745 int iobase = self->io.fir_base; 746 747 register_bank(iobase, 0); 748 outb(IRCC_MASTER_RESET, iobase + IRCC_MASTER); 749 outb(0x00, iobase + IRCC_MASTER); 750 751 register_bank(iobase, 1); 752 outb(((inb(iobase + IRCC_SCE_CFGA) & 0x87) | IRCC_CFGA_IRDA_SIR_A), 753 iobase + IRCC_SCE_CFGA); 754 755#ifdef smsc_669 /* Uses pin 88/89 for Rx/Tx */ 756 outb(((inb(iobase + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_COM), 757 iobase + IRCC_SCE_CFGB); 758#else 759 outb(((inb(iobase + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_IR), 760 iobase + IRCC_SCE_CFGB); 761#endif 762 (void) inb(iobase + IRCC_FIFO_THRESHOLD); 763 outb(SMSC_IRCC2_FIFO_THRESHOLD, iobase + IRCC_FIFO_THRESHOLD); 764 765 register_bank(iobase, 4); 766 outb((inb(iobase + IRCC_CONTROL) & 0x30), iobase + IRCC_CONTROL); 767 768 register_bank(iobase, 0); 769 outb(0, iobase + IRCC_LCR_A); 770 771 smsc_ircc_set_sir_speed(self, SMSC_IRCC2_C_IRDA_FALLBACK_SPEED); 772 773 /* Power on device */ 774 outb(0x00, iobase + IRCC_MASTER); 775} 776 777/* 778 * Function smsc_ircc_net_ioctl (dev, rq, cmd) 779 * 780 * Process IOCTL commands for this device 781 * 782 */ 783static int smsc_ircc_net_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 784{ 785 struct if_irda_req *irq = (struct if_irda_req *) rq; 786 struct smsc_ircc_cb *self; 787 unsigned long flags; 788 int ret = 0; 789 790 IRDA_ASSERT(dev != NULL, return -1;); 791 792 self = netdev_priv(dev); 793 794 IRDA_ASSERT(self != NULL, return -1;); 795 796 IRDA_DEBUG(2, "%s(), %s, (cmd=0x%X)\n", __FUNCTION__, dev->name, cmd); 797 798 switch (cmd) { 799 case SIOCSBANDWIDTH: /* Set bandwidth */ 800 if (!capable(CAP_NET_ADMIN)) 801 ret = -EPERM; 802 else { 803 /* Make sure we are the only one touching 804 * self->io.speed and the hardware - Jean II */ 805 spin_lock_irqsave(&self->lock, flags); 806 smsc_ircc_change_speed(self, irq->ifr_baudrate); 807 spin_unlock_irqrestore(&self->lock, flags); 808 } 809 break; 810 case SIOCSMEDIABUSY: /* Set media busy */ 811 if (!capable(CAP_NET_ADMIN)) { 812 ret = -EPERM; 813 break; 814 } 815 816 irda_device_set_media_busy(self->netdev, TRUE); 817 break; 818 case SIOCGRECEIVING: /* Check if we are receiving right now */ 819 irq->ifr_receiving = smsc_ircc_is_receiving(self); 820 break; 821 #if 0 822 case SIOCSDTRRTS: 823 if (!capable(CAP_NET_ADMIN)) { 824 ret = -EPERM; 825 break; 826 } 827 smsc_ircc_sir_set_dtr_rts(dev, irq->ifr_dtr, irq->ifr_rts); 828 break; 829 #endif 830 default: 831 ret = -EOPNOTSUPP; 832 } 833 834 return ret; 835} 836 837static struct net_device_stats *smsc_ircc_net_get_stats(struct net_device *dev) 838{ 839 struct smsc_ircc_cb *self = netdev_priv(dev); 840 841 return &self->stats; 842} 843 844#if SMSC_IRCC2_C_NET_TIMEOUT 845/* 846 * Function smsc_ircc_timeout (struct net_device *dev) 847 * 848 * The networking timeout management. 849 * 850 */ 851 852static void smsc_ircc_timeout(struct net_device *dev) 853{ 854 struct smsc_ircc_cb *self = netdev_priv(dev); 855 unsigned long flags; 856 857 IRDA_WARNING("%s: transmit timed out, changing speed to: %d\n", 858 dev->name, self->io.speed); 859 spin_lock_irqsave(&self->lock, flags); 860 smsc_ircc_sir_start(self); 861 smsc_ircc_change_speed(self, self->io.speed); 862 dev->trans_start = jiffies; 863 netif_wake_queue(dev); 864 spin_unlock_irqrestore(&self->lock, flags); 865} 866#endif 867 868/* 869 * Function smsc_ircc_hard_xmit_sir (struct sk_buff *skb, struct net_device *dev) 870 * 871 * Transmits the current frame until FIFO is full, then 872 * waits until the next transmit interrupt, and continues until the 873 * frame is transmitted. 874 */ 875int smsc_ircc_hard_xmit_sir(struct sk_buff *skb, struct net_device *dev) 876{ 877 struct smsc_ircc_cb *self; 878 unsigned long flags; 879 s32 speed; 880 881 IRDA_DEBUG(1, "%s\n", __FUNCTION__); 882 883 IRDA_ASSERT(dev != NULL, return 0;); 884 885 self = netdev_priv(dev); 886 IRDA_ASSERT(self != NULL, return 0;); 887 888 netif_stop_queue(dev); 889 890 /* Make sure test of self->io.speed & speed change are atomic */ 891 spin_lock_irqsave(&self->lock, flags); 892 893 /* Check if we need to change the speed */ 894 speed = irda_get_next_speed(skb); 895 if (speed != self->io.speed && speed != -1) { 896 /* Check for empty frame */ 897 if (!skb->len) { 898 /* 899 * We send frames one by one in SIR mode (no 900 * pipelining), so at this point, if we were sending 901 * a previous frame, we just received the interrupt 902 * telling us it is finished (UART_IIR_THRI). 903 * Therefore, waiting for the transmitter to really 904 * finish draining the fifo won't take too long. 905 * And the interrupt handler is not expected to run. 906 * - Jean II */ 907 smsc_ircc_sir_wait_hw_transmitter_finish(self); 908 smsc_ircc_change_speed(self, speed); 909 spin_unlock_irqrestore(&self->lock, flags); 910 dev_kfree_skb(skb); 911 return 0; 912 } 913 self->new_speed = speed; 914 } 915 916 /* Init tx buffer */ 917 self->tx_buff.data = self->tx_buff.head; 918 919 /* Copy skb to tx_buff while wrapping, stuffing and making CRC */ 920 self->tx_buff.len = async_wrap_skb(skb, self->tx_buff.data, 921 self->tx_buff.truesize); 922 923 self->stats.tx_bytes += self->tx_buff.len; 924 925 /* Turn on transmit finished interrupt. Will fire immediately! */ 926 outb(UART_IER_THRI, self->io.sir_base + UART_IER); 927 928 spin_unlock_irqrestore(&self->lock, flags); 929 930 dev_kfree_skb(skb); 931 932 return 0; 933} 934 935/* 936 * Function smsc_ircc_set_fir_speed (self, baud) 937 * 938 * Change the speed of the device 939 * 940 */ 941static void smsc_ircc_set_fir_speed(struct smsc_ircc_cb *self, u32 speed) 942{ 943 int fir_base, ir_mode, ctrl, fast; 944 945 IRDA_ASSERT(self != NULL, return;); 946 fir_base = self->io.fir_base; 947 948 self->io.speed = speed; 949 950 switch (speed) { 951 default: 952 case 576000: 953 ir_mode = IRCC_CFGA_IRDA_HDLC; 954 ctrl = IRCC_CRC; 955 fast = 0; 956 IRDA_DEBUG(0, "%s(), handling baud of 576000\n", __FUNCTION__); 957 break; 958 case 1152000: 959 ir_mode = IRCC_CFGA_IRDA_HDLC; 960 ctrl = IRCC_1152 | IRCC_CRC; 961 fast = IRCC_LCR_A_FAST | IRCC_LCR_A_GP_DATA; 962 IRDA_DEBUG(0, "%s(), handling baud of 1152000\n", 963 __FUNCTION__); 964 break; 965 case 4000000: 966 ir_mode = IRCC_CFGA_IRDA_4PPM; 967 ctrl = IRCC_CRC; 968 fast = IRCC_LCR_A_FAST; 969 IRDA_DEBUG(0, "%s(), handling baud of 4000000\n", 970 __FUNCTION__); 971 break; 972 } 973 #if 0 974 Now in tranceiver! 975 /* This causes an interrupt */ 976 register_bank(fir_base, 0); 977 outb((inb(fir_base + IRCC_LCR_A) & 0xbf) | fast, fir_base + IRCC_LCR_A); 978 #endif 979 980 register_bank(fir_base, 1); 981 outb(((inb(fir_base + IRCC_SCE_CFGA) & IRCC_SCE_CFGA_BLOCK_CTRL_BITS_MASK) | ir_mode), fir_base + IRCC_SCE_CFGA); 982 983 register_bank(fir_base, 4); 984 outb((inb(fir_base + IRCC_CONTROL) & 0x30) | ctrl, fir_base + IRCC_CONTROL); 985} 986 987/* 988 * Function smsc_ircc_fir_start(self) 989 * 990 * Change the speed of the device 991 * 992 */ 993static void smsc_ircc_fir_start(struct smsc_ircc_cb *self) 994{ 995 struct net_device *dev; 996 int fir_base; 997 998 IRDA_DEBUG(1, "%s\n", __FUNCTION__); 999 1000 IRDA_ASSERT(self != NULL, return;); 1001 dev = self->netdev; 1002 IRDA_ASSERT(dev != NULL, return;); 1003 1004 fir_base = self->io.fir_base; 1005 1006 /* Reset everything */ 1007 1008 /* Install FIR transmit handler */ 1009 dev->hard_start_xmit = smsc_ircc_hard_xmit_fir; 1010 1011 /* Clear FIFO */ 1012 outb(inb(fir_base + IRCC_LCR_A) | IRCC_LCR_A_FIFO_RESET, fir_base + IRCC_LCR_A); 1013 1014 /* Enable interrupt */ 1015 /*outb(IRCC_IER_ACTIVE_FRAME|IRCC_IER_EOM, fir_base + IRCC_IER);*/ 1016 1017 register_bank(fir_base, 1); 1018 1019 /* Select the TX/RX interface */ 1020#ifdef SMSC_669 /* Uses pin 88/89 for Rx/Tx */ 1021 outb(((inb(fir_base + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_COM), 1022 fir_base + IRCC_SCE_CFGB); 1023#else 1024 outb(((inb(fir_base + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_IR), 1025 fir_base + IRCC_SCE_CFGB); 1026#endif 1027 (void) inb(fir_base + IRCC_FIFO_THRESHOLD); 1028 1029 /* Enable SCE interrupts */ 1030 outb(0, fir_base + IRCC_MASTER); 1031 register_bank(fir_base, 0); 1032 outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, fir_base + IRCC_IER); 1033 outb(IRCC_MASTER_INT_EN, fir_base + IRCC_MASTER); 1034} 1035 1036/* 1037 * Function smsc_ircc_fir_stop(self, baud) 1038 * 1039 * Change the speed of the device 1040 * 1041 */ 1042static void smsc_ircc_fir_stop(struct smsc_ircc_cb *self) 1043{ 1044 int fir_base; 1045 1046 IRDA_DEBUG(1, "%s\n", __FUNCTION__); 1047 1048 IRDA_ASSERT(self != NULL, return;); 1049 1050 fir_base = self->io.fir_base; 1051 register_bank(fir_base, 0); 1052 /*outb(IRCC_MASTER_RESET, fir_base + IRCC_MASTER);*/ 1053 outb(inb(fir_base + IRCC_LCR_B) & IRCC_LCR_B_SIP_ENABLE, fir_base + IRCC_LCR_B); 1054} 1055 1056 1057/* 1058 * Function smsc_ircc_change_speed(self, baud) 1059 * 1060 * Change the speed of the device 1061 * 1062 * This function *must* be called with spinlock held, because it may 1063 * be called from the irq handler. - Jean II 1064 */ 1065static void smsc_ircc_change_speed(struct smsc_ircc_cb *self, u32 speed) 1066{ 1067 struct net_device *dev; 1068 int last_speed_was_sir; 1069 1070 IRDA_DEBUG(0, "%s() changing speed to: %d\n", __FUNCTION__, speed); 1071 1072 IRDA_ASSERT(self != NULL, return;); 1073 dev = self->netdev; 1074 1075 last_speed_was_sir = self->io.speed <= SMSC_IRCC2_MAX_SIR_SPEED; 1076 1077 #if 0 1078 /* Temp Hack */ 1079 speed= 1152000; 1080 self->io.speed = speed; 1081 last_speed_was_sir = 0; 1082 smsc_ircc_fir_start(self); 1083 #endif 1084 1085 if (self->io.speed == 0) 1086 smsc_ircc_sir_start(self); 1087 1088 #if 0 1089 if (!last_speed_was_sir) speed = self->io.speed; 1090 #endif 1091 1092 if (self->io.speed != speed) 1093 smsc_ircc_set_transceiver_for_speed(self, speed); 1094 1095 self->io.speed = speed; 1096 1097 if (speed <= SMSC_IRCC2_MAX_SIR_SPEED) { 1098 if (!last_speed_was_sir) { 1099 smsc_ircc_fir_stop(self); 1100 smsc_ircc_sir_start(self); 1101 } 1102 smsc_ircc_set_sir_speed(self, speed); 1103 } else { 1104 if (last_speed_was_sir) { 1105 #if SMSC_IRCC2_C_SIR_STOP 1106 smsc_ircc_sir_stop(self); 1107 #endif 1108 smsc_ircc_fir_start(self); 1109 } 1110 smsc_ircc_set_fir_speed(self, speed); 1111 1112 #if 0 1113 self->tx_buff.len = 10; 1114 self->tx_buff.data = self->tx_buff.head; 1115 1116 smsc_ircc_dma_xmit(self, 4000); 1117 #endif 1118 /* Be ready for incoming frames */ 1119 smsc_ircc_dma_receive(self); 1120 } 1121 1122 netif_wake_queue(dev); 1123} 1124 1125/* 1126 * Function smsc_ircc_set_sir_speed (self, speed) 1127 * 1128 * Set speed of IrDA port to specified baudrate 1129 * 1130 */ 1131void smsc_ircc_set_sir_speed(struct smsc_ircc_cb *self, __u32 speed) 1132{ 1133 int iobase; 1134 int fcr; /* FIFO control reg */ 1135 int lcr; /* Line control reg */ 1136 int divisor; 1137 1138 IRDA_DEBUG(0, "%s(), Setting speed to: %d\n", __FUNCTION__, speed); 1139 1140 IRDA_ASSERT(self != NULL, return;); 1141 iobase = self->io.sir_base; 1142 1143 /* Update accounting for new speed */ 1144 self->io.speed = speed; 1145 1146 /* Turn off interrupts */ 1147 outb(0, iobase + UART_IER); 1148 1149 divisor = SMSC_IRCC2_MAX_SIR_SPEED / speed; 1150 1151 fcr = UART_FCR_ENABLE_FIFO; 1152 1153 /* 1154 * Use trigger level 1 to avoid 3 ms. timeout delay at 9600 bps, and 1155 * almost 1,7 ms at 19200 bps. At speeds above that we can just forget 1156 * about this timeout since it will always be fast enough. 1157 */ 1158 fcr |= self->io.speed < 38400 ? 1159 UART_FCR_TRIGGER_1 : UART_FCR_TRIGGER_14; 1160 1161 /* IrDA ports use 8N1 */ 1162 lcr = UART_LCR_WLEN8; 1163 1164 outb(UART_LCR_DLAB | lcr, iobase + UART_LCR); /* Set DLAB */ 1165 outb(divisor & 0xff, iobase + UART_DLL); /* Set speed */ 1166 outb(divisor >> 8, iobase + UART_DLM); 1167 outb(lcr, iobase + UART_LCR); /* Set 8N1 */ 1168 outb(fcr, iobase + UART_FCR); /* Enable FIFO's */ 1169 1170 /* Turn on interrups */ 1171 outb(UART_IER_RLSI | UART_IER_RDI | UART_IER_THRI, iobase + UART_IER); 1172 1173 IRDA_DEBUG(2, "%s() speed changed to: %d\n", __FUNCTION__, speed); 1174} 1175 1176 1177/* 1178 * Function smsc_ircc_hard_xmit_fir (skb, dev) 1179 * 1180 * Transmit the frame! 1181 * 1182 */ 1183static int smsc_ircc_hard_xmit_fir(struct sk_buff *skb, struct net_device *dev) 1184{ 1185 struct smsc_ircc_cb *self; 1186 unsigned long flags; 1187 s32 speed; 1188 int mtt; 1189 1190 IRDA_ASSERT(dev != NULL, return 0;); 1191 self = netdev_priv(dev); 1192 IRDA_ASSERT(self != NULL, return 0;); 1193 1194 netif_stop_queue(dev); 1195 1196 /* Make sure test of self->io.speed & speed change are atomic */ 1197 spin_lock_irqsave(&self->lock, flags); 1198 1199 /* Check if we need to change the speed after this frame */ 1200 speed = irda_get_next_speed(skb); 1201 if (speed != self->io.speed && speed != -1) { 1202 /* Check for empty frame */ 1203 if (!skb->len) { 1204 /* Note : you should make sure that speed changes 1205 * are not going to corrupt any outgoing frame. 1206 * Look at nsc-ircc for the gory details - Jean II */ 1207 smsc_ircc_change_speed(self, speed); 1208 spin_unlock_irqrestore(&self->lock, flags); 1209 dev_kfree_skb(skb); 1210 return 0; 1211 } 1212 1213 self->new_speed = speed; 1214 } 1215 1216 skb_copy_from_linear_data(skb, self->tx_buff.head, skb->len); 1217 1218 self->tx_buff.len = skb->len; 1219 self->tx_buff.data = self->tx_buff.head; 1220 1221 mtt = irda_get_mtt(skb); 1222 if (mtt) { 1223 int bofs; 1224 1225 /* 1226 * Compute how many BOFs (STA or PA's) we need to waste the 1227 * min turn time given the speed of the link. 1228 */ 1229 bofs = mtt * (self->io.speed / 1000) / 8000; 1230 if (bofs > 4095) 1231 bofs = 4095; 1232 1233 smsc_ircc_dma_xmit(self, bofs); 1234 } else { 1235 /* Transmit frame */ 1236 smsc_ircc_dma_xmit(self, 0); 1237 } 1238 1239 spin_unlock_irqrestore(&self->lock, flags); 1240 dev_kfree_skb(skb); 1241 1242 return 0; 1243} 1244 1245/* 1246 * Function smsc_ircc_dma_xmit (self, bofs) 1247 * 1248 * Transmit data using DMA 1249 * 1250 */ 1251static void smsc_ircc_dma_xmit(struct smsc_ircc_cb *self, int bofs) 1252{ 1253 int iobase = self->io.fir_base; 1254 u8 ctrl; 1255 1256 IRDA_DEBUG(3, "%s\n", __FUNCTION__); 1257 /* Disable Rx */ 1258 register_bank(iobase, 0); 1259 outb(0x00, iobase + IRCC_LCR_B); 1260 register_bank(iobase, 1); 1261 outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE, 1262 iobase + IRCC_SCE_CFGB); 1263 1264 self->io.direction = IO_XMIT; 1265 1266 /* Set BOF additional count for generating the min turn time */ 1267 register_bank(iobase, 4); 1268 outb(bofs & 0xff, iobase + IRCC_BOF_COUNT_LO); 1269 ctrl = inb(iobase + IRCC_CONTROL) & 0xf0; 1270 outb(ctrl | ((bofs >> 8) & 0x0f), iobase + IRCC_BOF_COUNT_HI); 1271 1272 /* Set max Tx frame size */ 1273 outb(self->tx_buff.len >> 8, iobase + IRCC_TX_SIZE_HI); 1274 outb(self->tx_buff.len & 0xff, iobase + IRCC_TX_SIZE_LO); 1275 1276 /*outb(UART_MCR_OUT2, self->io.sir_base + UART_MCR);*/ 1277 1278 /* Enable burst mode chip Tx DMA */ 1279 register_bank(iobase, 1); 1280 outb(inb(iobase + IRCC_SCE_CFGB) | IRCC_CFGB_DMA_ENABLE | 1281 IRCC_CFGB_DMA_BURST, iobase + IRCC_SCE_CFGB); 1282 1283 /* Setup DMA controller (must be done after enabling chip DMA) */ 1284 irda_setup_dma(self->io.dma, self->tx_buff_dma, self->tx_buff.len, 1285 DMA_TX_MODE); 1286 1287 /* Enable interrupt */ 1288 1289 register_bank(iobase, 0); 1290 outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase + IRCC_IER); 1291 outb(IRCC_MASTER_INT_EN, iobase + IRCC_MASTER); 1292 1293 /* Enable transmit */ 1294 outb(IRCC_LCR_B_SCE_TRANSMIT | IRCC_LCR_B_SIP_ENABLE, iobase + IRCC_LCR_B); 1295} 1296 1297/* 1298 * Function smsc_ircc_dma_xmit_complete (self) 1299 * 1300 * The transfer of a frame in finished. This function will only be called 1301 * by the interrupt handler 1302 * 1303 */ 1304static void smsc_ircc_dma_xmit_complete(struct smsc_ircc_cb *self) 1305{ 1306 int iobase = self->io.fir_base; 1307 1308 IRDA_DEBUG(3, "%s\n", __FUNCTION__); 1309 register_bank(iobase, 1); 1310 outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE, 1311 iobase + IRCC_SCE_CFGB); 1312 1313 /* Check for underrun! */ 1314 register_bank(iobase, 0); 1315 if (inb(iobase + IRCC_LSR) & IRCC_LSR_UNDERRUN) { 1316 self->stats.tx_errors++; 1317 self->stats.tx_fifo_errors++; 1318 1319 /* Reset error condition */ 1320 register_bank(iobase, 0); 1321 outb(IRCC_MASTER_ERROR_RESET, iobase + IRCC_MASTER); 1322 outb(0x00, iobase + IRCC_MASTER); 1323 } else { 1324 self->stats.tx_packets++; 1325 self->stats.tx_bytes += self->tx_buff.len; 1326 } 1327 1328 /* Check if it's time to change the speed */ 1329 if (self->new_speed) { 1330 smsc_ircc_change_speed(self, self->new_speed); 1331 self->new_speed = 0; 1332 } 1333 1334 netif_wake_queue(self->netdev); 1335} 1336 1337/* 1338 * Function smsc_ircc_dma_receive(self) 1339 * 1340 * Get ready for receiving a frame. The device will initiate a DMA 1341 * if it starts to receive a frame. 1342 * 1343 */ 1344static int smsc_ircc_dma_receive(struct smsc_ircc_cb *self) 1345{ 1346 int iobase = self->io.fir_base; 1347 1348 /* Disable Tx */ 1349 register_bank(iobase, 0); 1350 outb(0x00, iobase + IRCC_LCR_B); 1351 1352 /* Turn off chip DMA */ 1353 register_bank(iobase, 1); 1354 outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE, 1355 iobase + IRCC_SCE_CFGB); 1356 1357 self->io.direction = IO_RECV; 1358 self->rx_buff.data = self->rx_buff.head; 1359 1360 /* Set max Rx frame size */ 1361 register_bank(iobase, 4); 1362 outb((2050 >> 8) & 0x0f, iobase + IRCC_RX_SIZE_HI); 1363 outb(2050 & 0xff, iobase + IRCC_RX_SIZE_LO); 1364 1365 /* Setup DMA controller */ 1366 irda_setup_dma(self->io.dma, self->rx_buff_dma, self->rx_buff.truesize, 1367 DMA_RX_MODE); 1368 1369 /* Enable burst mode chip Rx DMA */ 1370 register_bank(iobase, 1); 1371 outb(inb(iobase + IRCC_SCE_CFGB) | IRCC_CFGB_DMA_ENABLE | 1372 IRCC_CFGB_DMA_BURST, iobase + IRCC_SCE_CFGB); 1373 1374 /* Enable interrupt */ 1375 register_bank(iobase, 0); 1376 outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase + IRCC_IER); 1377 outb(IRCC_MASTER_INT_EN, iobase + IRCC_MASTER); 1378 1379 /* Enable receiver */ 1380 register_bank(iobase, 0); 1381 outb(IRCC_LCR_B_SCE_RECEIVE | IRCC_LCR_B_SIP_ENABLE, 1382 iobase + IRCC_LCR_B); 1383 1384 return 0; 1385} 1386 1387/* 1388 * Function smsc_ircc_dma_receive_complete(self) 1389 * 1390 * Finished with receiving frames 1391 * 1392 */ 1393static void smsc_ircc_dma_receive_complete(struct smsc_ircc_cb *self) 1394{ 1395 struct sk_buff *skb; 1396 int len, msgcnt, lsr; 1397 int iobase = self->io.fir_base; 1398 1399 register_bank(iobase, 0); 1400 1401 IRDA_DEBUG(3, "%s\n", __FUNCTION__); 1402 register_bank(iobase, 0); 1403 outb(inb(iobase + IRCC_LSAR) & ~IRCC_LSAR_ADDRESS_MASK, iobase + IRCC_LSAR); 1404 lsr= inb(iobase + IRCC_LSR); 1405 msgcnt = inb(iobase + IRCC_LCR_B) & 0x08; 1406 1407 IRDA_DEBUG(2, "%s: dma count = %d\n", __FUNCTION__, 1408 get_dma_residue(self->io.dma)); 1409 1410 len = self->rx_buff.truesize - get_dma_residue(self->io.dma); 1411 1412 /* Look for errors */ 1413 if (lsr & (IRCC_LSR_FRAME_ERROR | IRCC_LSR_CRC_ERROR | IRCC_LSR_SIZE_ERROR)) { 1414 self->stats.rx_errors++; 1415 if (lsr & IRCC_LSR_FRAME_ERROR) 1416 self->stats.rx_frame_errors++; 1417 if (lsr & IRCC_LSR_CRC_ERROR) 1418 self->stats.rx_crc_errors++; 1419 if (lsr & IRCC_LSR_SIZE_ERROR) 1420 self->stats.rx_length_errors++; 1421 if (lsr & (IRCC_LSR_UNDERRUN | IRCC_LSR_OVERRUN)) 1422 self->stats.rx_length_errors++; 1423 return; 1424 } 1425 1426 /* Remove CRC */ 1427 len -= self->io.speed < 4000000 ? 2 : 4; 1428 1429 if (len < 2 || len > 2050) { 1430 IRDA_WARNING("%s(), bogus len=%d\n", __FUNCTION__, len); 1431 return; 1432 } 1433 IRDA_DEBUG(2, "%s: msgcnt = %d, len=%d\n", __FUNCTION__, msgcnt, len); 1434 1435 skb = dev_alloc_skb(len + 1); 1436 if (!skb) { 1437 IRDA_WARNING("%s(), memory squeeze, dropping frame.\n", 1438 __FUNCTION__); 1439 return; 1440 } 1441 /* Make sure IP header gets aligned */ 1442 skb_reserve(skb, 1); 1443 1444 memcpy(skb_put(skb, len), self->rx_buff.data, len); 1445 self->stats.rx_packets++; 1446 self->stats.rx_bytes += len; 1447 1448 skb->dev = self->netdev; 1449 skb_reset_mac_header(skb); 1450 skb->protocol = htons(ETH_P_IRDA); 1451 netif_rx(skb); 1452} 1453 1454/* 1455 * Function smsc_ircc_sir_receive (self) 1456 * 1457 * Receive one frame from the infrared port 1458 * 1459 */ 1460static void smsc_ircc_sir_receive(struct smsc_ircc_cb *self) 1461{ 1462 int boguscount = 0; 1463 int iobase; 1464 1465 IRDA_ASSERT(self != NULL, return;); 1466 1467 iobase = self->io.sir_base; 1468 1469 /* 1470 * Receive all characters in Rx FIFO, unwrap and unstuff them. 1471 * async_unwrap_char will deliver all found frames 1472 */ 1473 do { 1474 async_unwrap_char(self->netdev, &self->stats, &self->rx_buff, 1475 inb(iobase + UART_RX)); 1476 1477 /* Make sure we don't stay here to long */ 1478 if (boguscount++ > 32) { 1479 IRDA_DEBUG(2, "%s(), breaking!\n", __FUNCTION__); 1480 break; 1481 } 1482 } while (inb(iobase + UART_LSR) & UART_LSR_DR); 1483} 1484 1485 1486/* 1487 * Function smsc_ircc_interrupt (irq, dev_id, regs) 1488 * 1489 * An interrupt from the chip has arrived. Time to do some work 1490 * 1491 */ 1492static irqreturn_t smsc_ircc_interrupt(int irq, void *dev_id) 1493{ 1494 struct net_device *dev = (struct net_device *) dev_id; 1495 struct smsc_ircc_cb *self; 1496 int iobase, iir, lcra, lsr; 1497 irqreturn_t ret = IRQ_NONE; 1498 1499 if (dev == NULL) { 1500 printk(KERN_WARNING "%s: irq %d for unknown device.\n", 1501 driver_name, irq); 1502 goto irq_ret; 1503 } 1504 1505 self = netdev_priv(dev); 1506 IRDA_ASSERT(self != NULL, return IRQ_NONE;); 1507 1508 /* Serialise the interrupt handler in various CPUs, stop Tx path */ 1509 spin_lock(&self->lock); 1510 1511 /* Check if we should use the SIR interrupt handler */ 1512 if (self->io.speed <= SMSC_IRCC2_MAX_SIR_SPEED) { 1513 ret = smsc_ircc_interrupt_sir(dev); 1514 goto irq_ret_unlock; 1515 } 1516 1517 iobase = self->io.fir_base; 1518 1519 register_bank(iobase, 0); 1520 iir = inb(iobase + IRCC_IIR); 1521 if (iir == 0) 1522 goto irq_ret_unlock; 1523 ret = IRQ_HANDLED; 1524 1525 /* Disable interrupts */ 1526 outb(0, iobase + IRCC_IER); 1527 lcra = inb(iobase + IRCC_LCR_A); 1528 lsr = inb(iobase + IRCC_LSR); 1529 1530 IRDA_DEBUG(2, "%s(), iir = 0x%02x\n", __FUNCTION__, iir); 1531 1532 if (iir & IRCC_IIR_EOM) { 1533 if (self->io.direction == IO_RECV) 1534 smsc_ircc_dma_receive_complete(self); 1535 else 1536 smsc_ircc_dma_xmit_complete(self); 1537 1538 smsc_ircc_dma_receive(self); 1539 } 1540 1541 if (iir & IRCC_IIR_ACTIVE_FRAME) { 1542 /*printk(KERN_WARNING "%s(): Active Frame\n", __FUNCTION__);*/ 1543 } 1544 1545 /* Enable interrupts again */ 1546 1547 register_bank(iobase, 0); 1548 outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase + IRCC_IER); 1549 1550 irq_ret_unlock: 1551 spin_unlock(&self->lock); 1552 irq_ret: 1553 return ret; 1554} 1555 1556/* 1557 * Function irport_interrupt_sir (irq, dev_id) 1558 * 1559 * Interrupt handler for SIR modes 1560 */ 1561static irqreturn_t smsc_ircc_interrupt_sir(struct net_device *dev) 1562{ 1563 struct smsc_ircc_cb *self = netdev_priv(dev); 1564 int boguscount = 0; 1565 int iobase; 1566 int iir, lsr; 1567 1568 /* Already locked comming here in smsc_ircc_interrupt() */ 1569 /*spin_lock(&self->lock);*/ 1570 1571 iobase = self->io.sir_base; 1572 1573 iir = inb(iobase + UART_IIR) & UART_IIR_ID; 1574 if (iir == 0) 1575 return IRQ_NONE; 1576 while (iir) { 1577 /* Clear interrupt */ 1578 lsr = inb(iobase + UART_LSR); 1579 1580 IRDA_DEBUG(4, "%s(), iir=%02x, lsr=%02x, iobase=%#x\n", 1581 __FUNCTION__, iir, lsr, iobase); 1582 1583 switch (iir) { 1584 case UART_IIR_RLSI: 1585 IRDA_DEBUG(2, "%s(), RLSI\n", __FUNCTION__); 1586 break; 1587 case UART_IIR_RDI: 1588 /* Receive interrupt */ 1589 smsc_ircc_sir_receive(self); 1590 break; 1591 case UART_IIR_THRI: 1592 if (lsr & UART_LSR_THRE) 1593 /* Transmitter ready for data */ 1594 smsc_ircc_sir_write_wakeup(self); 1595 break; 1596 default: 1597 IRDA_DEBUG(0, "%s(), unhandled IIR=%#x\n", 1598 __FUNCTION__, iir); 1599 break; 1600 } 1601 1602 /* Make sure we don't stay here to long */ 1603 if (boguscount++ > 100) 1604 break; 1605 1606 iir = inb(iobase + UART_IIR) & UART_IIR_ID; 1607 } 1608 /*spin_unlock(&self->lock);*/ 1609 return IRQ_HANDLED; 1610} 1611 1612 1613 1614static int smsc_ircc_request_irq(struct smsc_ircc_cb *self) 1615{ 1616 int error; 1617 1618 error = request_irq(self->io.irq, smsc_ircc_interrupt, 0, 1619 self->netdev->name, self->netdev); 1620 if (error) 1621 IRDA_DEBUG(0, "%s(), unable to allocate irq=%d, err=%d\n", 1622 __FUNCTION__, self->io.irq, error); 1623 1624 return error; 1625} 1626 1627static void smsc_ircc_start_interrupts(struct smsc_ircc_cb *self) 1628{ 1629 unsigned long flags; 1630 1631 spin_lock_irqsave(&self->lock, flags); 1632 1633 self->io.speed = 0; 1634 smsc_ircc_change_speed(self, SMSC_IRCC2_C_IRDA_FALLBACK_SPEED); 1635 1636 spin_unlock_irqrestore(&self->lock, flags); 1637} 1638 1639static void smsc_ircc_stop_interrupts(struct smsc_ircc_cb *self) 1640{ 1641 int iobase = self->io.fir_base; 1642 unsigned long flags; 1643 1644 spin_lock_irqsave(&self->lock, flags); 1645 1646 register_bank(iobase, 0); 1647 outb(0, iobase + IRCC_IER); 1648 outb(IRCC_MASTER_RESET, iobase + IRCC_MASTER); 1649 outb(0x00, iobase + IRCC_MASTER); 1650 1651 spin_unlock_irqrestore(&self->lock, flags); 1652} 1653 1654 1655/* 1656 * Function smsc_ircc_net_open (dev) 1657 * 1658 * Start the device 1659 * 1660 */ 1661static int smsc_ircc_net_open(struct net_device *dev) 1662{ 1663 struct smsc_ircc_cb *self; 1664 char hwname[16]; 1665 1666 IRDA_DEBUG(1, "%s\n", __FUNCTION__); 1667 1668 IRDA_ASSERT(dev != NULL, return -1;); 1669 self = netdev_priv(dev); 1670 IRDA_ASSERT(self != NULL, return 0;); 1671 1672 if (self->io.suspended) { 1673 IRDA_DEBUG(0, "%s(), device is suspended\n", __FUNCTION__); 1674 return -EAGAIN; 1675 } 1676 1677 if (request_irq(self->io.irq, smsc_ircc_interrupt, 0, dev->name, 1678 (void *) dev)) { 1679 IRDA_DEBUG(0, "%s(), unable to allocate irq=%d\n", 1680 __FUNCTION__, self->io.irq); 1681 return -EAGAIN; 1682 } 1683 1684 smsc_ircc_start_interrupts(self); 1685 1686 /* Give self a hardware name */ 1687 /* It would be cool to offer the chip revision here - Jean II */ 1688 sprintf(hwname, "SMSC @ 0x%03x", self->io.fir_base); 1689 1690 /* 1691 * Open new IrLAP layer instance, now that everything should be 1692 * initialized properly 1693 */ 1694 self->irlap = irlap_open(dev, &self->qos, hwname); 1695 1696 /* 1697 * Always allocate the DMA channel after the IRQ, 1698 * and clean up on failure. 1699 */ 1700 if (request_dma(self->io.dma, dev->name)) { 1701 smsc_ircc_net_close(dev); 1702 1703 IRDA_WARNING("%s(), unable to allocate DMA=%d\n", 1704 __FUNCTION__, self->io.dma); 1705 return -EAGAIN; 1706 } 1707 1708 netif_start_queue(dev); 1709 1710 return 0; 1711} 1712 1713/* 1714 * Function smsc_ircc_net_close (dev) 1715 * 1716 * Stop the device 1717 * 1718 */ 1719static int smsc_ircc_net_close(struct net_device *dev) 1720{ 1721 struct smsc_ircc_cb *self; 1722 1723 IRDA_DEBUG(1, "%s\n", __FUNCTION__); 1724 1725 IRDA_ASSERT(dev != NULL, return -1;); 1726 self = netdev_priv(dev); 1727 IRDA_ASSERT(self != NULL, return 0;); 1728 1729 /* Stop device */ 1730 netif_stop_queue(dev); 1731 1732 /* Stop and remove instance of IrLAP */ 1733 if (self->irlap) 1734 irlap_close(self->irlap); 1735 self->irlap = NULL; 1736 1737 smsc_ircc_stop_interrupts(self); 1738 1739 /* if we are called from smsc_ircc_resume we don't have IRQ reserved */ 1740 if (!self->io.suspended) 1741 free_irq(self->io.irq, dev); 1742 1743 disable_dma(self->io.dma); 1744 free_dma(self->io.dma); 1745 1746 return 0; 1747} 1748 1749static int smsc_ircc_suspend(struct platform_device *dev, pm_message_t state) 1750{ 1751 struct smsc_ircc_cb *self = platform_get_drvdata(dev); 1752 1753 if (!self->io.suspended) { 1754 IRDA_DEBUG(1, "%s, Suspending\n", driver_name); 1755 1756 rtnl_lock(); 1757 if (netif_running(self->netdev)) { 1758 netif_device_detach(self->netdev); 1759 smsc_ircc_stop_interrupts(self); 1760 free_irq(self->io.irq, self->netdev); 1761 disable_dma(self->io.dma); 1762 } 1763 self->io.suspended = 1; 1764 rtnl_unlock(); 1765 } 1766 1767 return 0; 1768} 1769 1770static int smsc_ircc_resume(struct platform_device *dev) 1771{ 1772 struct smsc_ircc_cb *self = platform_get_drvdata(dev); 1773 1774 if (self->io.suspended) { 1775 IRDA_DEBUG(1, "%s, Waking up\n", driver_name); 1776 1777 rtnl_lock(); 1778 smsc_ircc_init_chip(self); 1779 if (netif_running(self->netdev)) { 1780 if (smsc_ircc_request_irq(self)) { 1781 /* 1782 * Don't fail resume process, just kill this 1783 * network interface 1784 */ 1785 unregister_netdevice(self->netdev); 1786 } else { 1787 enable_dma(self->io.dma); 1788 smsc_ircc_start_interrupts(self); 1789 netif_device_attach(self->netdev); 1790 } 1791 } 1792 self->io.suspended = 0; 1793 rtnl_unlock(); 1794 } 1795 return 0; 1796} 1797 1798/* 1799 * Function smsc_ircc_close (self) 1800 * 1801 * Close driver instance 1802 * 1803 */ 1804static int __exit smsc_ircc_close(struct smsc_ircc_cb *self) 1805{ 1806 IRDA_DEBUG(1, "%s\n", __FUNCTION__); 1807 1808 IRDA_ASSERT(self != NULL, return -1;); 1809 1810 platform_device_unregister(self->pldev); 1811 1812 /* Remove netdevice */ 1813 unregister_netdev(self->netdev); 1814 1815 smsc_ircc_stop_interrupts(self); 1816 1817 /* Release the PORTS that this driver is using */ 1818 IRDA_DEBUG(0, "%s(), releasing 0x%03x\n", __FUNCTION__, 1819 self->io.fir_base); 1820 1821 release_region(self->io.fir_base, self->io.fir_ext); 1822 1823 IRDA_DEBUG(0, "%s(), releasing 0x%03x\n", __FUNCTION__, 1824 self->io.sir_base); 1825 1826 release_region(self->io.sir_base, self->io.sir_ext); 1827 1828 if (self->tx_buff.head) 1829 dma_free_coherent(NULL, self->tx_buff.truesize, 1830 self->tx_buff.head, self->tx_buff_dma); 1831 1832 if (self->rx_buff.head) 1833 dma_free_coherent(NULL, self->rx_buff.truesize, 1834 self->rx_buff.head, self->rx_buff_dma); 1835 1836 free_netdev(self->netdev); 1837 1838 return 0; 1839} 1840 1841static void __exit smsc_ircc_cleanup(void) 1842{ 1843 int i; 1844 1845 IRDA_DEBUG(1, "%s\n", __FUNCTION__); 1846 1847 for (i = 0; i < 2; i++) { 1848 if (dev_self[i]) 1849 smsc_ircc_close(dev_self[i]); 1850 } 1851 1852 if (pnp_driver_registered) 1853 pnp_unregister_driver(&smsc_ircc_pnp_driver); 1854 1855 platform_driver_unregister(&smsc_ircc_driver); 1856} 1857 1858/* 1859 * Start SIR operations 1860 * 1861 * This function *must* be called with spinlock held, because it may 1862 * be called from the irq handler (via smsc_ircc_change_speed()). - Jean II 1863 */ 1864void smsc_ircc_sir_start(struct smsc_ircc_cb *self) 1865{ 1866 struct net_device *dev; 1867 int fir_base, sir_base; 1868 1869 IRDA_DEBUG(3, "%s\n", __FUNCTION__); 1870 1871 IRDA_ASSERT(self != NULL, return;); 1872 dev = self->netdev; 1873 IRDA_ASSERT(dev != NULL, return;); 1874 dev->hard_start_xmit = &smsc_ircc_hard_xmit_sir; 1875 1876 fir_base = self->io.fir_base; 1877 sir_base = self->io.sir_base; 1878 1879 /* Reset everything */ 1880 outb(IRCC_MASTER_RESET, fir_base + IRCC_MASTER); 1881 1882 #if SMSC_IRCC2_C_SIR_STOP 1883 /*smsc_ircc_sir_stop(self);*/ 1884 #endif 1885 1886 register_bank(fir_base, 1); 1887 outb(((inb(fir_base + IRCC_SCE_CFGA) & IRCC_SCE_CFGA_BLOCK_CTRL_BITS_MASK) | IRCC_CFGA_IRDA_SIR_A), fir_base + IRCC_SCE_CFGA); 1888 1889 /* Initialize UART */ 1890 outb(UART_LCR_WLEN8, sir_base + UART_LCR); /* Reset DLAB */ 1891 outb((UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2), sir_base + UART_MCR); 1892 1893 /* Turn on interrups */ 1894 outb(UART_IER_RLSI | UART_IER_RDI |UART_IER_THRI, sir_base + UART_IER); 1895 1896 IRDA_DEBUG(3, "%s() - exit\n", __FUNCTION__); 1897 1898 outb(0x00, fir_base + IRCC_MASTER); 1899} 1900 1901#if SMSC_IRCC2_C_SIR_STOP 1902void smsc_ircc_sir_stop(struct smsc_ircc_cb *self) 1903{ 1904 int iobase; 1905 1906 IRDA_DEBUG(3, "%s\n", __FUNCTION__); 1907 iobase = self->io.sir_base; 1908 1909 /* Reset UART */ 1910 outb(0, iobase + UART_MCR); 1911 1912 /* Turn off interrupts */ 1913 outb(0, iobase + UART_IER); 1914} 1915#endif 1916 1917/* 1918 * Function smsc_sir_write_wakeup (self) 1919 * 1920 * Called by the SIR interrupt handler when there's room for more data. 1921 * If we have more packets to send, we send them here. 1922 * 1923 */ 1924static void smsc_ircc_sir_write_wakeup(struct smsc_ircc_cb *self) 1925{ 1926 int actual = 0; 1927 int iobase; 1928 int fcr; 1929 1930 IRDA_ASSERT(self != NULL, return;); 1931 1932 IRDA_DEBUG(4, "%s\n", __FUNCTION__); 1933 1934 iobase = self->io.sir_base; 1935 1936 /* Finished with frame? */ 1937 if (self->tx_buff.len > 0) { 1938 /* Write data left in transmit buffer */ 1939 actual = smsc_ircc_sir_write(iobase, self->io.fifo_size, 1940 self->tx_buff.data, self->tx_buff.len); 1941 self->tx_buff.data += actual; 1942 self->tx_buff.len -= actual; 1943 } else { 1944 1945 /*if (self->tx_buff.len ==0) {*/ 1946 1947 /* 1948 * Now serial buffer is almost free & we can start 1949 * transmission of another packet. But first we must check 1950 * if we need to change the speed of the hardware 1951 */ 1952 if (self->new_speed) { 1953 IRDA_DEBUG(5, "%s(), Changing speed to %d.\n", 1954 __FUNCTION__, self->new_speed); 1955 smsc_ircc_sir_wait_hw_transmitter_finish(self); 1956 smsc_ircc_change_speed(self, self->new_speed); 1957 self->new_speed = 0; 1958 } else { 1959 /* Tell network layer that we want more frames */ 1960 netif_wake_queue(self->netdev); 1961 } 1962 self->stats.tx_packets++; 1963 1964 if (self->io.speed <= 115200) { 1965 /* 1966 * Reset Rx FIFO to make sure that all reflected transmit data 1967 * is discarded. This is needed for half duplex operation 1968 */ 1969 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR; 1970 fcr |= self->io.speed < 38400 ? 1971 UART_FCR_TRIGGER_1 : UART_FCR_TRIGGER_14; 1972 1973 outb(fcr, iobase + UART_FCR); 1974 1975 /* Turn on receive interrupts */ 1976 outb(UART_IER_RDI, iobase + UART_IER); 1977 } 1978 } 1979} 1980 1981/* 1982 * Function smsc_ircc_sir_write (iobase, fifo_size, buf, len) 1983 * 1984 * Fill Tx FIFO with transmit data 1985 * 1986 */ 1987static int smsc_ircc_sir_write(int iobase, int fifo_size, __u8 *buf, int len) 1988{ 1989 int actual = 0; 1990 1991 /* Tx FIFO should be empty! */ 1992 if (!(inb(iobase + UART_LSR) & UART_LSR_THRE)) { 1993 IRDA_WARNING("%s(), failed, fifo not empty!\n", __FUNCTION__); 1994 return 0; 1995 } 1996 1997 /* Fill FIFO with current frame */ 1998 while (fifo_size-- > 0 && actual < len) { 1999 /* Transmit next byte */ 2000 outb(buf[actual], iobase + UART_TX); 2001 actual++; 2002 } 2003 return actual; 2004} 2005 2006/* 2007 * Function smsc_ircc_is_receiving (self) 2008 * 2009 * Returns true is we are currently receiving data 2010 * 2011 */ 2012static int smsc_ircc_is_receiving(struct smsc_ircc_cb *self) 2013{ 2014 return (self->rx_buff.state != OUTSIDE_FRAME); 2015} 2016 2017 2018/* 2019 * Function smsc_ircc_probe_transceiver(self) 2020 * 2021 * Tries to find the used Transceiver 2022 * 2023 */ 2024static void smsc_ircc_probe_transceiver(struct smsc_ircc_cb *self) 2025{ 2026 unsigned int i; 2027 2028 IRDA_ASSERT(self != NULL, return;); 2029 2030 for (i = 0; smsc_transceivers[i].name != NULL; i++) 2031 if (smsc_transceivers[i].probe(self->io.fir_base)) { 2032 IRDA_MESSAGE(" %s transceiver found\n", 2033 smsc_transceivers[i].name); 2034 self->transceiver= i + 1; 2035 return; 2036 } 2037 2038 IRDA_MESSAGE("No transceiver found. Defaulting to %s\n", 2039 smsc_transceivers[SMSC_IRCC2_C_DEFAULT_TRANSCEIVER].name); 2040 2041 self->transceiver = SMSC_IRCC2_C_DEFAULT_TRANSCEIVER; 2042} 2043 2044 2045/* 2046 * Function smsc_ircc_set_transceiver_for_speed(self, speed) 2047 * 2048 * Set the transceiver according to the speed 2049 * 2050 */ 2051static void smsc_ircc_set_transceiver_for_speed(struct smsc_ircc_cb *self, u32 speed) 2052{ 2053 unsigned int trx; 2054 2055 trx = self->transceiver; 2056 if (trx > 0) 2057 smsc_transceivers[trx - 1].set_for_speed(self->io.fir_base, speed); 2058} 2059 2060/* 2061 * Function smsc_ircc_wait_hw_transmitter_finish () 2062 * 2063 * Wait for the real end of HW transmission 2064 * 2065 * The UART is a strict FIFO, and we get called only when we have finished 2066 * pushing data to the FIFO, so the maximum amount of time we must wait 2067 * is only for the FIFO to drain out. 2068 * 2069 * We use a simple calibrated loop. We may need to adjust the loop 2070 * delay (udelay) to balance I/O traffic and latency. And we also need to 2071 * adjust the maximum timeout. 2072 * It would probably be better to wait for the proper interrupt, 2073 * but it doesn't seem to be available. 2074 * 2075 * We can't use jiffies or kernel timers because : 2076 * 1) We are called from the interrupt handler, which disable softirqs, 2077 * so jiffies won't be increased 2078 * 2) Jiffies granularity is usually very coarse (10ms), and we don't 2079 * want to wait that long to detect stuck hardware. 2080 * Jean II 2081 */ 2082 2083static void smsc_ircc_sir_wait_hw_transmitter_finish(struct smsc_ircc_cb *self) 2084{ 2085 int iobase = self->io.sir_base; 2086 int count = SMSC_IRCC2_HW_TRANSMITTER_TIMEOUT_US; 2087 2088 /* Calibrated busy loop */ 2089 while (count-- > 0 && !(inb(iobase + UART_LSR) & UART_LSR_TEMT)) 2090 udelay(1); 2091 2092 if (count == 0) 2093 IRDA_DEBUG(0, "%s(): stuck transmitter\n", __FUNCTION__); 2094} 2095 2096 2097/* PROBING 2098 * 2099 * REVISIT we can be told about the device by PNP, and should use that info 2100 * instead of probing hardware and creating a platform_device ... 2101 */ 2102 2103static int __init smsc_ircc_look_for_chips(void) 2104{ 2105 struct smsc_chip_address *address; 2106 char *type; 2107 unsigned int cfg_base, found; 2108 2109 found = 0; 2110 address = possible_addresses; 2111 2112 while (address->cfg_base) { 2113 cfg_base = address->cfg_base; 2114 2115 /*printk(KERN_WARNING "%s(): probing: 0x%02x for: 0x%02x\n", __FUNCTION__, cfg_base, address->type);*/ 2116 2117 if (address->type & SMSCSIO_TYPE_FDC) { 2118 type = "FDC"; 2119 if (address->type & SMSCSIO_TYPE_FLAT) 2120 if (!smsc_superio_flat(fdc_chips_flat, cfg_base, type)) 2121 found++; 2122 2123 if (address->type & SMSCSIO_TYPE_PAGED) 2124 if (!smsc_superio_paged(fdc_chips_paged, cfg_base, type)) 2125 found++; 2126 } 2127 if (address->type & SMSCSIO_TYPE_LPC) { 2128 type = "LPC"; 2129 if (address->type & SMSCSIO_TYPE_FLAT) 2130 if (!smsc_superio_flat(lpc_chips_flat, cfg_base, type)) 2131 found++; 2132 2133 if (address->type & SMSCSIO_TYPE_PAGED) 2134 if (!smsc_superio_paged(lpc_chips_paged, cfg_base, type)) 2135 found++; 2136 } 2137 address++; 2138 } 2139 return found; 2140} 2141 2142/* 2143 * Function smsc_superio_flat (chip, base, type) 2144 * 2145 * Try to get configuration of a smc SuperIO chip with flat register model 2146 * 2147 */ 2148static int __init smsc_superio_flat(const struct smsc_chip *chips, unsigned short cfgbase, char *type) 2149{ 2150 unsigned short firbase, sirbase; 2151 u8 mode, dma, irq; 2152 int ret = -ENODEV; 2153 2154 IRDA_DEBUG(1, "%s\n", __FUNCTION__); 2155 2156 if (smsc_ircc_probe(cfgbase, SMSCSIOFLAT_DEVICEID_REG, chips, type) == NULL) 2157 return ret; 2158 2159 outb(SMSCSIOFLAT_UARTMODE0C_REG, cfgbase); 2160 mode = inb(cfgbase + 1); 2161 2162 /*printk(KERN_WARNING "%s(): mode: 0x%02x\n", __FUNCTION__, mode);*/ 2163 2164 if (!(mode & SMSCSIOFLAT_UART2MODE_VAL_IRDA)) 2165 IRDA_WARNING("%s(): IrDA not enabled\n", __FUNCTION__); 2166 2167 outb(SMSCSIOFLAT_UART2BASEADDR_REG, cfgbase); 2168 sirbase = inb(cfgbase + 1) << 2; 2169 2170 /* FIR iobase */ 2171 outb(SMSCSIOFLAT_FIRBASEADDR_REG, cfgbase); 2172 firbase = inb(cfgbase + 1) << 3; 2173 2174 /* DMA */ 2175 outb(SMSCSIOFLAT_FIRDMASELECT_REG, cfgbase); 2176 dma = inb(cfgbase + 1) & SMSCSIOFLAT_FIRDMASELECT_MASK; 2177 2178 /* IRQ */ 2179 outb(SMSCSIOFLAT_UARTIRQSELECT_REG, cfgbase); 2180 irq = inb(cfgbase + 1) & SMSCSIOFLAT_UART2IRQSELECT_MASK; 2181 2182 IRDA_MESSAGE("%s(): fir: 0x%02x, sir: 0x%02x, dma: %02d, irq: %d, mode: 0x%02x\n", __FUNCTION__, firbase, sirbase, dma, irq, mode); 2183 2184 if (firbase && smsc_ircc_open(firbase, sirbase, dma, irq) == 0) 2185 ret = 0; 2186 2187 /* Exit configuration */ 2188 outb(SMSCSIO_CFGEXITKEY, cfgbase); 2189 2190 return ret; 2191} 2192 2193/* 2194 * Function smsc_superio_paged (chip, base, type) 2195 * 2196 * Try to get configuration of a smc SuperIO chip with paged register model 2197 * 2198 */ 2199static int __init smsc_superio_paged(const struct smsc_chip *chips, unsigned short cfg_base, char *type) 2200{ 2201 unsigned short fir_io, sir_io; 2202 int ret = -ENODEV; 2203 2204 IRDA_DEBUG(1, "%s\n", __FUNCTION__); 2205 2206 if (smsc_ircc_probe(cfg_base, 0x20, chips, type) == NULL) 2207 return ret; 2208 2209 /* Select logical device (UART2) */ 2210 outb(0x07, cfg_base); 2211 outb(0x05, cfg_base + 1); 2212 2213 /* SIR iobase */ 2214 outb(0x60, cfg_base); 2215 sir_io = inb(cfg_base + 1) << 8; 2216 outb(0x61, cfg_base); 2217 sir_io |= inb(cfg_base + 1); 2218 2219 /* Read FIR base */ 2220 outb(0x62, cfg_base); 2221 fir_io = inb(cfg_base + 1) << 8; 2222 outb(0x63, cfg_base); 2223 fir_io |= inb(cfg_base + 1); 2224 outb(0x2b, cfg_base); /* ??? */ 2225 2226 if (fir_io && smsc_ircc_open(fir_io, sir_io, ircc_dma, ircc_irq) == 0) 2227 ret = 0; 2228 2229 /* Exit configuration */ 2230 outb(SMSCSIO_CFGEXITKEY, cfg_base); 2231 2232 return ret; 2233} 2234 2235 2236static int __init smsc_access(unsigned short cfg_base, unsigned char reg) 2237{ 2238 IRDA_DEBUG(1, "%s\n", __FUNCTION__); 2239 2240 outb(reg, cfg_base); 2241 return inb(cfg_base) != reg ? -1 : 0; 2242} 2243 2244static const struct smsc_chip * __init smsc_ircc_probe(unsigned short cfg_base, u8 reg, const struct smsc_chip *chip, char *type) 2245{ 2246 u8 devid, xdevid, rev; 2247 2248 IRDA_DEBUG(1, "%s\n", __FUNCTION__); 2249 2250 /* Leave configuration */ 2251 2252 outb(SMSCSIO_CFGEXITKEY, cfg_base); 2253 2254 if (inb(cfg_base) == SMSCSIO_CFGEXITKEY) /* not a smc superio chip */ 2255 return NULL; 2256 2257 outb(reg, cfg_base); 2258 2259 xdevid = inb(cfg_base + 1); 2260 2261 /* Enter configuration */ 2262 2263 outb(SMSCSIO_CFGACCESSKEY, cfg_base); 2264 2265 #if 0 2266 if (smsc_access(cfg_base,0x55)) /* send second key and check */ 2267 return NULL; 2268 #endif 2269 2270 /* probe device ID */ 2271 2272 if (smsc_access(cfg_base, reg)) 2273 return NULL; 2274 2275 devid = inb(cfg_base + 1); 2276 2277 if (devid == 0 || devid == 0xff) /* typical values for unused port */ 2278 return NULL; 2279 2280 /* probe revision ID */ 2281 2282 if (smsc_access(cfg_base, reg + 1)) 2283 return NULL; 2284 2285 rev = inb(cfg_base + 1); 2286 2287 if (rev >= 128) /* i think this will make no sense */ 2288 return NULL; 2289 2290 if (devid == xdevid) /* protection against false positives */ 2291 return NULL; 2292 2293 /* Check for expected device ID; are there others? */ 2294 2295 while (chip->devid != devid) { 2296 2297 chip++; 2298 2299 if (chip->name == NULL) 2300 return NULL; 2301 } 2302 2303 IRDA_MESSAGE("found SMC SuperIO Chip (devid=0x%02x rev=%02X base=0x%04x): %s%s\n", 2304 devid, rev, cfg_base, type, chip->name); 2305 2306 if (chip->rev > rev) { 2307 IRDA_MESSAGE("Revision higher than expected\n"); 2308 return NULL; 2309 } 2310 2311 if (chip->flags & NoIRDA) 2312 IRDA_MESSAGE("chipset does not support IRDA\n"); 2313 2314 return chip; 2315} 2316 2317static int __init smsc_superio_fdc(unsigned short cfg_base) 2318{ 2319 int ret = -1; 2320 2321 if (!request_region(cfg_base, 2, driver_name)) { 2322 IRDA_WARNING("%s: can't get cfg_base of 0x%03x\n", 2323 __FUNCTION__, cfg_base); 2324 } else { 2325 if (!smsc_superio_flat(fdc_chips_flat, cfg_base, "FDC") || 2326 !smsc_superio_paged(fdc_chips_paged, cfg_base, "FDC")) 2327 ret = 0; 2328 2329 release_region(cfg_base, 2); 2330 } 2331 2332 return ret; 2333} 2334 2335static int __init smsc_superio_lpc(unsigned short cfg_base) 2336{ 2337 int ret = -1; 2338 2339 if (!request_region(cfg_base, 2, driver_name)) { 2340 IRDA_WARNING("%s: can't get cfg_base of 0x%03x\n", 2341 __FUNCTION__, cfg_base); 2342 } else { 2343 if (!smsc_superio_flat(lpc_chips_flat, cfg_base, "LPC") || 2344 !smsc_superio_paged(lpc_chips_paged, cfg_base, "LPC")) 2345 ret = 0; 2346 2347 release_region(cfg_base, 2); 2348 } 2349 return ret; 2350} 2351 2352/* 2353 * Look for some specific subsystem setups that need 2354 * pre-configuration not properly done by the BIOS (especially laptops) 2355 * This code is based in part on smcinit.c, tosh1800-smcinit.c 2356 * and tosh2450-smcinit.c. The table lists the device entries 2357 * for ISA bridges with an LPC (Low Pin Count) controller which 2358 * handles the communication with the SMSC device. After the LPC 2359 * controller is initialized through PCI, the SMSC device is initialized 2360 * through a dedicated port in the ISA port-mapped I/O area, this latter 2361 * area is used to configure the SMSC device with default 2362 * SIR and FIR I/O ports, DMA and IRQ. Different vendors have 2363 * used different sets of parameters and different control port 2364 * addresses making a subsystem device table necessary. 2365 */ 2366#ifdef CONFIG_PCI 2367#define PCIID_VENDOR_INTEL 0x8086 2368#define PCIID_VENDOR_ALI 0x10b9 2369static struct smsc_ircc_subsystem_configuration subsystem_configurations[] __initdata = { 2370 /* 2371 * Subsystems needing entries: 2372 * 0x10b9:0x1533 0x103c:0x0850 HP nx9010 family 2373 * 0x10b9:0x1533 0x0e11:0x005a Compaq nc4000 family 2374 * 0x8086:0x24cc 0x0e11:0x002a HP nx9000 family 2375 */ 2376 { 2377 /* Guessed entry */ 2378 .vendor = PCIID_VENDOR_INTEL, /* Intel 82801DBM LPC bridge */ 2379 .device = 0x24cc, 2380 .subvendor = 0x103c, 2381 .subdevice = 0x08bc, 2382 .sir_io = 0x02f8, 2383 .fir_io = 0x0130, 2384 .fir_irq = 0x05, 2385 .fir_dma = 0x03, 2386 .cfg_base = 0x004e, 2387 .preconfigure = preconfigure_through_82801, 2388 .name = "HP nx5000 family", 2389 }, 2390 { 2391 .vendor = PCIID_VENDOR_INTEL, /* Intel 82801DBM LPC bridge */ 2392 .device = 0x24cc, 2393 .subvendor = 0x103c, 2394 .subdevice = 0x088c, 2395 /* Quite certain these are the same for nc8000 as for nc6000 */ 2396 .sir_io = 0x02f8, 2397 .fir_io = 0x0130, 2398 .fir_irq = 0x05, 2399 .fir_dma = 0x03, 2400 .cfg_base = 0x004e, 2401 .preconfigure = preconfigure_through_82801, 2402 .name = "HP nc8000 family", 2403 }, 2404 { 2405 .vendor = PCIID_VENDOR_INTEL, /* Intel 82801DBM LPC bridge */ 2406 .device = 0x24cc, 2407 .subvendor = 0x103c, 2408 .subdevice = 0x0890, 2409 .sir_io = 0x02f8, 2410 .fir_io = 0x0130, 2411 .fir_irq = 0x05, 2412 .fir_dma = 0x03, 2413 .cfg_base = 0x004e, 2414 .preconfigure = preconfigure_through_82801, 2415 .name = "HP nc6000 family", 2416 }, 2417 { 2418 .vendor = PCIID_VENDOR_INTEL, /* Intel 82801DBM LPC bridge */ 2419 .device = 0x24cc, 2420 .subvendor = 0x0e11, 2421 .subdevice = 0x0860, 2422 /* I assume these are the same for x1000 as for the others */ 2423 .sir_io = 0x02e8, 2424 .fir_io = 0x02f8, 2425 .fir_irq = 0x07, 2426 .fir_dma = 0x03, 2427 .cfg_base = 0x002e, 2428 .preconfigure = preconfigure_through_82801, 2429 .name = "Compaq x1000 family", 2430 }, 2431 { 2432 /* Intel 82801DB/DBL (ICH4/ICH4-L) LPC Interface Bridge */ 2433 .vendor = PCIID_VENDOR_INTEL, 2434 .device = 0x24c0, 2435 .subvendor = 0x1179, 2436 .subdevice = 0xffff, /* 0xffff is "any" */ 2437 .sir_io = 0x03f8, 2438 .fir_io = 0x0130, 2439 .fir_irq = 0x07, 2440 .fir_dma = 0x01, 2441 .cfg_base = 0x002e, 2442 .preconfigure = preconfigure_through_82801, 2443 .name = "Toshiba laptop with Intel 82801DB/DBL LPC bridge", 2444 }, 2445 { 2446 .vendor = PCIID_VENDOR_INTEL, /* Intel 82801CAM ISA bridge */ 2447 .device = 0x248c, 2448 .subvendor = 0x1179, 2449 .subdevice = 0xffff, /* 0xffff is "any" */ 2450 .sir_io = 0x03f8, 2451 .fir_io = 0x0130, 2452 .fir_irq = 0x03, 2453 .fir_dma = 0x03, 2454 .cfg_base = 0x002e, 2455 .preconfigure = preconfigure_through_82801, 2456 .name = "Toshiba laptop with Intel 82801CAM ISA bridge", 2457 }, 2458 { 2459 /* 82801DBM (ICH4-M) LPC Interface Bridge */ 2460 .vendor = PCIID_VENDOR_INTEL, 2461 .device = 0x24cc, 2462 .subvendor = 0x1179, 2463 .subdevice = 0xffff, /* 0xffff is "any" */ 2464 .sir_io = 0x03f8, 2465 .fir_io = 0x0130, 2466 .fir_irq = 0x03, 2467 .fir_dma = 0x03, 2468 .cfg_base = 0x002e, 2469 .preconfigure = preconfigure_through_82801, 2470 .name = "Toshiba laptop with Intel 8281DBM LPC bridge", 2471 }, 2472 { 2473 /* ALi M1533/M1535 PCI to ISA Bridge [Aladdin IV/V/V+] */ 2474 .vendor = PCIID_VENDOR_ALI, 2475 .device = 0x1533, 2476 .subvendor = 0x1179, 2477 .subdevice = 0xffff, /* 0xffff is "any" */ 2478 .sir_io = 0x02e8, 2479 .fir_io = 0x02f8, 2480 .fir_irq = 0x07, 2481 .fir_dma = 0x03, 2482 .cfg_base = 0x002e, 2483 .preconfigure = preconfigure_through_ali, 2484 .name = "Toshiba laptop with ALi ISA bridge", 2485 }, 2486 { } // Terminator 2487}; 2488 2489 2490/* 2491 * This sets up the basic SMSC parameters 2492 * (FIR port, SIR port, FIR DMA, FIR IRQ) 2493 * through the chip configuration port. 2494 */ 2495static int __init preconfigure_smsc_chip(struct 2496 smsc_ircc_subsystem_configuration 2497 *conf) 2498{ 2499 unsigned short iobase = conf->cfg_base; 2500 unsigned char tmpbyte; 2501 2502 outb(LPC47N227_CFGACCESSKEY, iobase); // enter configuration state 2503 outb(SMSCSIOFLAT_DEVICEID_REG, iobase); // set for device ID 2504 tmpbyte = inb(iobase +1); // Read device ID 2505 IRDA_DEBUG(0, 2506 "Detected Chip id: 0x%02x, setting up registers...\n", 2507 tmpbyte); 2508 2509 /* Disable UART1 and set up SIR I/O port */ 2510 outb(0x24, iobase); // select CR24 - UART1 base addr 2511 outb(0x00, iobase + 1); // disable UART1 2512 outb(SMSCSIOFLAT_UART2BASEADDR_REG, iobase); // select CR25 - UART2 base addr 2513 outb( (conf->sir_io >> 2), iobase + 1); // bits 2-9 of 0x3f8 2514 tmpbyte = inb(iobase + 1); 2515 if (tmpbyte != (conf->sir_io >> 2) ) { 2516 IRDA_WARNING("ERROR: could not configure SIR ioport.\n"); 2517 IRDA_WARNING("Try to supply ircc_cfg argument.\n"); 2518 return -ENXIO; 2519 } 2520 2521 /* Set up FIR IRQ channel for UART2 */ 2522 outb(SMSCSIOFLAT_UARTIRQSELECT_REG, iobase); // select CR28 - UART1,2 IRQ select 2523 tmpbyte = inb(iobase + 1); 2524 tmpbyte &= SMSCSIOFLAT_UART1IRQSELECT_MASK; // Do not touch the UART1 portion 2525 tmpbyte |= (conf->fir_irq & SMSCSIOFLAT_UART2IRQSELECT_MASK); 2526 outb(tmpbyte, iobase + 1); 2527 tmpbyte = inb(iobase + 1) & SMSCSIOFLAT_UART2IRQSELECT_MASK; 2528 if (tmpbyte != conf->fir_irq) { 2529 IRDA_WARNING("ERROR: could not configure FIR IRQ channel.\n"); 2530 return -ENXIO; 2531 } 2532 2533 /* Set up FIR I/O port */ 2534 outb(SMSCSIOFLAT_FIRBASEADDR_REG, iobase); // CR2B - SCE (FIR) base addr 2535 outb((conf->fir_io >> 3), iobase + 1); 2536 tmpbyte = inb(iobase + 1); 2537 if (tmpbyte != (conf->fir_io >> 3) ) { 2538 IRDA_WARNING("ERROR: could not configure FIR I/O port.\n"); 2539 return -ENXIO; 2540 } 2541 2542 /* Set up FIR DMA channel */ 2543 outb(SMSCSIOFLAT_FIRDMASELECT_REG, iobase); // CR2C - SCE (FIR) DMA select 2544 outb((conf->fir_dma & LPC47N227_FIRDMASELECT_MASK), iobase + 1); // DMA 2545 tmpbyte = inb(iobase + 1) & LPC47N227_FIRDMASELECT_MASK; 2546 if (tmpbyte != (conf->fir_dma & LPC47N227_FIRDMASELECT_MASK)) { 2547 IRDA_WARNING("ERROR: could not configure FIR DMA channel.\n"); 2548 return -ENXIO; 2549 } 2550 2551 outb(SMSCSIOFLAT_UARTMODE0C_REG, iobase); // CR0C - UART mode 2552 tmpbyte = inb(iobase + 1); 2553 tmpbyte &= ~SMSCSIOFLAT_UART2MODE_MASK | 2554 SMSCSIOFLAT_UART2MODE_VAL_IRDA; 2555 outb(tmpbyte, iobase + 1); // enable IrDA (HPSIR) mode, high speed 2556 2557 outb(LPC47N227_APMBOOTDRIVE_REG, iobase); // CR07 - Auto Pwr Mgt/boot drive sel 2558 tmpbyte = inb(iobase + 1); 2559 outb(tmpbyte | LPC47N227_UART2AUTOPWRDOWN_MASK, iobase + 1); // enable UART2 autopower down 2560 2561 /* This one was not part of tosh1800 */ 2562 outb(0x0a, iobase); // CR0a - ecp fifo / ir mux 2563 tmpbyte = inb(iobase + 1); 2564 outb(tmpbyte | 0x40, iobase + 1); // send active device to ir port 2565 2566 outb(LPC47N227_UART12POWER_REG, iobase); // CR02 - UART 1,2 power 2567 tmpbyte = inb(iobase + 1); 2568 outb(tmpbyte | LPC47N227_UART2POWERDOWN_MASK, iobase + 1); // UART2 power up mode, UART1 power down 2569 2570 outb(LPC47N227_FDCPOWERVALIDCONF_REG, iobase); // CR00 - FDC Power/valid config cycle 2571 tmpbyte = inb(iobase + 1); 2572 outb(tmpbyte | LPC47N227_VALID_MASK, iobase + 1); // valid config cycle done 2573 2574 outb(LPC47N227_CFGEXITKEY, iobase); // Exit configuration 2575 2576 return 0; 2577} 2578 2579/* 82801CAM generic registers */ 2580#define VID 0x00 2581#define DID 0x02 2582#define PIRQ_A_D_ROUT 0x60 2583#define SIRQ_CNTL 0x64 2584#define PIRQ_E_H_ROUT 0x68 2585#define PCI_DMA_C 0x90 2586/* LPC-specific registers */ 2587#define COM_DEC 0xe0 2588#define GEN1_DEC 0xe4 2589#define LPC_EN 0xe6 2590#define GEN2_DEC 0xec 2591/* 2592 * Sets up the I/O range using the 82801CAM ISA bridge, 82801DBM LPC bridge 2593 * or Intel 82801DB/DBL (ICH4/ICH4-L) LPC Interface Bridge. 2594 * They all work the same way! 2595 */ 2596static int __init preconfigure_through_82801(struct pci_dev *dev, 2597 struct 2598 smsc_ircc_subsystem_configuration 2599 *conf) 2600{ 2601 unsigned short tmpword; 2602 unsigned char tmpbyte; 2603 2604 IRDA_MESSAGE("Setting up Intel 82801 controller and SMSC device\n"); 2605 /* 2606 * Select the range for the COMA COM port (SIR) 2607 * Register COM_DEC: 2608 * Bit 7: reserved 2609 * Bit 6-4, COMB decode range 2610 * Bit 3: reserved 2611 * Bit 2-0, COMA decode range 2612 * 2613 * Decode ranges: 2614 * 000 = 0x3f8-0x3ff (COM1) 2615 * 001 = 0x2f8-0x2ff (COM2) 2616 * 010 = 0x220-0x227 2617 * 011 = 0x228-0x22f 2618 * 100 = 0x238-0x23f 2619 * 101 = 0x2e8-0x2ef (COM4) 2620 * 110 = 0x338-0x33f 2621 * 111 = 0x3e8-0x3ef (COM3) 2622 */ 2623 pci_read_config_byte(dev, COM_DEC, &tmpbyte); 2624 tmpbyte &= 0xf8; /* mask COMA bits */ 2625 switch(conf->sir_io) { 2626 case 0x3f8: 2627 tmpbyte |= 0x00; 2628 break; 2629 case 0x2f8: 2630 tmpbyte |= 0x01; 2631 break; 2632 case 0x220: 2633 tmpbyte |= 0x02; 2634 break; 2635 case 0x228: 2636 tmpbyte |= 0x03; 2637 break; 2638 case 0x238: 2639 tmpbyte |= 0x04; 2640 break; 2641 case 0x2e8: 2642 tmpbyte |= 0x05; 2643 break; 2644 case 0x338: 2645 tmpbyte |= 0x06; 2646 break; 2647 case 0x3e8: 2648 tmpbyte |= 0x07; 2649 break; 2650 default: 2651 tmpbyte |= 0x01; /* COM2 default */ 2652 } 2653 IRDA_DEBUG(1, "COM_DEC (write): 0x%02x\n", tmpbyte); 2654 pci_write_config_byte(dev, COM_DEC, tmpbyte); 2655 2656 /* Enable Low Pin Count interface */ 2657 pci_read_config_word(dev, LPC_EN, &tmpword); 2658 /* These seem to be set up at all times, 2659 * just make sure it is properly set. 2660 */ 2661 switch(conf->cfg_base) { 2662 case 0x04e: 2663 tmpword |= 0x2000; 2664 break; 2665 case 0x02e: 2666 tmpword |= 0x1000; 2667 break; 2668 case 0x062: 2669 tmpword |= 0x0800; 2670 break; 2671 case 0x060: 2672 tmpword |= 0x0400; 2673 break; 2674 default: 2675 IRDA_WARNING("Uncommon I/O base address: 0x%04x\n", 2676 conf->cfg_base); 2677 break; 2678 } 2679 tmpword &= 0xfffd; /* disable LPC COMB */ 2680 tmpword |= 0x0001; /* set bit 0 : enable LPC COMA addr range (GEN2) */ 2681 IRDA_DEBUG(1, "LPC_EN (write): 0x%04x\n", tmpword); 2682 pci_write_config_word(dev, LPC_EN, tmpword); 2683 2684 /* 2685 * Configure LPC DMA channel 2686 * PCI_DMA_C bits: 2687 * Bit 15-14: DMA channel 7 select 2688 * Bit 13-12: DMA channel 6 select 2689 * Bit 11-10: DMA channel 5 select 2690 * Bit 9-8: Reserved 2691 * Bit 7-6: DMA channel 3 select 2692 * Bit 5-4: DMA channel 2 select 2693 * Bit 3-2: DMA channel 1 select 2694 * Bit 1-0: DMA channel 0 select 2695 * 00 = Reserved value 2696 * 01 = PC/PCI DMA 2697 * 10 = Reserved value 2698 * 11 = LPC I/F DMA 2699 */ 2700 pci_read_config_word(dev, PCI_DMA_C, &tmpword); 2701 switch(conf->fir_dma) { 2702 case 0x07: 2703 tmpword |= 0xc000; 2704 break; 2705 case 0x06: 2706 tmpword |= 0x3000; 2707 break; 2708 case 0x05: 2709 tmpword |= 0x0c00; 2710 break; 2711 case 0x03: 2712 tmpword |= 0x00c0; 2713 break; 2714 case 0x02: 2715 tmpword |= 0x0030; 2716 break; 2717 case 0x01: 2718 tmpword |= 0x000c; 2719 break; 2720 case 0x00: 2721 tmpword |= 0x0003; 2722 break; 2723 default: 2724 break; /* do not change settings */ 2725 } 2726 IRDA_DEBUG(1, "PCI_DMA_C (write): 0x%04x\n", tmpword); 2727 pci_write_config_word(dev, PCI_DMA_C, tmpword); 2728 2729 /* 2730 * GEN2_DEC bits: 2731 * Bit 15-4: Generic I/O range 2732 * Bit 3-1: reserved (read as 0) 2733 * Bit 0: enable GEN2 range on LPC I/F 2734 */ 2735 tmpword = conf->fir_io & 0xfff8; 2736 tmpword |= 0x0001; 2737 IRDA_DEBUG(1, "GEN2_DEC (write): 0x%04x\n", tmpword); 2738 pci_write_config_word(dev, GEN2_DEC, tmpword); 2739 2740 /* Pre-configure chip */ 2741 return preconfigure_smsc_chip(conf); 2742} 2743 2744/* 2745 * Pre-configure a certain port on the ALi 1533 bridge. 2746 * This is based on reverse-engineering since ALi does not 2747 * provide any data sheet for the 1533 chip. 2748 */ 2749static void __init preconfigure_ali_port(struct pci_dev *dev, 2750 unsigned short port) 2751{ 2752 unsigned char reg; 2753 /* These bits obviously control the different ports */ 2754 unsigned char mask; 2755 unsigned char tmpbyte; 2756 2757 switch(port) { 2758 case 0x0130: 2759 case 0x0178: 2760 reg = 0xb0; 2761 mask = 0x80; 2762 break; 2763 case 0x03f8: 2764 reg = 0xb4; 2765 mask = 0x80; 2766 break; 2767 case 0x02f8: 2768 reg = 0xb4; 2769 mask = 0x30; 2770 break; 2771 case 0x02e8: 2772 reg = 0xb4; 2773 mask = 0x08; 2774 break; 2775 default: 2776 IRDA_ERROR("Failed to configure unsupported port on ALi 1533 bridge: 0x%04x\n", port); 2777 return; 2778 } 2779 2780 pci_read_config_byte(dev, reg, &tmpbyte); 2781 /* Turn on the right bits */ 2782 tmpbyte |= mask; 2783 pci_write_config_byte(dev, reg, tmpbyte); 2784 IRDA_MESSAGE("Activated ALi 1533 ISA bridge port 0x%04x.\n", port); 2785 return; 2786} 2787 2788static int __init preconfigure_through_ali(struct pci_dev *dev, 2789 struct 2790 smsc_ircc_subsystem_configuration 2791 *conf) 2792{ 2793 /* Configure the two ports on the ALi 1533 */ 2794 preconfigure_ali_port(dev, conf->sir_io); 2795 preconfigure_ali_port(dev, conf->fir_io); 2796 2797 /* Pre-configure chip */ 2798 return preconfigure_smsc_chip(conf); 2799} 2800 2801static int __init smsc_ircc_preconfigure_subsystems(unsigned short ircc_cfg, 2802 unsigned short ircc_fir, 2803 unsigned short ircc_sir, 2804 unsigned char ircc_dma, 2805 unsigned char ircc_irq) 2806{ 2807 struct pci_dev *dev = NULL; 2808 unsigned short ss_vendor = 0x0000; 2809 unsigned short ss_device = 0x0000; 2810 int ret = 0; 2811 2812 dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev); 2813 2814 while (dev != NULL) { 2815 struct smsc_ircc_subsystem_configuration *conf; 2816 2817 /* 2818 * Cache the subsystem vendor/device: 2819 * some manufacturers fail to set this for all components, 2820 * so we save it in case there is just 0x0000 0x0000 on the 2821 * device we want to check. 2822 */ 2823 if (dev->subsystem_vendor != 0x0000U) { 2824 ss_vendor = dev->subsystem_vendor; 2825 ss_device = dev->subsystem_device; 2826 } 2827 conf = subsystem_configurations; 2828 for( ; conf->subvendor; conf++) { 2829 if(conf->vendor == dev->vendor && 2830 conf->device == dev->device && 2831 conf->subvendor == ss_vendor && 2832 /* Sometimes these are cached values */ 2833 (conf->subdevice == ss_device || 2834 conf->subdevice == 0xffff)) { 2835 struct smsc_ircc_subsystem_configuration 2836 tmpconf; 2837 2838 memcpy(&tmpconf, conf, 2839 sizeof(struct smsc_ircc_subsystem_configuration)); 2840 2841 /* 2842 * Override the default values with anything 2843 * passed in as parameter 2844 */ 2845 if (ircc_cfg != 0) 2846 tmpconf.cfg_base = ircc_cfg; 2847 if (ircc_fir != 0) 2848 tmpconf.fir_io = ircc_fir; 2849 if (ircc_sir != 0) 2850 tmpconf.sir_io = ircc_sir; 2851 if (ircc_dma != DMA_INVAL) 2852 tmpconf.fir_dma = ircc_dma; 2853 if (ircc_irq != IRQ_INVAL) 2854 tmpconf.fir_irq = ircc_irq; 2855 2856 IRDA_MESSAGE("Detected unconfigured %s SMSC IrDA chip, pre-configuring device.\n", conf->name); 2857 if (conf->preconfigure) 2858 ret = conf->preconfigure(dev, &tmpconf); 2859 else 2860 ret = -ENODEV; 2861 } 2862 } 2863 dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev); 2864 } 2865 2866 return ret; 2867} 2868#endif // CONFIG_PCI 2869 2870/************************************************ 2871 * 2872 * Transceivers specific functions 2873 * 2874 ************************************************/ 2875 2876 2877/* 2878 * Function smsc_ircc_set_transceiver_smsc_ircc_atc(fir_base, speed) 2879 * 2880 * Program transceiver through smsc-ircc ATC circuitry 2881 * 2882 */ 2883 2884static void smsc_ircc_set_transceiver_smsc_ircc_atc(int fir_base, u32 speed) 2885{ 2886 unsigned long jiffies_now, jiffies_timeout; 2887 u8 val; 2888 2889 jiffies_now = jiffies; 2890 jiffies_timeout = jiffies + SMSC_IRCC2_ATC_PROGRAMMING_TIMEOUT_JIFFIES; 2891 2892 /* ATC */ 2893 register_bank(fir_base, 4); 2894 outb((inb(fir_base + IRCC_ATC) & IRCC_ATC_MASK) | IRCC_ATC_nPROGREADY|IRCC_ATC_ENABLE, 2895 fir_base + IRCC_ATC); 2896 2897 while ((val = (inb(fir_base + IRCC_ATC) & IRCC_ATC_nPROGREADY)) && 2898 !time_after(jiffies, jiffies_timeout)) 2899 /* empty */; 2900 2901 if (val) 2902 IRDA_WARNING("%s(): ATC: 0x%02x\n", __FUNCTION__, 2903 inb(fir_base + IRCC_ATC)); 2904} 2905 2906/* 2907 * Function smsc_ircc_probe_transceiver_smsc_ircc_atc(fir_base) 2908 * 2909 * Probe transceiver smsc-ircc ATC circuitry 2910 * 2911 */ 2912 2913static int smsc_ircc_probe_transceiver_smsc_ircc_atc(int fir_base) 2914{ 2915 return 0; 2916} 2917 2918/* 2919 * Function smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select(self, speed) 2920 * 2921 * Set transceiver 2922 * 2923 */ 2924 2925static void smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select(int fir_base, u32 speed) 2926{ 2927 u8 fast_mode; 2928 2929 switch (speed) { 2930 default: 2931 case 576000 : 2932 fast_mode = 0; 2933 break; 2934 case 1152000 : 2935 case 4000000 : 2936 fast_mode = IRCC_LCR_A_FAST; 2937 break; 2938 } 2939 register_bank(fir_base, 0); 2940 outb((inb(fir_base + IRCC_LCR_A) & 0xbf) | fast_mode, fir_base + IRCC_LCR_A); 2941} 2942 2943/* 2944 * Function smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select(fir_base) 2945 * 2946 * Probe transceiver 2947 * 2948 */ 2949 2950static int smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select(int fir_base) 2951{ 2952 return 0; 2953} 2954 2955/* 2956 * Function smsc_ircc_set_transceiver_toshiba_sat1800(fir_base, speed) 2957 * 2958 * Set transceiver 2959 * 2960 */ 2961 2962static void smsc_ircc_set_transceiver_toshiba_sat1800(int fir_base, u32 speed) 2963{ 2964 u8 fast_mode; 2965 2966 switch (speed) { 2967 default: 2968 case 576000 : 2969 fast_mode = 0; 2970 break; 2971 case 1152000 : 2972 case 4000000 : 2973 fast_mode = /*IRCC_LCR_A_FAST |*/ IRCC_LCR_A_GP_DATA; 2974 break; 2975 2976 } 2977 /* This causes an interrupt */ 2978 register_bank(fir_base, 0); 2979 outb((inb(fir_base + IRCC_LCR_A) & 0xbf) | fast_mode, fir_base + IRCC_LCR_A); 2980} 2981 2982/* 2983 * Function smsc_ircc_probe_transceiver_toshiba_sat1800(fir_base) 2984 * 2985 * Probe transceiver 2986 * 2987 */ 2988 2989static int smsc_ircc_probe_transceiver_toshiba_sat1800(int fir_base) 2990{ 2991 return 0; 2992} 2993 2994 2995module_init(smsc_ircc_init); 2996module_exit(smsc_ircc_cleanup); 2997