1/*********************************************************************
2 *
3 * Filename:      nsc-ircc.h
4 * Version:
5 * Description:
6 * Status:        Experimental.
7 * Author:        Dag Brattli <dagb@cs.uit.no>
8 * Created at:    Fri Nov 13 14:37:40 1998
9 * Modified at:   Sun Jan 23 17:47:00 2000
10 * Modified by:   Dag Brattli <dagb@cs.uit.no>
11 *
12 *     Copyright (c) 1998-2000 Dag Brattli <dagb@cs.uit.no>
13 *     Copyright (c) 1998 Lichen Wang, <lwang@actisys.com>
14 *     Copyright (c) 1998 Actisys Corp., www.actisys.com
15 *     All Rights Reserved
16 *
17 *     This program is free software; you can redistribute it and/or
18 *     modify it under the terms of the GNU General Public License as
19 *     published by the Free Software Foundation; either version 2 of
20 *     the License, or (at your option) any later version.
21 *
22 *     Neither Dag Brattli nor University of Troms� admit liability nor
23 *     provide warranty for any of this software. This material is
24 *     provided "AS-IS" and at no charge.
25 *
26 ********************************************************************/
27
28#ifndef NSC_IRCC_H
29#define NSC_IRCC_H
30
31#include <linux/time.h>
32
33#include <linux/spinlock.h>
34#include <linux/pm.h>
35#include <linux/types.h>
36#include <asm/io.h>
37
38/* DMA modes needed */
39#define DMA_TX_MODE     0x08    /* Mem to I/O, ++, demand. */
40#define DMA_RX_MODE     0x04    /* I/O to mem, ++, demand. */
41
42/* Config registers for the '108 */
43#define CFG_108_BAIC 0x00
44#define CFG_108_CSRT 0x01
45#define CFG_108_MCTL 0x02
46
47/* Config registers for the '338 */
48#define CFG_338_FER  0x00
49#define CFG_338_FAR  0x01
50#define CFG_338_PTR  0x02
51#define CFG_338_PNP0 0x1b
52#define CFG_338_PNP1 0x1c
53#define CFG_338_PNP3 0x4f
54
55/* Config registers for the '39x (in the logical device bank) */
56#define CFG_39X_LDN	0x07	/* Logical device number (Super I/O bank) */
57#define CFG_39X_SIOCF1	0x21	/* SuperI/O Config */
58#define CFG_39X_ACT	0x30	/* Device activation */
59#define CFG_39X_BASEH	0x60	/* Device base address (high bits) */
60#define CFG_39X_BASEL	0x61	/* Device base address (low bits) */
61#define CFG_39X_IRQNUM	0x70	/* Interrupt number & wake up enable */
62#define CFG_39X_IRQSEL	0x71	/* Interrupt select (edge/level + polarity) */
63#define CFG_39X_DMA0	0x74	/* DMA 0 configuration */
64#define CFG_39X_DMA1	0x75	/* DMA 1 configuration */
65#define CFG_39X_SPC	0xF0	/* Serial port configuration register */
66
67/* Flags for configuration register CRF0 */
68#define APEDCRC		0x02
69#define ENBNKSEL	0x01
70
71/* Set 0 */
72#define TXD             0x00 /* Transmit data port */
73#define RXD             0x00 /* Receive data port */
74
75/* Register 1 */
76#define IER		0x01 /* Interrupt Enable Register*/
77#define IER_RXHDL_IE    0x01 /* Receiver high data level interrupt */
78#define IER_TXLDL_IE    0x02 /* Transeiver low data level interrupt */
79#define IER_LS_IE	0x04//* Link Status Interrupt */
80#define IER_ETXURI      0x04 /* Tx underrun */
81#define IER_DMA_IE	0x10 /* DMA finished interrupt */
82#define IER_TXEMP_IE    0x20
83#define IER_SFIF_IE     0x40 /* Frame status FIFO intr */
84#define IER_TMR_IE      0x80 /* Timer event */
85
86#define FCR		0x02 /* (write only) */
87#define FCR_FIFO_EN     0x01 /* Enable FIFO's */
88#define FCR_RXSR        0x02 /* Rx FIFO soft reset */
89#define FCR_TXSR        0x04 /* Tx FIFO soft reset */
90#define FCR_RXTH	0x40 /* Rx FIFO threshold (set to 16) */
91#define FCR_TXTH	0x20 /* Tx FIFO threshold (set to 17) */
92
93#define EIR		0x02 /* (read only) */
94#define EIR_RXHDL_EV	0x01
95#define EIR_TXLDL_EV    0x02
96#define EIR_LS_EV	0x04
97#define EIR_DMA_EV	0x10
98#define EIR_TXEMP_EV	0x20
99#define EIR_SFIF_EV     0x40
100#define EIR_TMR_EV      0x80
101
102#define LCR             0x03 /* Link control register */
103#define LCR_WLS_8       0x03 /* 8 bits */
104
105#define BSR 	        0x03 /* Bank select register */
106#define BSR_BKSE        0x80
107#define BANK0 	        LCR_WLS_8 /* Must make sure that we set 8N1 */
108#define BANK1	        0x80
109#define BANK2	        0xe0
110#define BANK3	        0xe4
111#define BANK4	        0xe8
112#define BANK5	        0xec
113#define BANK6	        0xf0
114#define BANK7     	0xf4
115
116#define MCR		0x04 /* Mode Control Register */
117#define MCR_MODE_MASK	~(0xd0)
118#define MCR_UART        0x00
119#define MCR_RESERVED  	0x20
120#define MCR_SHARP_IR    0x40
121#define MCR_SIR         0x60
122#define MCR_MIR  	0x80
123#define MCR_FIR		0xa0
124#define MCR_CEIR        0xb0
125#define MCR_IR_PLS      0x10
126#define MCR_DMA_EN	0x04
127#define MCR_EN_IRQ	0x08
128#define MCR_TX_DFR	0x08
129
130#define LSR             0x05 /* Link status register */
131#define LSR_RXDA        0x01 /* Receiver data available */
132#define LSR_TXRDY       0x20 /* Transmitter ready */
133#define LSR_TXEMP       0x40 /* Transmitter empty */
134
135#define ASCR            0x07 /* Auxillary Status and Control Register */
136#define ASCR_RXF_TOUT   0x01 /* Rx FIFO timeout */
137#define ASCR_FEND_INF   0x02 /* Frame end bytes in rx FIFO */
138#define ASCR_S_EOT      0x04 /* Set end of transmission */
139#define ASCT_RXBSY      0x20 /* Rx busy */
140#define ASCR_TXUR       0x40 /* Transeiver underrun */
141#define ASCR_CTE        0x80 /* Clear timer event */
142
143/* Bank 2 */
144#define BGDL            0x00 /* Baud Generator Divisor Port (Low Byte) */
145#define BGDH            0x01 /* Baud Generator Divisor Port (High Byte) */
146
147#define ECR1		0x02 /* Extended Control Register 1 */
148#define ECR1_EXT_SL	0x01 /* Extended Mode Select */
149#define ECR1_DMANF	0x02 /* DMA Fairness */
150#define ECR1_DMATH      0x04 /* DMA Threshold */
151#define ECR1_DMASWP	0x08 /* DMA Swap */
152
153#define EXCR2		0x04
154#define EXCR2_TFSIZ	0x01 /* Rx FIFO size = 32 */
155#define EXCR2_RFSIZ	0x04 /* Tx FIFO size = 32 */
156
157#define TXFLV           0x06 /* Tx FIFO level */
158#define RXFLV           0x07 /* Rx FIFO level */
159
160/* Bank 3 */
161#define MID		0x00
162
163/* Bank 4 */
164#define TMRL            0x00 /* Timer low byte */
165#define TMRH            0x01 /* Timer high byte */
166#define IRCR1           0x02 /* Infrared control register 1 */
167#define IRCR1_TMR_EN    0x01 /* Timer enable */
168
169#define TFRLL		0x04
170#define TFRLH		0x05
171#define RFRLL		0x06
172#define RFRLH		0x07
173
174/* Bank 5 */
175#define IRCR2           0x04 /* Infrared control register 2 */
176#define IRCR2_MDRS      0x04 /* MIR data rate select */
177#define IRCR2_FEND_MD   0x20 /* */
178
179#define FRM_ST          0x05 /* Frame status FIFO */
180#define FRM_ST_VLD      0x80 /* Frame status FIFO data valid */
181#define FRM_ST_ERR_MSK  0x5f
182#define FRM_ST_LOST_FR  0x40 /* Frame lost */
183#define FRM_ST_MAX_LEN  0x10 /* Max frame len exceeded */
184#define FRM_ST_PHY_ERR  0x08 /* Physical layer error */
185#define FRM_ST_BAD_CRC  0x04
186#define FRM_ST_OVR1     0x02 /* Rx FIFO overrun */
187#define FRM_ST_OVR2     0x01 /* Frame status FIFO overrun */
188
189#define RFLFL           0x06
190#define RFLFH           0x07
191
192/* Bank 6 */
193#define IR_CFG2		0x00
194#define IR_CFG2_DIS_CRC	0x02
195
196/* Bank 7 */
197#define IRM_CR		0x07 /* Infrared module control register */
198#define IRM_CR_IRX_MSL	0x40
199#define IRM_CR_AF_MNT   0x80 /* Automatic format */
200
201/* NSC chip information */
202struct nsc_chip {
203	char *name;          /* Name of chipset */
204	int cfg[3];          /* Config registers */
205	u_int8_t cid_index;  /* Chip identification index reg */
206	u_int8_t cid_value;  /* Chip identification expected value */
207	u_int8_t cid_mask;   /* Chip identification revision mask */
208
209	/* Functions for probing and initializing the specific chip */
210	int (*probe)(struct nsc_chip *chip, chipio_t *info);
211	int (*init)(struct nsc_chip *chip, chipio_t *info);
212};
213typedef struct nsc_chip nsc_chip_t;
214
215/* For storing entries in the status FIFO */
216struct st_fifo_entry {
217	int status;
218	int len;
219};
220
221#define MAX_TX_WINDOW 7
222#define MAX_RX_WINDOW 7
223
224struct st_fifo {
225	struct st_fifo_entry entries[MAX_RX_WINDOW];
226	int pending_bytes;
227	int head;
228	int tail;
229	int len;
230};
231
232struct frame_cb {
233	void *start; /* Start of frame in DMA mem */
234	int len;     /* Lenght of frame in DMA mem */
235};
236
237struct tx_fifo {
238	struct frame_cb queue[MAX_TX_WINDOW]; /* Info about frames in queue */
239	int             ptr;                  /* Currently being sent */
240	int             len;                  /* Lenght of queue */
241	int             free;                 /* Next free slot */
242	void           *tail;                 /* Next free start in DMA mem */
243};
244
245/* Private data for each instance */
246struct nsc_ircc_cb {
247	struct st_fifo st_fifo;    /* Info about received frames */
248	struct tx_fifo tx_fifo;    /* Info about frames to be transmitted */
249
250	struct net_device *netdev;     /* Yes! we are some kind of netdevice */
251	struct net_device_stats stats;
252
253	struct irlap_cb *irlap;    /* The link layer we are binded to */
254	struct qos_info qos;       /* QoS capabilities for this device */
255
256	chipio_t io;               /* IrDA controller information */
257	iobuff_t tx_buff;          /* Transmit buffer */
258	iobuff_t rx_buff;          /* Receive buffer */
259	dma_addr_t tx_buff_dma;
260	dma_addr_t rx_buff_dma;
261
262	__u8 ier;                  /* Interrupt enable register */
263
264	struct timeval stamp;
265	struct timeval now;
266
267	spinlock_t lock;           /* For serializing operations */
268
269	__u32 new_speed;
270	int index;                 /* Instance index */
271
272	struct platform_device *pldev;
273};
274
275static inline void switch_bank(int iobase, int bank)
276{
277		outb(bank, iobase+BSR);
278}
279
280#endif /* NSC_IRCC_H */
281