1/* 2 Driver for STV0297 demodulator 3 4 Copyright (C) 2004 Andrew de Quincey <adq_dvb@lidskialf.net> 5 Copyright (C) 2003-2004 Dennis Noermann <dennis.noermann@noernet.de> 6 7 This program is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 2 of the License, or 10 (at your option) any later version. 11 12 This program is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with this program; if not, write to the Free Software 19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 20*/ 21 22#include <linux/init.h> 23#include <linux/kernel.h> 24#include <linux/module.h> 25#include <linux/string.h> 26#include <linux/delay.h> 27#include <linux/jiffies.h> 28#include <linux/slab.h> 29 30#include "dvb_frontend.h" 31#include "stv0297.h" 32 33struct stv0297_state { 34 struct i2c_adapter *i2c; 35 const struct stv0297_config *config; 36 struct dvb_frontend frontend; 37 38 unsigned long last_ber; 39 unsigned long base_freq; 40}; 41 42#define dprintk(x...) printk(x) 43 44#define STV0297_CLOCK_KHZ 28900 45 46 47static int stv0297_writereg(struct stv0297_state *state, u8 reg, u8 data) 48{ 49 int ret; 50 u8 buf[] = { reg, data }; 51 struct i2c_msg msg = {.addr = state->config->demod_address,.flags = 0,.buf = buf,.len = 2 }; 52 53 ret = i2c_transfer(state->i2c, &msg, 1); 54 55 if (ret != 1) 56 dprintk("%s: writereg error (reg == 0x%02x, val == 0x%02x, " 57 "ret == %i)\n", __FUNCTION__, reg, data, ret); 58 59 return (ret != 1) ? -1 : 0; 60} 61 62static int stv0297_readreg(struct stv0297_state *state, u8 reg) 63{ 64 int ret; 65 u8 b0[] = { reg }; 66 u8 b1[] = { 0 }; 67 struct i2c_msg msg[] = { {.addr = state->config->demod_address,.flags = 0,.buf = b0,.len = 1}, 68 {.addr = state->config->demod_address,.flags = I2C_M_RD,.buf = b1,.len = 1} 69 }; 70 71 // this device needs a STOP between the register and data 72 if (state->config->stop_during_read) { 73 if ((ret = i2c_transfer(state->i2c, &msg[0], 1)) != 1) { 74 dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __FUNCTION__, reg, ret); 75 return -1; 76 } 77 if ((ret = i2c_transfer(state->i2c, &msg[1], 1)) != 1) { 78 dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __FUNCTION__, reg, ret); 79 return -1; 80 } 81 } else { 82 if ((ret = i2c_transfer(state->i2c, msg, 2)) != 2) { 83 dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __FUNCTION__, reg, ret); 84 return -1; 85 } 86 } 87 88 return b1[0]; 89} 90 91static int stv0297_writereg_mask(struct stv0297_state *state, u8 reg, u8 mask, u8 data) 92{ 93 int val; 94 95 val = stv0297_readreg(state, reg); 96 val &= ~mask; 97 val |= (data & mask); 98 stv0297_writereg(state, reg, val); 99 100 return 0; 101} 102 103static int stv0297_readregs(struct stv0297_state *state, u8 reg1, u8 * b, u8 len) 104{ 105 int ret; 106 struct i2c_msg msg[] = { {.addr = state->config->demod_address,.flags = 0,.buf = 107 ®1,.len = 1}, 108 {.addr = state->config->demod_address,.flags = I2C_M_RD,.buf = b,.len = len} 109 }; 110 111 // this device needs a STOP between the register and data 112 if (state->config->stop_during_read) { 113 if ((ret = i2c_transfer(state->i2c, &msg[0], 1)) != 1) { 114 dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __FUNCTION__, reg1, ret); 115 return -1; 116 } 117 if ((ret = i2c_transfer(state->i2c, &msg[1], 1)) != 1) { 118 dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __FUNCTION__, reg1, ret); 119 return -1; 120 } 121 } else { 122 if ((ret = i2c_transfer(state->i2c, msg, 2)) != 2) { 123 dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __FUNCTION__, reg1, ret); 124 return -1; 125 } 126 } 127 128 return 0; 129} 130 131static u32 stv0297_get_symbolrate(struct stv0297_state *state) 132{ 133 u64 tmp; 134 135 tmp = stv0297_readreg(state, 0x55); 136 tmp |= stv0297_readreg(state, 0x56) << 8; 137 tmp |= stv0297_readreg(state, 0x57) << 16; 138 tmp |= stv0297_readreg(state, 0x58) << 24; 139 140 tmp *= STV0297_CLOCK_KHZ; 141 tmp >>= 32; 142 143 return (u32) tmp; 144} 145 146static void stv0297_set_symbolrate(struct stv0297_state *state, u32 srate) 147{ 148 long tmp; 149 150 tmp = 131072L * srate; /* 131072 = 2^17 */ 151 tmp = tmp / (STV0297_CLOCK_KHZ / 4); /* 1/4 = 2^-2 */ 152 tmp = tmp * 8192L; /* 8192 = 2^13 */ 153 154 stv0297_writereg(state, 0x55, (unsigned char) (tmp & 0xFF)); 155 stv0297_writereg(state, 0x56, (unsigned char) (tmp >> 8)); 156 stv0297_writereg(state, 0x57, (unsigned char) (tmp >> 16)); 157 stv0297_writereg(state, 0x58, (unsigned char) (tmp >> 24)); 158} 159 160static void stv0297_set_sweeprate(struct stv0297_state *state, short fshift, long symrate) 161{ 162 long tmp; 163 164 tmp = (long) fshift *262144L; /* 262144 = 2*18 */ 165 tmp /= symrate; 166 tmp *= 1024; /* 1024 = 2*10 */ 167 168 // adjust 169 if (tmp >= 0) { 170 tmp += 500000; 171 } else { 172 tmp -= 500000; 173 } 174 tmp /= 1000000; 175 176 stv0297_writereg(state, 0x60, tmp & 0xFF); 177 stv0297_writereg_mask(state, 0x69, 0xF0, (tmp >> 4) & 0xf0); 178} 179 180static void stv0297_set_carrieroffset(struct stv0297_state *state, long offset) 181{ 182 long tmp; 183 184 /* symrate is hardcoded to 10000 */ 185 tmp = offset * 26844L; /* (2**28)/10000 */ 186 if (tmp < 0) 187 tmp += 0x10000000; 188 tmp &= 0x0FFFFFFF; 189 190 stv0297_writereg(state, 0x66, (unsigned char) (tmp & 0xFF)); 191 stv0297_writereg(state, 0x67, (unsigned char) (tmp >> 8)); 192 stv0297_writereg(state, 0x68, (unsigned char) (tmp >> 16)); 193 stv0297_writereg_mask(state, 0x69, 0x0F, (tmp >> 24) & 0x0f); 194} 195 196/* 197static long stv0297_get_carrieroffset(struct stv0297_state *state) 198{ 199 s64 tmp; 200 201 stv0297_writereg(state, 0x6B, 0x00); 202 203 tmp = stv0297_readreg(state, 0x66); 204 tmp |= (stv0297_readreg(state, 0x67) << 8); 205 tmp |= (stv0297_readreg(state, 0x68) << 16); 206 tmp |= (stv0297_readreg(state, 0x69) & 0x0F) << 24; 207 208 tmp *= stv0297_get_symbolrate(state); 209 tmp >>= 28; 210 211 return (s32) tmp; 212} 213*/ 214 215static void stv0297_set_initialdemodfreq(struct stv0297_state *state, long freq) 216{ 217 s32 tmp; 218 219 if (freq > 10000) 220 freq -= STV0297_CLOCK_KHZ; 221 222 tmp = (STV0297_CLOCK_KHZ * 1000) / (1 << 16); 223 tmp = (freq * 1000) / tmp; 224 if (tmp > 0xffff) 225 tmp = 0xffff; 226 227 stv0297_writereg_mask(state, 0x25, 0x80, 0x80); 228 stv0297_writereg(state, 0x21, tmp >> 8); 229 stv0297_writereg(state, 0x20, tmp); 230} 231 232static int stv0297_set_qam(struct stv0297_state *state, fe_modulation_t modulation) 233{ 234 int val = 0; 235 236 switch (modulation) { 237 case QAM_16: 238 val = 0; 239 break; 240 241 case QAM_32: 242 val = 1; 243 break; 244 245 case QAM_64: 246 val = 4; 247 break; 248 249 case QAM_128: 250 val = 2; 251 break; 252 253 case QAM_256: 254 val = 3; 255 break; 256 257 default: 258 return -EINVAL; 259 } 260 261 stv0297_writereg_mask(state, 0x00, 0x70, val << 4); 262 263 return 0; 264} 265 266static int stv0297_set_inversion(struct stv0297_state *state, fe_spectral_inversion_t inversion) 267{ 268 int val = 0; 269 270 switch (inversion) { 271 case INVERSION_OFF: 272 val = 0; 273 break; 274 275 case INVERSION_ON: 276 val = 1; 277 break; 278 279 default: 280 return -EINVAL; 281 } 282 283 stv0297_writereg_mask(state, 0x83, 0x08, val << 3); 284 285 return 0; 286} 287 288static int stv0297_i2c_gate_ctrl(struct dvb_frontend *fe, int enable) 289{ 290 struct stv0297_state *state = fe->demodulator_priv; 291 292 if (enable) { 293 stv0297_writereg(state, 0x87, 0x78); 294 stv0297_writereg(state, 0x86, 0xc8); 295 } 296 297 return 0; 298} 299 300static int stv0297_init(struct dvb_frontend *fe) 301{ 302 struct stv0297_state *state = fe->demodulator_priv; 303 int i; 304 305 /* load init table */ 306 for (i=0; !(state->config->inittab[i] == 0xff && state->config->inittab[i+1] == 0xff); i+=2) 307 stv0297_writereg(state, state->config->inittab[i], state->config->inittab[i+1]); 308 msleep(200); 309 310 state->last_ber = 0; 311 312 return 0; 313} 314 315static int stv0297_sleep(struct dvb_frontend *fe) 316{ 317 struct stv0297_state *state = fe->demodulator_priv; 318 319 stv0297_writereg_mask(state, 0x80, 1, 1); 320 321 return 0; 322} 323 324static int stv0297_read_status(struct dvb_frontend *fe, fe_status_t * status) 325{ 326 struct stv0297_state *state = fe->demodulator_priv; 327 328 u8 sync = stv0297_readreg(state, 0xDF); 329 330 *status = 0; 331 if (sync & 0x80) 332 *status |= 333 FE_HAS_SYNC | FE_HAS_SIGNAL | FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_LOCK; 334 return 0; 335} 336 337static int stv0297_read_ber(struct dvb_frontend *fe, u32 * ber) 338{ 339 struct stv0297_state *state = fe->demodulator_priv; 340 u8 BER[3]; 341 342 stv0297_readregs(state, 0xA0, BER, 3); 343 if (!(BER[0] & 0x80)) { 344 state->last_ber = BER[2] << 8 | BER[1]; 345 stv0297_writereg_mask(state, 0xA0, 0x80, 0x80); 346 } 347 348 *ber = state->last_ber; 349 350 return 0; 351} 352 353 354static int stv0297_read_signal_strength(struct dvb_frontend *fe, u16 * strength) 355{ 356 struct stv0297_state *state = fe->demodulator_priv; 357 u8 STRENGTH[2]; 358 359 stv0297_readregs(state, 0x41, STRENGTH, 2); 360 *strength = (STRENGTH[1] & 0x03) << 8 | STRENGTH[0]; 361 362 return 0; 363} 364 365static int stv0297_read_snr(struct dvb_frontend *fe, u16 * snr) 366{ 367 struct stv0297_state *state = fe->demodulator_priv; 368 u8 SNR[2]; 369 370 stv0297_readregs(state, 0x07, SNR, 2); 371 *snr = SNR[1] << 8 | SNR[0]; 372 373 return 0; 374} 375 376static int stv0297_read_ucblocks(struct dvb_frontend *fe, u32 * ucblocks) 377{ 378 struct stv0297_state *state = fe->demodulator_priv; 379 380 stv0297_writereg_mask(state, 0xDF, 0x03, 0x03); /* freeze the counters */ 381 382 *ucblocks = (stv0297_readreg(state, 0xD5) << 8) 383 | stv0297_readreg(state, 0xD4); 384 385 stv0297_writereg_mask(state, 0xDF, 0x03, 0x02); /* clear the counters */ 386 stv0297_writereg_mask(state, 0xDF, 0x03, 0x01); /* re-enable the counters */ 387 388 return 0; 389} 390 391static int stv0297_set_frontend(struct dvb_frontend *fe, struct dvb_frontend_parameters *p) 392{ 393 struct stv0297_state *state = fe->demodulator_priv; 394 int u_threshold; 395 int initial_u; 396 int blind_u; 397 int delay; 398 int sweeprate; 399 int carrieroffset; 400 unsigned long starttime; 401 unsigned long timeout; 402 fe_spectral_inversion_t inversion; 403 404 switch (p->u.qam.modulation) { 405 case QAM_16: 406 case QAM_32: 407 case QAM_64: 408 delay = 100; 409 sweeprate = 1000; 410 break; 411 412 case QAM_128: 413 case QAM_256: 414 delay = 200; 415 sweeprate = 500; 416 break; 417 418 default: 419 return -EINVAL; 420 } 421 422 // determine inversion dependant parameters 423 inversion = p->inversion; 424 if (state->config->invert) 425 inversion = (inversion == INVERSION_ON) ? INVERSION_OFF : INVERSION_ON; 426 carrieroffset = -330; 427 switch (inversion) { 428 case INVERSION_OFF: 429 break; 430 431 case INVERSION_ON: 432 sweeprate = -sweeprate; 433 carrieroffset = -carrieroffset; 434 break; 435 436 default: 437 return -EINVAL; 438 } 439 440 stv0297_init(fe); 441 if (fe->ops.tuner_ops.set_params) { 442 fe->ops.tuner_ops.set_params(fe, p); 443 if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0); 444 } 445 446 /* clear software interrupts */ 447 stv0297_writereg(state, 0x82, 0x0); 448 449 /* set initial demodulation frequency */ 450 stv0297_set_initialdemodfreq(state, 7250); 451 452 /* setup AGC */ 453 stv0297_writereg_mask(state, 0x43, 0x10, 0x00); 454 stv0297_writereg(state, 0x41, 0x00); 455 stv0297_writereg_mask(state, 0x42, 0x03, 0x01); 456 stv0297_writereg_mask(state, 0x36, 0x60, 0x00); 457 stv0297_writereg_mask(state, 0x36, 0x18, 0x00); 458 stv0297_writereg_mask(state, 0x71, 0x80, 0x80); 459 stv0297_writereg(state, 0x72, 0x00); 460 stv0297_writereg(state, 0x73, 0x00); 461 stv0297_writereg_mask(state, 0x74, 0x0F, 0x00); 462 stv0297_writereg_mask(state, 0x43, 0x08, 0x00); 463 stv0297_writereg_mask(state, 0x71, 0x80, 0x00); 464 465 /* setup STL */ 466 stv0297_writereg_mask(state, 0x5a, 0x20, 0x20); 467 stv0297_writereg_mask(state, 0x5b, 0x02, 0x02); 468 stv0297_writereg_mask(state, 0x5b, 0x02, 0x00); 469 stv0297_writereg_mask(state, 0x5b, 0x01, 0x00); 470 stv0297_writereg_mask(state, 0x5a, 0x40, 0x40); 471 472 /* disable frequency sweep */ 473 stv0297_writereg_mask(state, 0x6a, 0x01, 0x00); 474 475 /* reset deinterleaver */ 476 stv0297_writereg_mask(state, 0x81, 0x01, 0x01); 477 stv0297_writereg_mask(state, 0x81, 0x01, 0x00); 478 479 /* ??? */ 480 stv0297_writereg_mask(state, 0x83, 0x20, 0x20); 481 stv0297_writereg_mask(state, 0x83, 0x20, 0x00); 482 483 /* reset equaliser */ 484 u_threshold = stv0297_readreg(state, 0x00) & 0xf; 485 initial_u = stv0297_readreg(state, 0x01) >> 4; 486 blind_u = stv0297_readreg(state, 0x01) & 0xf; 487 stv0297_writereg_mask(state, 0x84, 0x01, 0x01); 488 stv0297_writereg_mask(state, 0x84, 0x01, 0x00); 489 stv0297_writereg_mask(state, 0x00, 0x0f, u_threshold); 490 stv0297_writereg_mask(state, 0x01, 0xf0, initial_u << 4); 491 stv0297_writereg_mask(state, 0x01, 0x0f, blind_u); 492 493 /* data comes from internal A/D */ 494 stv0297_writereg_mask(state, 0x87, 0x80, 0x00); 495 496 /* clear phase registers */ 497 stv0297_writereg(state, 0x63, 0x00); 498 stv0297_writereg(state, 0x64, 0x00); 499 stv0297_writereg(state, 0x65, 0x00); 500 stv0297_writereg(state, 0x66, 0x00); 501 stv0297_writereg(state, 0x67, 0x00); 502 stv0297_writereg(state, 0x68, 0x00); 503 stv0297_writereg_mask(state, 0x69, 0x0f, 0x00); 504 505 /* set parameters */ 506 stv0297_set_qam(state, p->u.qam.modulation); 507 stv0297_set_symbolrate(state, p->u.qam.symbol_rate / 1000); 508 stv0297_set_sweeprate(state, sweeprate, p->u.qam.symbol_rate / 1000); 509 stv0297_set_carrieroffset(state, carrieroffset); 510 stv0297_set_inversion(state, inversion); 511 512 /* kick off lock */ 513 /* Disable corner detection for higher QAMs */ 514 if (p->u.qam.modulation == QAM_128 || 515 p->u.qam.modulation == QAM_256) 516 stv0297_writereg_mask(state, 0x88, 0x08, 0x00); 517 else 518 stv0297_writereg_mask(state, 0x88, 0x08, 0x08); 519 520 stv0297_writereg_mask(state, 0x5a, 0x20, 0x00); 521 stv0297_writereg_mask(state, 0x6a, 0x01, 0x01); 522 stv0297_writereg_mask(state, 0x43, 0x40, 0x40); 523 stv0297_writereg_mask(state, 0x5b, 0x30, 0x00); 524 stv0297_writereg_mask(state, 0x03, 0x0c, 0x0c); 525 stv0297_writereg_mask(state, 0x03, 0x03, 0x03); 526 stv0297_writereg_mask(state, 0x43, 0x10, 0x10); 527 528 /* wait for WGAGC lock */ 529 starttime = jiffies; 530 timeout = jiffies + msecs_to_jiffies(2000); 531 while (time_before(jiffies, timeout)) { 532 msleep(10); 533 if (stv0297_readreg(state, 0x43) & 0x08) 534 break; 535 } 536 if (time_after(jiffies, timeout)) { 537 goto timeout; 538 } 539 msleep(20); 540 541 /* wait for equaliser partial convergence */ 542 timeout = jiffies + msecs_to_jiffies(500); 543 while (time_before(jiffies, timeout)) { 544 msleep(10); 545 546 if (stv0297_readreg(state, 0x82) & 0x04) { 547 break; 548 } 549 } 550 if (time_after(jiffies, timeout)) { 551 goto timeout; 552 } 553 554 /* wait for equaliser full convergence */ 555 timeout = jiffies + msecs_to_jiffies(delay); 556 while (time_before(jiffies, timeout)) { 557 msleep(10); 558 559 if (stv0297_readreg(state, 0x82) & 0x08) { 560 break; 561 } 562 } 563 if (time_after(jiffies, timeout)) { 564 goto timeout; 565 } 566 567 /* disable sweep */ 568 stv0297_writereg_mask(state, 0x6a, 1, 0); 569 stv0297_writereg_mask(state, 0x88, 8, 0); 570 571 /* wait for main lock */ 572 timeout = jiffies + msecs_to_jiffies(20); 573 while (time_before(jiffies, timeout)) { 574 msleep(10); 575 576 if (stv0297_readreg(state, 0xDF) & 0x80) { 577 break; 578 } 579 } 580 if (time_after(jiffies, timeout)) { 581 goto timeout; 582 } 583 msleep(100); 584 585 /* is it still locked after that delay? */ 586 if (!(stv0297_readreg(state, 0xDF) & 0x80)) { 587 goto timeout; 588 } 589 590 /* success!! */ 591 stv0297_writereg_mask(state, 0x5a, 0x40, 0x00); 592 state->base_freq = p->frequency; 593 return 0; 594 595timeout: 596 stv0297_writereg_mask(state, 0x6a, 0x01, 0x00); 597 return 0; 598} 599 600static int stv0297_get_frontend(struct dvb_frontend *fe, struct dvb_frontend_parameters *p) 601{ 602 struct stv0297_state *state = fe->demodulator_priv; 603 int reg_00, reg_83; 604 605 reg_00 = stv0297_readreg(state, 0x00); 606 reg_83 = stv0297_readreg(state, 0x83); 607 608 p->frequency = state->base_freq; 609 p->inversion = (reg_83 & 0x08) ? INVERSION_ON : INVERSION_OFF; 610 if (state->config->invert) 611 p->inversion = (p->inversion == INVERSION_ON) ? INVERSION_OFF : INVERSION_ON; 612 p->u.qam.symbol_rate = stv0297_get_symbolrate(state) * 1000; 613 p->u.qam.fec_inner = FEC_NONE; 614 615 switch ((reg_00 >> 4) & 0x7) { 616 case 0: 617 p->u.qam.modulation = QAM_16; 618 break; 619 case 1: 620 p->u.qam.modulation = QAM_32; 621 break; 622 case 2: 623 p->u.qam.modulation = QAM_128; 624 break; 625 case 3: 626 p->u.qam.modulation = QAM_256; 627 break; 628 case 4: 629 p->u.qam.modulation = QAM_64; 630 break; 631 } 632 633 return 0; 634} 635 636static void stv0297_release(struct dvb_frontend *fe) 637{ 638 struct stv0297_state *state = fe->demodulator_priv; 639 kfree(state); 640} 641 642static struct dvb_frontend_ops stv0297_ops; 643 644struct dvb_frontend *stv0297_attach(const struct stv0297_config *config, 645 struct i2c_adapter *i2c) 646{ 647 struct stv0297_state *state = NULL; 648 649 /* allocate memory for the internal state */ 650 state = kmalloc(sizeof(struct stv0297_state), GFP_KERNEL); 651 if (state == NULL) 652 goto error; 653 654 /* setup the state */ 655 state->config = config; 656 state->i2c = i2c; 657 state->last_ber = 0; 658 state->base_freq = 0; 659 660 /* check if the demod is there */ 661 if ((stv0297_readreg(state, 0x80) & 0x70) != 0x20) 662 goto error; 663 664 /* create dvb_frontend */ 665 memcpy(&state->frontend.ops, &stv0297_ops, sizeof(struct dvb_frontend_ops)); 666 state->frontend.demodulator_priv = state; 667 return &state->frontend; 668 669error: 670 kfree(state); 671 return NULL; 672} 673 674static struct dvb_frontend_ops stv0297_ops = { 675 676 .info = { 677 .name = "ST STV0297 DVB-C", 678 .type = FE_QAM, 679 .frequency_min = 64000000, 680 .frequency_max = 1300000000, 681 .frequency_stepsize = 62500, 682 .symbol_rate_min = 870000, 683 .symbol_rate_max = 11700000, 684 .caps = FE_CAN_QAM_16 | FE_CAN_QAM_32 | FE_CAN_QAM_64 | 685 FE_CAN_QAM_128 | FE_CAN_QAM_256 | FE_CAN_FEC_AUTO}, 686 687 .release = stv0297_release, 688 689 .init = stv0297_init, 690 .sleep = stv0297_sleep, 691 .i2c_gate_ctrl = stv0297_i2c_gate_ctrl, 692 693 .set_frontend = stv0297_set_frontend, 694 .get_frontend = stv0297_get_frontend, 695 696 .read_status = stv0297_read_status, 697 .read_ber = stv0297_read_ber, 698 .read_signal_strength = stv0297_read_signal_strength, 699 .read_snr = stv0297_read_snr, 700 .read_ucblocks = stv0297_read_ucblocks, 701}; 702 703MODULE_DESCRIPTION("ST STV0297 DVB-C Demodulator driver"); 704MODULE_AUTHOR("Dennis Noermann and Andrew de Quincey"); 705MODULE_LICENSE("GPL"); 706 707EXPORT_SYMBOL(stv0297_attach); 708