1/* 2 * Copyright (c) 2006 QLogic, Inc. All rights reserved. 3 * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved. 4 * 5 * This software is available to you under a choice of one of two 6 * licenses. You may choose to be licensed under the terms of the GNU 7 * General Public License (GPL) Version 2, available from the file 8 * COPYING in the main directory of this source tree, or the 9 * OpenIB.org BSD license below: 10 * 11 * Redistribution and use in source and binary forms, with or 12 * without modification, are permitted provided that the following 13 * conditions are met: 14 * 15 * - Redistributions of source code must retain the above 16 * copyright notice, this list of conditions and the following 17 * disclaimer. 18 * 19 * - Redistributions in binary form must reproduce the above 20 * copyright notice, this list of conditions and the following 21 * disclaimer in the documentation and/or other materials 22 * provided with the distribution. 23 * 24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 31 * SOFTWARE. 32 */ 33/* 34 * This file contains all of the code that is specific to the 35 * InfiniPath PCIe chip. 36 */ 37 38#include <linux/interrupt.h> 39#include <linux/pci.h> 40#include <linux/delay.h> 41 42 43#include "ipath_kernel.h" 44#include "ipath_registers.h" 45 46static void ipath_setup_pe_setextled(struct ipath_devdata *, u64, u64); 47 48/* 49 * This file contains all the chip-specific register information and 50 * access functions for the QLogic InfiniPath PCI-Express chip. 51 * 52 * This lists the InfiniPath registers, in the actual chip layout. 53 * This structure should never be directly accessed. 54 */ 55struct _infinipath_do_not_use_kernel_regs { 56 unsigned long long Revision; 57 unsigned long long Control; 58 unsigned long long PageAlign; 59 unsigned long long PortCnt; 60 unsigned long long DebugPortSelect; 61 unsigned long long Reserved0; 62 unsigned long long SendRegBase; 63 unsigned long long UserRegBase; 64 unsigned long long CounterRegBase; 65 unsigned long long Scratch; 66 unsigned long long Reserved1; 67 unsigned long long Reserved2; 68 unsigned long long IntBlocked; 69 unsigned long long IntMask; 70 unsigned long long IntStatus; 71 unsigned long long IntClear; 72 unsigned long long ErrorMask; 73 unsigned long long ErrorStatus; 74 unsigned long long ErrorClear; 75 unsigned long long HwErrMask; 76 unsigned long long HwErrStatus; 77 unsigned long long HwErrClear; 78 unsigned long long HwDiagCtrl; 79 unsigned long long MDIO; 80 unsigned long long IBCStatus; 81 unsigned long long IBCCtrl; 82 unsigned long long ExtStatus; 83 unsigned long long ExtCtrl; 84 unsigned long long GPIOOut; 85 unsigned long long GPIOMask; 86 unsigned long long GPIOStatus; 87 unsigned long long GPIOClear; 88 unsigned long long RcvCtrl; 89 unsigned long long RcvBTHQP; 90 unsigned long long RcvHdrSize; 91 unsigned long long RcvHdrCnt; 92 unsigned long long RcvHdrEntSize; 93 unsigned long long RcvTIDBase; 94 unsigned long long RcvTIDCnt; 95 unsigned long long RcvEgrBase; 96 unsigned long long RcvEgrCnt; 97 unsigned long long RcvBufBase; 98 unsigned long long RcvBufSize; 99 unsigned long long RxIntMemBase; 100 unsigned long long RxIntMemSize; 101 unsigned long long RcvPartitionKey; 102 unsigned long long Reserved3; 103 unsigned long long RcvPktLEDCnt; 104 unsigned long long Reserved4[8]; 105 unsigned long long SendCtrl; 106 unsigned long long SendPIOBufBase; 107 unsigned long long SendPIOSize; 108 unsigned long long SendPIOBufCnt; 109 unsigned long long SendPIOAvailAddr; 110 unsigned long long TxIntMemBase; 111 unsigned long long TxIntMemSize; 112 unsigned long long Reserved5; 113 unsigned long long PCIeRBufTestReg0; 114 unsigned long long PCIeRBufTestReg1; 115 unsigned long long Reserved51[6]; 116 unsigned long long SendBufferError; 117 unsigned long long SendBufferErrorCONT1; 118 unsigned long long Reserved6SBE[6]; 119 unsigned long long RcvHdrAddr0; 120 unsigned long long RcvHdrAddr1; 121 unsigned long long RcvHdrAddr2; 122 unsigned long long RcvHdrAddr3; 123 unsigned long long RcvHdrAddr4; 124 unsigned long long Reserved7RHA[11]; 125 unsigned long long RcvHdrTailAddr0; 126 unsigned long long RcvHdrTailAddr1; 127 unsigned long long RcvHdrTailAddr2; 128 unsigned long long RcvHdrTailAddr3; 129 unsigned long long RcvHdrTailAddr4; 130 unsigned long long Reserved8RHTA[11]; 131 unsigned long long Reserved9SW[8]; 132 unsigned long long SerdesConfig0; 133 unsigned long long SerdesConfig1; 134 unsigned long long SerdesStatus; 135 unsigned long long XGXSConfig; 136 unsigned long long IBPLLCfg; 137 unsigned long long Reserved10SW2[3]; 138 unsigned long long PCIEQ0SerdesConfig0; 139 unsigned long long PCIEQ0SerdesConfig1; 140 unsigned long long PCIEQ0SerdesStatus; 141 unsigned long long Reserved11; 142 unsigned long long PCIEQ1SerdesConfig0; 143 unsigned long long PCIEQ1SerdesConfig1; 144 unsigned long long PCIEQ1SerdesStatus; 145 unsigned long long Reserved12; 146}; 147 148#define IPATH_KREG_OFFSET(field) (offsetof(struct \ 149 _infinipath_do_not_use_kernel_regs, field) / sizeof(u64)) 150#define IPATH_CREG_OFFSET(field) (offsetof( \ 151 struct infinipath_counters, field) / sizeof(u64)) 152 153static const struct ipath_kregs ipath_pe_kregs = { 154 .kr_control = IPATH_KREG_OFFSET(Control), 155 .kr_counterregbase = IPATH_KREG_OFFSET(CounterRegBase), 156 .kr_debugportselect = IPATH_KREG_OFFSET(DebugPortSelect), 157 .kr_errorclear = IPATH_KREG_OFFSET(ErrorClear), 158 .kr_errormask = IPATH_KREG_OFFSET(ErrorMask), 159 .kr_errorstatus = IPATH_KREG_OFFSET(ErrorStatus), 160 .kr_extctrl = IPATH_KREG_OFFSET(ExtCtrl), 161 .kr_extstatus = IPATH_KREG_OFFSET(ExtStatus), 162 .kr_gpio_clear = IPATH_KREG_OFFSET(GPIOClear), 163 .kr_gpio_mask = IPATH_KREG_OFFSET(GPIOMask), 164 .kr_gpio_out = IPATH_KREG_OFFSET(GPIOOut), 165 .kr_gpio_status = IPATH_KREG_OFFSET(GPIOStatus), 166 .kr_hwdiagctrl = IPATH_KREG_OFFSET(HwDiagCtrl), 167 .kr_hwerrclear = IPATH_KREG_OFFSET(HwErrClear), 168 .kr_hwerrmask = IPATH_KREG_OFFSET(HwErrMask), 169 .kr_hwerrstatus = IPATH_KREG_OFFSET(HwErrStatus), 170 .kr_ibcctrl = IPATH_KREG_OFFSET(IBCCtrl), 171 .kr_ibcstatus = IPATH_KREG_OFFSET(IBCStatus), 172 .kr_intblocked = IPATH_KREG_OFFSET(IntBlocked), 173 .kr_intclear = IPATH_KREG_OFFSET(IntClear), 174 .kr_intmask = IPATH_KREG_OFFSET(IntMask), 175 .kr_intstatus = IPATH_KREG_OFFSET(IntStatus), 176 .kr_mdio = IPATH_KREG_OFFSET(MDIO), 177 .kr_pagealign = IPATH_KREG_OFFSET(PageAlign), 178 .kr_partitionkey = IPATH_KREG_OFFSET(RcvPartitionKey), 179 .kr_portcnt = IPATH_KREG_OFFSET(PortCnt), 180 .kr_rcvbthqp = IPATH_KREG_OFFSET(RcvBTHQP), 181 .kr_rcvbufbase = IPATH_KREG_OFFSET(RcvBufBase), 182 .kr_rcvbufsize = IPATH_KREG_OFFSET(RcvBufSize), 183 .kr_rcvctrl = IPATH_KREG_OFFSET(RcvCtrl), 184 .kr_rcvegrbase = IPATH_KREG_OFFSET(RcvEgrBase), 185 .kr_rcvegrcnt = IPATH_KREG_OFFSET(RcvEgrCnt), 186 .kr_rcvhdrcnt = IPATH_KREG_OFFSET(RcvHdrCnt), 187 .kr_rcvhdrentsize = IPATH_KREG_OFFSET(RcvHdrEntSize), 188 .kr_rcvhdrsize = IPATH_KREG_OFFSET(RcvHdrSize), 189 .kr_rcvintmembase = IPATH_KREG_OFFSET(RxIntMemBase), 190 .kr_rcvintmemsize = IPATH_KREG_OFFSET(RxIntMemSize), 191 .kr_rcvtidbase = IPATH_KREG_OFFSET(RcvTIDBase), 192 .kr_rcvtidcnt = IPATH_KREG_OFFSET(RcvTIDCnt), 193 .kr_revision = IPATH_KREG_OFFSET(Revision), 194 .kr_scratch = IPATH_KREG_OFFSET(Scratch), 195 .kr_sendbuffererror = IPATH_KREG_OFFSET(SendBufferError), 196 .kr_sendctrl = IPATH_KREG_OFFSET(SendCtrl), 197 .kr_sendpioavailaddr = IPATH_KREG_OFFSET(SendPIOAvailAddr), 198 .kr_sendpiobufbase = IPATH_KREG_OFFSET(SendPIOBufBase), 199 .kr_sendpiobufcnt = IPATH_KREG_OFFSET(SendPIOBufCnt), 200 .kr_sendpiosize = IPATH_KREG_OFFSET(SendPIOSize), 201 .kr_sendregbase = IPATH_KREG_OFFSET(SendRegBase), 202 .kr_txintmembase = IPATH_KREG_OFFSET(TxIntMemBase), 203 .kr_txintmemsize = IPATH_KREG_OFFSET(TxIntMemSize), 204 .kr_userregbase = IPATH_KREG_OFFSET(UserRegBase), 205 .kr_serdesconfig0 = IPATH_KREG_OFFSET(SerdesConfig0), 206 .kr_serdesconfig1 = IPATH_KREG_OFFSET(SerdesConfig1), 207 .kr_serdesstatus = IPATH_KREG_OFFSET(SerdesStatus), 208 .kr_xgxsconfig = IPATH_KREG_OFFSET(XGXSConfig), 209 .kr_ibpllcfg = IPATH_KREG_OFFSET(IBPLLCfg), 210 211 /* 212 * These should not be used directly via ipath_write_kreg64(), 213 * use them with ipath_write_kreg64_port(), 214 */ 215 .kr_rcvhdraddr = IPATH_KREG_OFFSET(RcvHdrAddr0), 216 .kr_rcvhdrtailaddr = IPATH_KREG_OFFSET(RcvHdrTailAddr0), 217 218 /* The rcvpktled register controls one of the debug port signals, so 219 * a packet activity LED can be connected to it. */ 220 .kr_rcvpktledcnt = IPATH_KREG_OFFSET(RcvPktLEDCnt), 221 .kr_pcierbuftestreg0 = IPATH_KREG_OFFSET(PCIeRBufTestReg0), 222 .kr_pcierbuftestreg1 = IPATH_KREG_OFFSET(PCIeRBufTestReg1), 223 .kr_pcieq0serdesconfig0 = IPATH_KREG_OFFSET(PCIEQ0SerdesConfig0), 224 .kr_pcieq0serdesconfig1 = IPATH_KREG_OFFSET(PCIEQ0SerdesConfig1), 225 .kr_pcieq0serdesstatus = IPATH_KREG_OFFSET(PCIEQ0SerdesStatus), 226 .kr_pcieq1serdesconfig0 = IPATH_KREG_OFFSET(PCIEQ1SerdesConfig0), 227 .kr_pcieq1serdesconfig1 = IPATH_KREG_OFFSET(PCIEQ1SerdesConfig1), 228 .kr_pcieq1serdesstatus = IPATH_KREG_OFFSET(PCIEQ1SerdesStatus) 229}; 230 231static const struct ipath_cregs ipath_pe_cregs = { 232 .cr_badformatcnt = IPATH_CREG_OFFSET(RxBadFormatCnt), 233 .cr_erricrccnt = IPATH_CREG_OFFSET(RxICRCErrCnt), 234 .cr_errlinkcnt = IPATH_CREG_OFFSET(RxLinkProblemCnt), 235 .cr_errlpcrccnt = IPATH_CREG_OFFSET(RxLPCRCErrCnt), 236 .cr_errpkey = IPATH_CREG_OFFSET(RxPKeyMismatchCnt), 237 .cr_errrcvflowctrlcnt = IPATH_CREG_OFFSET(RxFlowCtrlErrCnt), 238 .cr_err_rlencnt = IPATH_CREG_OFFSET(RxLenErrCnt), 239 .cr_errslencnt = IPATH_CREG_OFFSET(TxLenErrCnt), 240 .cr_errtidfull = IPATH_CREG_OFFSET(RxTIDFullErrCnt), 241 .cr_errtidvalid = IPATH_CREG_OFFSET(RxTIDValidErrCnt), 242 .cr_errvcrccnt = IPATH_CREG_OFFSET(RxVCRCErrCnt), 243 .cr_ibstatuschange = IPATH_CREG_OFFSET(IBStatusChangeCnt), 244 .cr_intcnt = IPATH_CREG_OFFSET(LBIntCnt), 245 .cr_invalidrlencnt = IPATH_CREG_OFFSET(RxMaxMinLenErrCnt), 246 .cr_invalidslencnt = IPATH_CREG_OFFSET(TxMaxMinLenErrCnt), 247 .cr_lbflowstallcnt = IPATH_CREG_OFFSET(LBFlowStallCnt), 248 .cr_pktrcvcnt = IPATH_CREG_OFFSET(RxDataPktCnt), 249 .cr_pktrcvflowctrlcnt = IPATH_CREG_OFFSET(RxFlowPktCnt), 250 .cr_pktsendcnt = IPATH_CREG_OFFSET(TxDataPktCnt), 251 .cr_pktsendflowcnt = IPATH_CREG_OFFSET(TxFlowPktCnt), 252 .cr_portovflcnt = IPATH_CREG_OFFSET(RxP0HdrEgrOvflCnt), 253 .cr_rcvebpcnt = IPATH_CREG_OFFSET(RxEBPCnt), 254 .cr_rcvovflcnt = IPATH_CREG_OFFSET(RxBufOvflCnt), 255 .cr_senddropped = IPATH_CREG_OFFSET(TxDroppedPktCnt), 256 .cr_sendstallcnt = IPATH_CREG_OFFSET(TxFlowStallCnt), 257 .cr_sendunderruncnt = IPATH_CREG_OFFSET(TxUnderrunCnt), 258 .cr_wordrcvcnt = IPATH_CREG_OFFSET(RxDwordCnt), 259 .cr_wordsendcnt = IPATH_CREG_OFFSET(TxDwordCnt), 260 .cr_unsupvlcnt = IPATH_CREG_OFFSET(TxUnsupVLErrCnt), 261 .cr_rxdroppktcnt = IPATH_CREG_OFFSET(RxDroppedPktCnt), 262 .cr_iblinkerrrecovcnt = IPATH_CREG_OFFSET(IBLinkErrRecoveryCnt), 263 .cr_iblinkdowncnt = IPATH_CREG_OFFSET(IBLinkDownedCnt), 264 .cr_ibsymbolerrcnt = IPATH_CREG_OFFSET(IBSymbolErrCnt) 265}; 266 267/* kr_intstatus, kr_intclear, kr_intmask bits */ 268#define INFINIPATH_I_RCVURG_MASK ((1U<<5)-1) 269#define INFINIPATH_I_RCVAVAIL_MASK ((1U<<5)-1) 270 271/* kr_hwerrclear, kr_hwerrmask, kr_hwerrstatus, bits */ 272#define INFINIPATH_HWE_PCIEMEMPARITYERR_MASK 0x000000000000003fULL 273#define INFINIPATH_HWE_PCIEMEMPARITYERR_SHIFT 0 274#define INFINIPATH_HWE_PCIEPOISONEDTLP 0x0000000010000000ULL 275#define INFINIPATH_HWE_PCIECPLTIMEOUT 0x0000000020000000ULL 276#define INFINIPATH_HWE_PCIEBUSPARITYXTLH 0x0000000040000000ULL 277#define INFINIPATH_HWE_PCIEBUSPARITYXADM 0x0000000080000000ULL 278#define INFINIPATH_HWE_PCIEBUSPARITYRADM 0x0000000100000000ULL 279#define INFINIPATH_HWE_COREPLL_FBSLIP 0x0080000000000000ULL 280#define INFINIPATH_HWE_COREPLL_RFSLIP 0x0100000000000000ULL 281#define INFINIPATH_HWE_PCIE1PLLFAILED 0x0400000000000000ULL 282#define INFINIPATH_HWE_PCIE0PLLFAILED 0x0800000000000000ULL 283#define INFINIPATH_HWE_SERDESPLLFAILED 0x1000000000000000ULL 284 285/* kr_extstatus bits */ 286#define INFINIPATH_EXTS_FREQSEL 0x2 287#define INFINIPATH_EXTS_SERDESSEL 0x4 288#define INFINIPATH_EXTS_MEMBIST_ENDTEST 0x0000000000004000 289#define INFINIPATH_EXTS_MEMBIST_FOUND 0x0000000000008000 290 291#define _IPATH_GPIO_SDA_NUM 1 292#define _IPATH_GPIO_SCL_NUM 0 293 294#define IPATH_GPIO_SDA (1ULL << \ 295 (_IPATH_GPIO_SDA_NUM+INFINIPATH_EXTC_GPIOOE_SHIFT)) 296#define IPATH_GPIO_SCL (1ULL << \ 297 (_IPATH_GPIO_SCL_NUM+INFINIPATH_EXTC_GPIOOE_SHIFT)) 298 299/* 300 * Rev2 silicon allows suppressing check for ArmLaunch errors. 301 * this can speed up short packet sends on systems that do 302 * not guaranteee write-order. 303 */ 304#define INFINIPATH_XGXS_SUPPRESS_ARMLAUNCH_ERR (1ULL<<63) 305 306/* 6120 specific hardware errors... */ 307static const struct ipath_hwerror_msgs ipath_6120_hwerror_msgs[] = { 308 INFINIPATH_HWE_MSG(PCIEPOISONEDTLP, "PCIe Poisoned TLP"), 309 INFINIPATH_HWE_MSG(PCIECPLTIMEOUT, "PCIe completion timeout"), 310 /* 311 * In practice, it's unlikely wthat we'll see PCIe PLL, or bus 312 * parity or memory parity error failures, because most likely we 313 * won't be able to talk to the core of the chip. Nonetheless, we 314 * might see them, if they are in parts of the PCIe core that aren't 315 * essential. 316 */ 317 INFINIPATH_HWE_MSG(PCIE1PLLFAILED, "PCIePLL1"), 318 INFINIPATH_HWE_MSG(PCIE0PLLFAILED, "PCIePLL0"), 319 INFINIPATH_HWE_MSG(PCIEBUSPARITYXTLH, "PCIe XTLH core parity"), 320 INFINIPATH_HWE_MSG(PCIEBUSPARITYXADM, "PCIe ADM TX core parity"), 321 INFINIPATH_HWE_MSG(PCIEBUSPARITYRADM, "PCIe ADM RX core parity"), 322 INFINIPATH_HWE_MSG(RXDSYNCMEMPARITYERR, "Rx Dsync"), 323 INFINIPATH_HWE_MSG(SERDESPLLFAILED, "SerDes PLL"), 324}; 325 326#define TXE_PIO_PARITY ((INFINIPATH_HWE_TXEMEMPARITYERR_PIOBUF | \ 327 INFINIPATH_HWE_TXEMEMPARITYERR_PIOPBC) \ 328 << INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT) 329 330static int ipath_pe_txe_recover(struct ipath_devdata *); 331 332/** 333 * ipath_pe_handle_hwerrors - display hardware errors. 334 * @dd: the infinipath device 335 * @msg: the output buffer 336 * @msgl: the size of the output buffer 337 * 338 * Use same msg buffer as regular errors to avoid excessive stack 339 * use. Most hardware errors are catastrophic, but for right now, 340 * we'll print them and continue. We reuse the same message buffer as 341 * ipath_handle_errors() to avoid excessive stack usage. 342 */ 343static void ipath_pe_handle_hwerrors(struct ipath_devdata *dd, char *msg, 344 size_t msgl) 345{ 346 ipath_err_t hwerrs; 347 u32 bits, ctrl; 348 int isfatal = 0; 349 char bitsmsg[64]; 350 351 hwerrs = ipath_read_kreg64(dd, dd->ipath_kregs->kr_hwerrstatus); 352 if (!hwerrs) { 353 /* 354 * better than printing cofusing messages 355 * This seems to be related to clearing the crc error, or 356 * the pll error during init. 357 */ 358 ipath_cdbg(VERBOSE, "Called but no hardware errors set\n"); 359 return; 360 } else if (hwerrs == ~0ULL) { 361 ipath_dev_err(dd, "Read of hardware error status failed " 362 "(all bits set); ignoring\n"); 363 return; 364 } 365 ipath_stats.sps_hwerrs++; 366 367 /* Always clear the error status register, except MEMBISTFAIL, 368 * regardless of whether we continue or stop using the chip. 369 * We want that set so we know it failed, even across driver reload. 370 * We'll still ignore it in the hwerrmask. We do this partly for 371 * diagnostics, but also for support */ 372 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear, 373 hwerrs&~INFINIPATH_HWE_MEMBISTFAILED); 374 375 hwerrs &= dd->ipath_hwerrmask; 376 377 /* 378 * make sure we get this much out, unless told to be quiet, 379 * or it's occurred within the last 5 seconds 380 */ 381 if ((hwerrs & ~(dd->ipath_lasthwerror | 382 ((INFINIPATH_HWE_TXEMEMPARITYERR_PIOBUF | 383 INFINIPATH_HWE_TXEMEMPARITYERR_PIOPBC) 384 << INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT))) || 385 (ipath_debug & __IPATH_VERBDBG)) 386 dev_info(&dd->pcidev->dev, "Hardware error: hwerr=0x%llx " 387 "(cleared)\n", (unsigned long long) hwerrs); 388 dd->ipath_lasthwerror |= hwerrs; 389 390 if (hwerrs & ~dd->ipath_hwe_bitsextant) 391 ipath_dev_err(dd, "hwerror interrupt with unknown errors " 392 "%llx set\n", (unsigned long long) 393 (hwerrs & ~dd->ipath_hwe_bitsextant)); 394 395 ctrl = ipath_read_kreg32(dd, dd->ipath_kregs->kr_control); 396 if (ctrl & INFINIPATH_C_FREEZEMODE) { 397 /* 398 * parity errors in send memory are recoverable, 399 * just cancel the send (if indicated in * sendbuffererror), 400 * count the occurrence, unfreeze (if no other handled 401 * hardware error bits are set), and continue. They can 402 * occur if a processor speculative read is done to the PIO 403 * buffer while we are sending a packet, for example. 404 */ 405 if ((hwerrs & TXE_PIO_PARITY) && ipath_pe_txe_recover(dd)) 406 hwerrs &= ~TXE_PIO_PARITY; 407 if (hwerrs) { 408 /* 409 * if any set that we aren't ignoring only make the 410 * complaint once, in case it's stuck or recurring, 411 * and we get here multiple times 412 * Force link down, so switch knows, and 413 * LEDs are turned off 414 */ 415 if (dd->ipath_flags & IPATH_INITTED) { 416 ipath_set_linkstate(dd, IPATH_IB_LINKDOWN); 417 ipath_setup_pe_setextled(dd, 418 INFINIPATH_IBCS_L_STATE_DOWN, 419 INFINIPATH_IBCS_LT_STATE_DISABLED); 420 ipath_dev_err(dd, "Fatal Hardware Error (freeze " 421 "mode), no longer usable, SN %.16s\n", 422 dd->ipath_serial); 423 isfatal = 1; 424 } 425 /* 426 * Mark as having had an error for driver, and also 427 * for /sys and status word mapped to user programs. 428 * This marks unit as not usable, until reset 429 */ 430 *dd->ipath_statusp &= ~IPATH_STATUS_IB_READY; 431 *dd->ipath_statusp |= IPATH_STATUS_HWERROR; 432 dd->ipath_flags &= ~IPATH_INITTED; 433 } else { 434 ipath_dbg("Clearing freezemode on ignored hardware " 435 "error\n"); 436 ipath_write_kreg(dd, dd->ipath_kregs->kr_control, 437 dd->ipath_control); 438 } 439 } 440 441 *msg = '\0'; 442 443 if (hwerrs & INFINIPATH_HWE_MEMBISTFAILED) { 444 strlcat(msg, "[Memory BIST test failed, InfiniPath hardware unusable]", 445 msgl); 446 /* ignore from now on, so disable until driver reloaded */ 447 *dd->ipath_statusp |= IPATH_STATUS_HWERROR; 448 dd->ipath_hwerrmask &= ~INFINIPATH_HWE_MEMBISTFAILED; 449 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask, 450 dd->ipath_hwerrmask); 451 } 452 453 ipath_format_hwerrors(hwerrs, 454 ipath_6120_hwerror_msgs, 455 sizeof(ipath_6120_hwerror_msgs)/ 456 sizeof(ipath_6120_hwerror_msgs[0]), 457 msg, msgl); 458 459 if (hwerrs & (INFINIPATH_HWE_PCIEMEMPARITYERR_MASK 460 << INFINIPATH_HWE_PCIEMEMPARITYERR_SHIFT)) { 461 bits = (u32) ((hwerrs >> 462 INFINIPATH_HWE_PCIEMEMPARITYERR_SHIFT) & 463 INFINIPATH_HWE_PCIEMEMPARITYERR_MASK); 464 snprintf(bitsmsg, sizeof bitsmsg, 465 "[PCIe Mem Parity Errs %x] ", bits); 466 strlcat(msg, bitsmsg, msgl); 467 } 468 469#define _IPATH_PLL_FAIL (INFINIPATH_HWE_COREPLL_FBSLIP | \ 470 INFINIPATH_HWE_COREPLL_RFSLIP ) 471 472 if (hwerrs & _IPATH_PLL_FAIL) { 473 snprintf(bitsmsg, sizeof bitsmsg, 474 "[PLL failed (%llx), InfiniPath hardware unusable]", 475 (unsigned long long) hwerrs & _IPATH_PLL_FAIL); 476 strlcat(msg, bitsmsg, msgl); 477 /* ignore from now on, so disable until driver reloaded */ 478 dd->ipath_hwerrmask &= ~(hwerrs & _IPATH_PLL_FAIL); 479 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask, 480 dd->ipath_hwerrmask); 481 } 482 483 if (hwerrs & INFINIPATH_HWE_SERDESPLLFAILED) { 484 /* 485 * If it occurs, it is left masked since the eternal 486 * interface is unused 487 */ 488 dd->ipath_hwerrmask &= ~INFINIPATH_HWE_SERDESPLLFAILED; 489 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask, 490 dd->ipath_hwerrmask); 491 } 492 493 if (*msg) 494 ipath_dev_err(dd, "%s hardware error\n", msg); 495 if (isfatal && !ipath_diag_inuse && dd->ipath_freezemsg) { 496 /* 497 * for /sys status file ; if no trailing } is copied, we'll 498 * know it was truncated. 499 */ 500 snprintf(dd->ipath_freezemsg, dd->ipath_freezelen, 501 "{%s}", msg); 502 } 503} 504 505/** 506 * ipath_pe_boardname - fill in the board name 507 * @dd: the infinipath device 508 * @name: the output buffer 509 * @namelen: the size of the output buffer 510 * 511 * info is based on the board revision register 512 */ 513static int ipath_pe_boardname(struct ipath_devdata *dd, char *name, 514 size_t namelen) 515{ 516 char *n = NULL; 517 u8 boardrev = dd->ipath_boardrev; 518 int ret; 519 520 switch (boardrev) { 521 case 0: 522 n = "InfiniPath_Emulation"; 523 break; 524 case 1: 525 n = "InfiniPath_QLE7140-Bringup"; 526 break; 527 case 2: 528 n = "InfiniPath_QLE7140"; 529 break; 530 case 3: 531 n = "InfiniPath_QMI7140"; 532 break; 533 case 4: 534 n = "InfiniPath_QEM7140"; 535 break; 536 case 5: 537 n = "InfiniPath_QMH7140"; 538 break; 539 case 6: 540 n = "InfiniPath_QLE7142"; 541 break; 542 default: 543 ipath_dev_err(dd, 544 "Don't yet know about board with ID %u\n", 545 boardrev); 546 snprintf(name, namelen, "Unknown_InfiniPath_PCIe_%u", 547 boardrev); 548 break; 549 } 550 if (n) 551 snprintf(name, namelen, "%s", n); 552 553 if (dd->ipath_majrev != 4 || !dd->ipath_minrev || dd->ipath_minrev>2) { 554 ipath_dev_err(dd, "Unsupported InfiniPath hardware revision %u.%u!\n", 555 dd->ipath_majrev, dd->ipath_minrev); 556 ret = 1; 557 } else 558 ret = 0; 559 560 return ret; 561} 562 563/** 564 * ipath_pe_init_hwerrors - enable hardware errors 565 * @dd: the infinipath device 566 * 567 * now that we have finished initializing everything that might reasonably 568 * cause a hardware error, and cleared those errors bits as they occur, 569 * we can enable hardware errors in the mask (potentially enabling 570 * freeze mode), and enable hardware errors as errors (along with 571 * everything else) in errormask 572 */ 573static void ipath_pe_init_hwerrors(struct ipath_devdata *dd) 574{ 575 ipath_err_t val; 576 u64 extsval; 577 578 extsval = ipath_read_kreg64(dd, dd->ipath_kregs->kr_extstatus); 579 580 if (!(extsval & INFINIPATH_EXTS_MEMBIST_ENDTEST)) 581 ipath_dev_err(dd, "MemBIST did not complete!\n"); 582 if (extsval & INFINIPATH_EXTS_MEMBIST_FOUND) 583 ipath_dbg("MemBIST corrected\n"); 584 585 val = ~0ULL; /* barring bugs, all hwerrors become interrupts, */ 586 587 if (!dd->ipath_boardrev) // no PLL for Emulator 588 val &= ~INFINIPATH_HWE_SERDESPLLFAILED; 589 590 if (dd->ipath_minrev < 2) { 591 val &= ~INFINIPATH_HWE_PCIEBUSPARITYRADM; 592 } 593 dd->ipath_hwerrmask = val; 594} 595 596/** 597 * ipath_pe_bringup_serdes - bring up the serdes 598 * @dd: the infinipath device 599 */ 600static int ipath_pe_bringup_serdes(struct ipath_devdata *dd) 601{ 602 u64 val, config1, prev_val; 603 int ret = 0; 604 605 ipath_dbg("Trying to bringup serdes\n"); 606 607 if (ipath_read_kreg64(dd, dd->ipath_kregs->kr_hwerrstatus) & 608 INFINIPATH_HWE_SERDESPLLFAILED) { 609 ipath_dbg("At start, serdes PLL failed bit set " 610 "in hwerrstatus, clearing and continuing\n"); 611 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear, 612 INFINIPATH_HWE_SERDESPLLFAILED); 613 } 614 615 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0); 616 config1 = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig1); 617 618 ipath_cdbg(VERBOSE, "SerDes status config0=%llx config1=%llx, " 619 "xgxsconfig %llx\n", (unsigned long long) val, 620 (unsigned long long) config1, (unsigned long long) 621 ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig)); 622 623 /* 624 * Force reset on, also set rxdetect enable. Must do before reading 625 * serdesstatus at least for simulation, or some of the bits in 626 * serdes status will come back as undefined and cause simulation 627 * failures 628 */ 629 val |= INFINIPATH_SERDC0_RESET_PLL | INFINIPATH_SERDC0_RXDETECT_EN 630 | INFINIPATH_SERDC0_L1PWR_DN; 631 ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val); 632 /* be sure chip saw it */ 633 ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch); 634 udelay(5); /* need pll reset set at least for a bit */ 635 /* 636 * after PLL is reset, set the per-lane Resets and TxIdle and 637 * clear the PLL reset and rxdetect (to get falling edge). 638 * Leave L1PWR bits set (permanently) 639 */ 640 val &= ~(INFINIPATH_SERDC0_RXDETECT_EN | INFINIPATH_SERDC0_RESET_PLL 641 | INFINIPATH_SERDC0_L1PWR_DN); 642 val |= INFINIPATH_SERDC0_RESET_MASK | INFINIPATH_SERDC0_TXIDLE; 643 ipath_cdbg(VERBOSE, "Clearing pll reset and setting lane resets " 644 "and txidle (%llx)\n", (unsigned long long) val); 645 ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val); 646 /* be sure chip saw it */ 647 ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch); 648 /* need PLL reset clear for at least 11 usec before lane 649 * resets cleared; give it a few more to be sure */ 650 udelay(15); 651 val &= ~(INFINIPATH_SERDC0_RESET_MASK | INFINIPATH_SERDC0_TXIDLE); 652 653 ipath_cdbg(VERBOSE, "Clearing lane resets and txidle " 654 "(writing %llx)\n", (unsigned long long) val); 655 ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val); 656 /* be sure chip saw it */ 657 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch); 658 659 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig); 660 prev_val = val; 661 if (((val >> INFINIPATH_XGXS_MDIOADDR_SHIFT) & 662 INFINIPATH_XGXS_MDIOADDR_MASK) != 3) { 663 val &= 664 ~(INFINIPATH_XGXS_MDIOADDR_MASK << 665 INFINIPATH_XGXS_MDIOADDR_SHIFT); 666 /* MDIO address 3 */ 667 val |= 3ULL << INFINIPATH_XGXS_MDIOADDR_SHIFT; 668 } 669 if (val & INFINIPATH_XGXS_RESET) { 670 val &= ~INFINIPATH_XGXS_RESET; 671 } 672 if (((val >> INFINIPATH_XGXS_RX_POL_SHIFT) & 673 INFINIPATH_XGXS_RX_POL_MASK) != dd->ipath_rx_pol_inv ) { 674 /* need to compensate for Tx inversion in partner */ 675 val &= ~(INFINIPATH_XGXS_RX_POL_MASK << 676 INFINIPATH_XGXS_RX_POL_SHIFT); 677 val |= dd->ipath_rx_pol_inv << 678 INFINIPATH_XGXS_RX_POL_SHIFT; 679 } 680 if (dd->ipath_minrev >= 2) { 681 /* Rev 2. can tolerate multiple writes to PBC, and 682 * allowing them can provide lower latency on some 683 * CPUs, but this feature is off by default, only 684 * turned on by setting D63 of XGXSconfig reg. 685 * May want to make this conditional more 686 * fine-grained in future. This is not exactly 687 * related to XGXS, but where the bit ended up. 688 */ 689 val |= INFINIPATH_XGXS_SUPPRESS_ARMLAUNCH_ERR; 690 } 691 if (val != prev_val) 692 ipath_write_kreg(dd, dd->ipath_kregs->kr_xgxsconfig, val); 693 694 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0); 695 696 /* clear current and de-emphasis bits */ 697 config1 &= ~0x0ffffffff00ULL; 698 /* set current to 20ma */ 699 config1 |= 0x00000000000ULL; 700 /* set de-emphasis to -5.68dB */ 701 config1 |= 0x0cccc000000ULL; 702 ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig1, config1); 703 704 ipath_cdbg(VERBOSE, "done: SerDes status config0=%llx " 705 "config1=%llx, sstatus=%llx xgxs=%llx\n", 706 (unsigned long long) val, (unsigned long long) config1, 707 (unsigned long long) 708 ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesstatus), 709 (unsigned long long) 710 ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig)); 711 712 if (!ipath_waitfor_mdio_cmdready(dd)) { 713 ipath_write_kreg( 714 dd, dd->ipath_kregs->kr_mdio, 715 ipath_mdio_req(IPATH_MDIO_CMD_READ, 31, 716 IPATH_MDIO_CTRL_XGXS_REG_8, 0)); 717 if (ipath_waitfor_complete(dd, dd->ipath_kregs->kr_mdio, 718 IPATH_MDIO_DATAVALID, &val)) 719 ipath_dbg("Never got MDIO data for XGXS " 720 "status read\n"); 721 else 722 ipath_cdbg(VERBOSE, "MDIO Read reg8, " 723 "'bank' 31 %x\n", (u32) val); 724 } else 725 ipath_dbg("Never got MDIO cmdready for XGXS status read\n"); 726 727 return ret; 728} 729 730/** 731 * ipath_pe_quiet_serdes - set serdes to txidle 732 * @dd: the infinipath device 733 * Called when driver is being unloaded 734 */ 735static void ipath_pe_quiet_serdes(struct ipath_devdata *dd) 736{ 737 u64 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0); 738 739 val |= INFINIPATH_SERDC0_TXIDLE; 740 ipath_dbg("Setting TxIdleEn on serdes (config0 = %llx)\n", 741 (unsigned long long) val); 742 ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val); 743} 744 745static int ipath_pe_intconfig(struct ipath_devdata *dd) 746{ 747 u32 chiprev; 748 749 /* 750 * If the chip supports added error indication via GPIO pins, 751 * enable interrupts on those bits so the interrupt routine 752 * can count the events. Also set flag so interrupt routine 753 * can know they are expected. 754 */ 755 chiprev = dd->ipath_revision >> INFINIPATH_R_CHIPREVMINOR_SHIFT; 756 if ((chiprev & INFINIPATH_R_CHIPREVMINOR_MASK) > 1) { 757 /* Rev2+ reports extra errors via internal GPIO pins */ 758 dd->ipath_flags |= IPATH_GPIO_ERRINTRS; 759 dd->ipath_gpio_mask |= IPATH_GPIO_ERRINTR_MASK; 760 ipath_write_kreg(dd, dd->ipath_kregs->kr_gpio_mask, 761 dd->ipath_gpio_mask); 762 } 763 return 0; 764} 765 766/** 767 * ipath_setup_pe_setextled - set the state of the two external LEDs 768 * @dd: the infinipath device 769 * @lst: the L state 770 * @ltst: the LT state 771 772 * These LEDs indicate the physical and logical state of IB link. 773 * For this chip (at least with recommended board pinouts), LED1 774 * is Yellow (logical state) and LED2 is Green (physical state), 775 * 776 * Note: We try to match the Mellanox HCA LED behavior as best 777 * we can. Green indicates physical link state is OK (something is 778 * plugged in, and we can train). 779 * Amber indicates the link is logically up (ACTIVE). 780 * Mellanox further blinks the amber LED to indicate data packet 781 * activity, but we have no hardware support for that, so it would 782 * require waking up every 10-20 msecs and checking the counters 783 * on the chip, and then turning the LED off if appropriate. That's 784 * visible overhead, so not something we will do. 785 * 786 */ 787static void ipath_setup_pe_setextled(struct ipath_devdata *dd, u64 lst, 788 u64 ltst) 789{ 790 u64 extctl; 791 792 /* the diags use the LED to indicate diag info, so we leave 793 * the external LED alone when the diags are running */ 794 if (ipath_diag_inuse) 795 return; 796 797 extctl = dd->ipath_extctrl & ~(INFINIPATH_EXTC_LED1PRIPORT_ON | 798 INFINIPATH_EXTC_LED2PRIPORT_ON); 799 800 if (ltst & INFINIPATH_IBCS_LT_STATE_LINKUP) 801 extctl |= INFINIPATH_EXTC_LED2PRIPORT_ON; 802 if (lst == INFINIPATH_IBCS_L_STATE_ACTIVE) 803 extctl |= INFINIPATH_EXTC_LED1PRIPORT_ON; 804 dd->ipath_extctrl = extctl; 805 ipath_write_kreg(dd, dd->ipath_kregs->kr_extctrl, extctl); 806} 807 808/** 809 * ipath_setup_pe_cleanup - clean up any per-chip chip-specific stuff 810 * @dd: the infinipath device 811 * 812 * This is called during driver unload. 813 * We do the pci_disable_msi here, not in generic code, because it 814 * isn't used for the HT chips. If we do end up needing pci_enable_msi 815 * at some point in the future for HT, we'll move the call back 816 * into the main init_one code. 817 */ 818static void ipath_setup_pe_cleanup(struct ipath_devdata *dd) 819{ 820 dd->ipath_msi_lo = 0; /* just in case unload fails */ 821 pci_disable_msi(dd->pcidev); 822} 823 824/** 825 * ipath_setup_pe_config - setup PCIe config related stuff 826 * @dd: the infinipath device 827 * @pdev: the PCI device 828 * 829 * The pci_enable_msi() call will fail on systems with MSI quirks 830 * such as those with AMD8131, even if the device of interest is not 831 * attached to that device, (in the 2.6.13 - 2.6.15 kernels, at least, fixed 832 * late in 2.6.16). 833 * All that can be done is to edit the kernel source to remove the quirk 834 * check until that is fixed. 835 * We do not need to call enable_msi() for our HyperTransport chip, 836 * even though it uses MSI, and we want to avoid the quirk warning, so 837 * So we call enable_msi only for PCIe. If we do end up needing 838 * pci_enable_msi at some point in the future for HT, we'll move the 839 * call back into the main init_one code. 840 * We save the msi lo and hi values, so we can restore them after 841 * chip reset (the kernel PCI infrastructure doesn't yet handle that 842 * correctly). 843 */ 844static int ipath_setup_pe_config(struct ipath_devdata *dd, 845 struct pci_dev *pdev) 846{ 847 int pos, ret; 848 849 dd->ipath_msi_lo = 0; /* used as a flag during reset processing */ 850 ret = pci_enable_msi(dd->pcidev); 851 if (ret) 852 ipath_dev_err(dd, "pci_enable_msi failed: %d, " 853 "interrupts may not work\n", ret); 854 /* continue even if it fails, we may still be OK... */ 855 dd->ipath_irq = pdev->irq; 856 857 if ((pos = pci_find_capability(dd->pcidev, PCI_CAP_ID_MSI))) { 858 u16 control; 859 pci_read_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_LO, 860 &dd->ipath_msi_lo); 861 pci_read_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_HI, 862 &dd->ipath_msi_hi); 863 pci_read_config_word(dd->pcidev, pos + PCI_MSI_FLAGS, 864 &control); 865 /* now save the data (vector) info */ 866 pci_read_config_word(dd->pcidev, 867 pos + ((control & PCI_MSI_FLAGS_64BIT) 868 ? 12 : 8), 869 &dd->ipath_msi_data); 870 ipath_cdbg(VERBOSE, "Read msi data 0x%x from config offset " 871 "0x%x, control=0x%x\n", dd->ipath_msi_data, 872 pos + ((control & PCI_MSI_FLAGS_64BIT) ? 12 : 8), 873 control); 874 /* we save the cachelinesize also, although it doesn't 875 * really matter */ 876 pci_read_config_byte(dd->pcidev, PCI_CACHE_LINE_SIZE, 877 &dd->ipath_pci_cacheline); 878 } else 879 ipath_dev_err(dd, "Can't find MSI capability, " 880 "can't save MSI settings for reset\n"); 881 if ((pos = pci_find_capability(dd->pcidev, PCI_CAP_ID_EXP))) { 882 u16 linkstat; 883 pci_read_config_word(dd->pcidev, pos + PCI_EXP_LNKSTA, 884 &linkstat); 885 linkstat >>= 4; 886 linkstat &= 0x1f; 887 if (linkstat != 8) 888 ipath_dev_err(dd, "PCIe width %u, " 889 "performance reduced\n", linkstat); 890 } 891 else 892 ipath_dev_err(dd, "Can't find PCI Express " 893 "capability!\n"); 894 return 0; 895} 896 897static void ipath_init_pe_variables(struct ipath_devdata *dd) 898{ 899 /* 900 * bits for selecting i2c direction and values, 901 * used for I2C serial flash 902 */ 903 dd->ipath_gpio_sda_num = _IPATH_GPIO_SDA_NUM; 904 dd->ipath_gpio_scl_num = _IPATH_GPIO_SCL_NUM; 905 dd->ipath_gpio_sda = IPATH_GPIO_SDA; 906 dd->ipath_gpio_scl = IPATH_GPIO_SCL; 907 908 /* variables for sanity checking interrupt and errors */ 909 dd->ipath_hwe_bitsextant = 910 (INFINIPATH_HWE_RXEMEMPARITYERR_MASK << 911 INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT) | 912 (INFINIPATH_HWE_TXEMEMPARITYERR_MASK << 913 INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT) | 914 (INFINIPATH_HWE_PCIEMEMPARITYERR_MASK << 915 INFINIPATH_HWE_PCIEMEMPARITYERR_SHIFT) | 916 INFINIPATH_HWE_PCIE1PLLFAILED | 917 INFINIPATH_HWE_PCIE0PLLFAILED | 918 INFINIPATH_HWE_PCIEPOISONEDTLP | 919 INFINIPATH_HWE_PCIECPLTIMEOUT | 920 INFINIPATH_HWE_PCIEBUSPARITYXTLH | 921 INFINIPATH_HWE_PCIEBUSPARITYXADM | 922 INFINIPATH_HWE_PCIEBUSPARITYRADM | 923 INFINIPATH_HWE_MEMBISTFAILED | 924 INFINIPATH_HWE_COREPLL_FBSLIP | 925 INFINIPATH_HWE_COREPLL_RFSLIP | 926 INFINIPATH_HWE_SERDESPLLFAILED | 927 INFINIPATH_HWE_IBCBUSTOSPCPARITYERR | 928 INFINIPATH_HWE_IBCBUSFRSPCPARITYERR; 929 dd->ipath_i_bitsextant = 930 (INFINIPATH_I_RCVURG_MASK << INFINIPATH_I_RCVURG_SHIFT) | 931 (INFINIPATH_I_RCVAVAIL_MASK << 932 INFINIPATH_I_RCVAVAIL_SHIFT) | 933 INFINIPATH_I_ERROR | INFINIPATH_I_SPIOSENT | 934 INFINIPATH_I_SPIOBUFAVAIL | INFINIPATH_I_GPIO; 935 dd->ipath_e_bitsextant = 936 INFINIPATH_E_RFORMATERR | INFINIPATH_E_RVCRC | 937 INFINIPATH_E_RICRC | INFINIPATH_E_RMINPKTLEN | 938 INFINIPATH_E_RMAXPKTLEN | INFINIPATH_E_RLONGPKTLEN | 939 INFINIPATH_E_RSHORTPKTLEN | INFINIPATH_E_RUNEXPCHAR | 940 INFINIPATH_E_RUNSUPVL | INFINIPATH_E_REBP | 941 INFINIPATH_E_RIBFLOW | INFINIPATH_E_RBADVERSION | 942 INFINIPATH_E_RRCVEGRFULL | INFINIPATH_E_RRCVHDRFULL | 943 INFINIPATH_E_RBADTID | INFINIPATH_E_RHDRLEN | 944 INFINIPATH_E_RHDR | INFINIPATH_E_RIBLOSTLINK | 945 INFINIPATH_E_SMINPKTLEN | INFINIPATH_E_SMAXPKTLEN | 946 INFINIPATH_E_SUNDERRUN | INFINIPATH_E_SPKTLEN | 947 INFINIPATH_E_SDROPPEDSMPPKT | INFINIPATH_E_SDROPPEDDATAPKT | 948 INFINIPATH_E_SPIOARMLAUNCH | INFINIPATH_E_SUNEXPERRPKTNUM | 949 INFINIPATH_E_SUNSUPVL | INFINIPATH_E_IBSTATUSCHANGED | 950 INFINIPATH_E_INVALIDADDR | INFINIPATH_E_RESET | 951 INFINIPATH_E_HARDWARE; 952 953 dd->ipath_i_rcvavail_mask = INFINIPATH_I_RCVAVAIL_MASK; 954 dd->ipath_i_rcvurg_mask = INFINIPATH_I_RCVURG_MASK; 955} 956 957/* setup the MSI stuff again after a reset. I'd like to just call 958 * pci_enable_msi() and request_irq() again, but when I do that, 959 * the MSI enable bit doesn't get set in the command word, and 960 * we switch to to a different interrupt vector, which is confusing, 961 * so I instead just do it all inline. Perhaps somehow can tie this 962 * into the PCIe hotplug support at some point 963 * Note, because I'm doing it all here, I don't call pci_disable_msi() 964 * or free_irq() at the start of ipath_setup_pe_reset(). 965 */ 966static int ipath_reinit_msi(struct ipath_devdata *dd) 967{ 968 int pos; 969 u16 control; 970 int ret; 971 972 if (!dd->ipath_msi_lo) { 973 dev_info(&dd->pcidev->dev, "Can't restore MSI config, " 974 "initial setup failed?\n"); 975 ret = 0; 976 goto bail; 977 } 978 979 if (!(pos = pci_find_capability(dd->pcidev, PCI_CAP_ID_MSI))) { 980 ipath_dev_err(dd, "Can't find MSI capability, " 981 "can't restore MSI settings\n"); 982 ret = 0; 983 goto bail; 984 } 985 ipath_cdbg(VERBOSE, "Writing msi_lo 0x%x to config offset 0x%x\n", 986 dd->ipath_msi_lo, pos + PCI_MSI_ADDRESS_LO); 987 pci_write_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_LO, 988 dd->ipath_msi_lo); 989 ipath_cdbg(VERBOSE, "Writing msi_lo 0x%x to config offset 0x%x\n", 990 dd->ipath_msi_hi, pos + PCI_MSI_ADDRESS_HI); 991 pci_write_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_HI, 992 dd->ipath_msi_hi); 993 pci_read_config_word(dd->pcidev, pos + PCI_MSI_FLAGS, &control); 994 if (!(control & PCI_MSI_FLAGS_ENABLE)) { 995 ipath_cdbg(VERBOSE, "MSI control at off %x was %x, " 996 "setting MSI enable (%x)\n", pos + PCI_MSI_FLAGS, 997 control, control | PCI_MSI_FLAGS_ENABLE); 998 control |= PCI_MSI_FLAGS_ENABLE; 999 pci_write_config_word(dd->pcidev, pos + PCI_MSI_FLAGS, 1000 control); 1001 } 1002 /* now rewrite the data (vector) info */ 1003 pci_write_config_word(dd->pcidev, pos + 1004 ((control & PCI_MSI_FLAGS_64BIT) ? 12 : 8), 1005 dd->ipath_msi_data); 1006 /* we restore the cachelinesize also, although it doesn't really 1007 * matter */ 1008 pci_write_config_byte(dd->pcidev, PCI_CACHE_LINE_SIZE, 1009 dd->ipath_pci_cacheline); 1010 /* and now set the pci master bit again */ 1011 pci_set_master(dd->pcidev); 1012 ret = 1; 1013 1014bail: 1015 return ret; 1016} 1017 1018/* This routine sleeps, so it can only be called from user context, not 1019 * from interrupt context. If we need interrupt context, we can split 1020 * it into two routines. 1021*/ 1022static int ipath_setup_pe_reset(struct ipath_devdata *dd) 1023{ 1024 u64 val; 1025 int i; 1026 int ret; 1027 1028 /* Use ERROR so it shows up in logs, etc. */ 1029 ipath_dev_err(dd, "Resetting InfiniPath unit %u\n", dd->ipath_unit); 1030 /* keep chip from being accessed in a few places */ 1031 dd->ipath_flags &= ~(IPATH_INITTED|IPATH_PRESENT); 1032 val = dd->ipath_control | INFINIPATH_C_RESET; 1033 ipath_write_kreg(dd, dd->ipath_kregs->kr_control, val); 1034 mb(); 1035 1036 for (i = 1; i <= 5; i++) { 1037 int r; 1038 /* allow MBIST, etc. to complete; longer on each retry. 1039 * We sometimes get machine checks from bus timeout if no 1040 * response, so for now, make it *really* long. 1041 */ 1042 msleep(1000 + (1 + i) * 2000); 1043 if ((r = 1044 pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_0, 1045 dd->ipath_pcibar0))) 1046 ipath_dev_err(dd, "rewrite of BAR0 failed: %d\n", 1047 r); 1048 if ((r = 1049 pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_1, 1050 dd->ipath_pcibar1))) 1051 ipath_dev_err(dd, "rewrite of BAR1 failed: %d\n", 1052 r); 1053 /* now re-enable memory access */ 1054 if ((r = pci_enable_device(dd->pcidev))) 1055 ipath_dev_err(dd, "pci_enable_device failed after " 1056 "reset: %d\n", r); 1057 /* whether it worked or not, mark as present, again */ 1058 dd->ipath_flags |= IPATH_PRESENT; 1059 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_revision); 1060 if (val == dd->ipath_revision) { 1061 ipath_cdbg(VERBOSE, "Got matching revision " 1062 "register %llx on try %d\n", 1063 (unsigned long long) val, i); 1064 ret = ipath_reinit_msi(dd); 1065 goto bail; 1066 } 1067 /* Probably getting -1 back */ 1068 ipath_dbg("Didn't get expected revision register, " 1069 "got %llx, try %d\n", (unsigned long long) val, 1070 i + 1); 1071 } 1072 ret = 0; /* failed */ 1073 1074bail: 1075 return ret; 1076} 1077 1078/** 1079 * ipath_pe_put_tid - write a TID in chip 1080 * @dd: the infinipath device 1081 * @tidptr: pointer to the expected TID (in chip) to udpate 1082 * @tidtype: 0 for eager, 1 for expected 1083 * @pa: physical address of in memory buffer; ipath_tidinvalid if freeing 1084 * 1085 * This exists as a separate routine to allow for special locking etc. 1086 * It's used for both the full cleanup on exit, as well as the normal 1087 * setup and teardown. 1088 */ 1089static void ipath_pe_put_tid(struct ipath_devdata *dd, u64 __iomem *tidptr, 1090 u32 type, unsigned long pa) 1091{ 1092 u32 __iomem *tidp32 = (u32 __iomem *)tidptr; 1093 unsigned long flags = 0; /* keep gcc quiet */ 1094 1095 if (pa != dd->ipath_tidinvalid) { 1096 if (pa & ((1U << 11) - 1)) { 1097 dev_info(&dd->pcidev->dev, "BUG: physaddr %lx " 1098 "not 4KB aligned!\n", pa); 1099 return; 1100 } 1101 pa >>= 11; 1102 /* paranoia check */ 1103 if (pa & (7<<29)) 1104 ipath_dev_err(dd, 1105 "BUG: Physical page address 0x%lx " 1106 "has bits set in 31-29\n", pa); 1107 1108 if (type == 0) 1109 pa |= dd->ipath_tidtemplate; 1110 else /* for now, always full 4KB page */ 1111 pa |= 2 << 29; 1112 } 1113 1114 spin_lock_irqsave(&dd->ipath_tid_lock, flags); 1115 ipath_write_kreg(dd, dd->ipath_kregs->kr_scratch, 0xfeeddeaf); 1116 if (dd->ipath_kregbase) 1117 writel(pa, tidp32); 1118 ipath_write_kreg(dd, dd->ipath_kregs->kr_scratch, 0xdeadbeef); 1119 mmiowb(); 1120 spin_unlock_irqrestore(&dd->ipath_tid_lock, flags); 1121} 1122/** 1123 * ipath_pe_put_tid_2 - write a TID in chip, Revision 2 or higher 1124 * @dd: the infinipath device 1125 * @tidptr: pointer to the expected TID (in chip) to udpate 1126 * @tidtype: 0 for eager, 1 for expected 1127 * @pa: physical address of in memory buffer; ipath_tidinvalid if freeing 1128 * 1129 * This exists as a separate routine to allow for selection of the 1130 * appropriate "flavor". The static calls in cleanup just use the 1131 * revision-agnostic form, as they are not performance critical. 1132 */ 1133static void ipath_pe_put_tid_2(struct ipath_devdata *dd, u64 __iomem *tidptr, 1134 u32 type, unsigned long pa) 1135{ 1136 u32 __iomem *tidp32 = (u32 __iomem *)tidptr; 1137 1138 if (pa != dd->ipath_tidinvalid) { 1139 if (pa & ((1U << 11) - 1)) { 1140 dev_info(&dd->pcidev->dev, "BUG: physaddr %lx " 1141 "not 2KB aligned!\n", pa); 1142 return; 1143 } 1144 pa >>= 11; 1145 /* paranoia check */ 1146 if (pa & (7<<29)) 1147 ipath_dev_err(dd, 1148 "BUG: Physical page address 0x%lx " 1149 "has bits set in 31-29\n", pa); 1150 1151 if (type == 0) 1152 pa |= dd->ipath_tidtemplate; 1153 else /* for now, always full 4KB page */ 1154 pa |= 2 << 29; 1155 } 1156 if (dd->ipath_kregbase) 1157 writel(pa, tidp32); 1158 mmiowb(); 1159} 1160 1161 1162/** 1163 * ipath_pe_clear_tid - clear all TID entries for a port, expected and eager 1164 * @dd: the infinipath device 1165 * @port: the port 1166 * 1167 * clear all TID entries for a port, expected and eager. 1168 * Used from ipath_close(). On this chip, TIDs are only 32 bits, 1169 * not 64, but they are still on 64 bit boundaries, so tidbase 1170 * is declared as u64 * for the pointer math, even though we write 32 bits 1171 */ 1172static void ipath_pe_clear_tids(struct ipath_devdata *dd, unsigned port) 1173{ 1174 u64 __iomem *tidbase; 1175 unsigned long tidinv; 1176 int i; 1177 1178 if (!dd->ipath_kregbase) 1179 return; 1180 1181 ipath_cdbg(VERBOSE, "Invalidate TIDs for port %u\n", port); 1182 1183 tidinv = dd->ipath_tidinvalid; 1184 tidbase = (u64 __iomem *) 1185 ((char __iomem *)(dd->ipath_kregbase) + 1186 dd->ipath_rcvtidbase + 1187 port * dd->ipath_rcvtidcnt * sizeof(*tidbase)); 1188 1189 for (i = 0; i < dd->ipath_rcvtidcnt; i++) 1190 ipath_pe_put_tid(dd, &tidbase[i], 0, tidinv); 1191 1192 tidbase = (u64 __iomem *) 1193 ((char __iomem *)(dd->ipath_kregbase) + 1194 dd->ipath_rcvegrbase + 1195 port * dd->ipath_rcvegrcnt * sizeof(*tidbase)); 1196 1197 for (i = 0; i < dd->ipath_rcvegrcnt; i++) 1198 ipath_pe_put_tid(dd, &tidbase[i], 1, tidinv); 1199} 1200 1201/** 1202 * ipath_pe_tidtemplate - setup constants for TID updates 1203 * @dd: the infinipath device 1204 * 1205 * We setup stuff that we use a lot, to avoid calculating each time 1206 */ 1207static void ipath_pe_tidtemplate(struct ipath_devdata *dd) 1208{ 1209 u32 egrsize = dd->ipath_rcvegrbufsize; 1210 1211 /* For now, we always allocate 4KB buffers (at init) so we can 1212 * receive max size packets. We may want a module parameter to 1213 * specify 2KB or 4KB and/or make be per port instead of per device 1214 * for those who want to reduce memory footprint. Note that the 1215 * ipath_rcvhdrentsize size must be large enough to hold the largest 1216 * IB header (currently 96 bytes) that we expect to handle (plus of 1217 * course the 2 dwords of RHF). 1218 */ 1219 if (egrsize == 2048) 1220 dd->ipath_tidtemplate = 1U << 29; 1221 else if (egrsize == 4096) 1222 dd->ipath_tidtemplate = 2U << 29; 1223 else { 1224 egrsize = 4096; 1225 dev_info(&dd->pcidev->dev, "BUG: unsupported egrbufsize " 1226 "%u, using %u\n", dd->ipath_rcvegrbufsize, 1227 egrsize); 1228 dd->ipath_tidtemplate = 2U << 29; 1229 } 1230 dd->ipath_tidinvalid = 0; 1231} 1232 1233static int ipath_pe_early_init(struct ipath_devdata *dd) 1234{ 1235 dd->ipath_flags |= IPATH_4BYTE_TID; 1236 1237 /* 1238 * For openfabrics, we need to be able to handle an IB header of 1239 * 24 dwords. HT chip has arbitrary sized receive buffers, so we 1240 * made them the same size as the PIO buffers. This chip does not 1241 * handle arbitrary size buffers, so we need the header large enough 1242 * to handle largest IB header, but still have room for a 2KB MTU 1243 * standard IB packet. 1244 */ 1245 dd->ipath_rcvhdrentsize = 24; 1246 dd->ipath_rcvhdrsize = IPATH_DFLT_RCVHDRSIZE; 1247 1248 /* 1249 * To truly support a 4KB MTU (for usermode), we need to 1250 * bump this to a larger value. For now, we use them for 1251 * the kernel only. 1252 */ 1253 dd->ipath_rcvegrbufsize = 2048; 1254 /* 1255 * the min() check here is currently a nop, but it may not always 1256 * be, depending on just how we do ipath_rcvegrbufsize 1257 */ 1258 dd->ipath_ibmaxlen = min(dd->ipath_piosize2k, 1259 dd->ipath_rcvegrbufsize + 1260 (dd->ipath_rcvhdrentsize << 2)); 1261 dd->ipath_init_ibmaxlen = dd->ipath_ibmaxlen; 1262 1263 /* 1264 * We can request a receive interrupt for 1 or 1265 * more packets from current offset. For now, we set this 1266 * up for a single packet. 1267 */ 1268 dd->ipath_rhdrhead_intr_off = 1ULL<<32; 1269 1270 ipath_get_eeprom_info(dd); 1271 1272 return 0; 1273} 1274 1275int __attribute__((weak)) ipath_unordered_wc(void) 1276{ 1277 return 0; 1278} 1279 1280/** 1281 * ipath_init_pe_get_base_info - set chip-specific flags for user code 1282 * @pd: the infinipath port 1283 * @kbase: ipath_base_info pointer 1284 * 1285 * We set the PCIE flag because the lower bandwidth on PCIe vs 1286 * HyperTransport can affect some user packet algorithms. 1287 */ 1288static int ipath_pe_get_base_info(struct ipath_portdata *pd, void *kbase) 1289{ 1290 struct ipath_base_info *kinfo = kbase; 1291 struct ipath_devdata *dd; 1292 1293 if (ipath_unordered_wc()) { 1294 kinfo->spi_runtime_flags |= IPATH_RUNTIME_FORCE_WC_ORDER; 1295 ipath_cdbg(PROC, "Intel processor, forcing WC order\n"); 1296 } 1297 else 1298 ipath_cdbg(PROC, "Not Intel processor, WC ordered\n"); 1299 1300 if (pd == NULL) 1301 goto done; 1302 1303 dd = pd->port_dd; 1304 1305 if (dd != NULL && dd->ipath_minrev >= 2) { 1306 ipath_cdbg(PROC, "IBA6120 Rev2, allow multiple PBC write\n"); 1307 kinfo->spi_runtime_flags |= IPATH_RUNTIME_PBC_REWRITE; 1308 ipath_cdbg(PROC, "IBA6120 Rev2, allow loose DMA alignment\n"); 1309 kinfo->spi_runtime_flags |= IPATH_RUNTIME_LOOSE_DMA_ALIGN; 1310 } 1311 1312done: 1313 kinfo->spi_runtime_flags |= IPATH_RUNTIME_PCIE; 1314 return 0; 1315} 1316 1317static void ipath_pe_free_irq(struct ipath_devdata *dd) 1318{ 1319 free_irq(dd->ipath_irq, dd); 1320 dd->ipath_irq = 0; 1321} 1322 1323/* 1324 * On platforms using this chip, and not having ordered WC stores, we 1325 * can get TXE parity errors due to speculative reads to the PIO buffers, 1326 * and this, due to a chip bug can result in (many) false parity error 1327 * reports. So it's a debug print on those, and an info print on systems 1328 * where the speculative reads don't occur. 1329 * Because we can get lots of false errors, we have no upper limit 1330 * on recovery attempts on those platforms. 1331 */ 1332static int ipath_pe_txe_recover(struct ipath_devdata *dd) 1333{ 1334 if (ipath_unordered_wc()) 1335 ipath_dbg("Recovering from TXE PIO parity error\n"); 1336 else { 1337 int cnt = ++ipath_stats.sps_txeparity; 1338 if (cnt >= IPATH_MAX_PARITY_ATTEMPTS) { 1339 if (cnt == IPATH_MAX_PARITY_ATTEMPTS) 1340 ipath_dev_err(dd, 1341 "Too many attempts to recover from " 1342 "TXE parity, giving up\n"); 1343 return 0; 1344 } 1345 dev_info(&dd->pcidev->dev, 1346 "Recovering from TXE PIO parity error\n"); 1347 } 1348 ipath_disarm_senderrbufs(dd, 1); 1349 return 1; 1350} 1351 1352/** 1353 * ipath_init_iba6120_funcs - set up the chip-specific function pointers 1354 * @dd: the infinipath device 1355 * 1356 * This is global, and is called directly at init to set up the 1357 * chip-specific function pointers for later use. 1358 */ 1359void ipath_init_iba6120_funcs(struct ipath_devdata *dd) 1360{ 1361 dd->ipath_f_intrsetup = ipath_pe_intconfig; 1362 dd->ipath_f_bus = ipath_setup_pe_config; 1363 dd->ipath_f_reset = ipath_setup_pe_reset; 1364 dd->ipath_f_get_boardname = ipath_pe_boardname; 1365 dd->ipath_f_init_hwerrors = ipath_pe_init_hwerrors; 1366 dd->ipath_f_early_init = ipath_pe_early_init; 1367 dd->ipath_f_handle_hwerrors = ipath_pe_handle_hwerrors; 1368 dd->ipath_f_quiet_serdes = ipath_pe_quiet_serdes; 1369 dd->ipath_f_bringup_serdes = ipath_pe_bringup_serdes; 1370 dd->ipath_f_clear_tids = ipath_pe_clear_tids; 1371 if (dd->ipath_minrev >= 2) 1372 dd->ipath_f_put_tid = ipath_pe_put_tid_2; 1373 else 1374 dd->ipath_f_put_tid = ipath_pe_put_tid; 1375 dd->ipath_f_cleanup = ipath_setup_pe_cleanup; 1376 dd->ipath_f_setextled = ipath_setup_pe_setextled; 1377 dd->ipath_f_get_base_info = ipath_pe_get_base_info; 1378 dd->ipath_f_free_irq = ipath_pe_free_irq; 1379 1380 /* initialize chip-specific variables */ 1381 dd->ipath_f_tidtemplate = ipath_pe_tidtemplate; 1382 1383 /* 1384 * setup the register offsets, since they are different for each 1385 * chip 1386 */ 1387 dd->ipath_kregs = &ipath_pe_kregs; 1388 dd->ipath_cregs = &ipath_pe_cregs; 1389 1390 ipath_init_pe_variables(dd); 1391} 1392