1/* linux/drivers/i2c/busses/i2c-s3c2410.c
2 *
3 * Copyright (C) 2004,2005 Simtec Electronics
4 *	Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C2410 I2C Controller
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
21*/
22
23#include <linux/kernel.h>
24#include <linux/module.h>
25
26#include <linux/i2c.h>
27#include <linux/i2c-id.h>
28#include <linux/init.h>
29#include <linux/time.h>
30#include <linux/interrupt.h>
31#include <linux/delay.h>
32#include <linux/errno.h>
33#include <linux/err.h>
34#include <linux/platform_device.h>
35#include <linux/clk.h>
36
37#include <asm/hardware.h>
38#include <asm/irq.h>
39#include <asm/io.h>
40
41#include <asm/arch/regs-gpio.h>
42#include <asm/arch/regs-iic.h>
43#include <asm/arch/iic.h>
44
45/* i2c controller state */
46
47enum s3c24xx_i2c_state {
48	STATE_IDLE,
49	STATE_START,
50	STATE_READ,
51	STATE_WRITE,
52	STATE_STOP
53};
54
55struct s3c24xx_i2c {
56	spinlock_t		lock;
57	wait_queue_head_t	wait;
58
59	struct i2c_msg		*msg;
60	unsigned int		msg_num;
61	unsigned int		msg_idx;
62	unsigned int		msg_ptr;
63
64	unsigned int		tx_setup;
65
66	enum s3c24xx_i2c_state	state;
67
68	void __iomem		*regs;
69	struct clk		*clk;
70	struct device		*dev;
71	struct resource		*irq;
72	struct resource		*ioarea;
73	struct i2c_adapter	adap;
74};
75
76/* default platform data to use if not supplied in the platform_device
77*/
78
79static struct s3c2410_platform_i2c s3c24xx_i2c_default_platform = {
80	.flags		= 0,
81	.slave_addr	= 0x10,
82	.bus_freq	= 100*1000,
83	.max_freq	= 400*1000,
84	.sda_delay	= S3C2410_IICLC_SDA_DELAY5 | S3C2410_IICLC_FILTER_ON,
85};
86
87/* s3c24xx_i2c_is2440()
88 *
89 * return true is this is an s3c2440
90*/
91
92static inline int s3c24xx_i2c_is2440(struct s3c24xx_i2c *i2c)
93{
94	struct platform_device *pdev = to_platform_device(i2c->dev);
95
96	return !strcmp(pdev->name, "s3c2440-i2c");
97}
98
99
100/* s3c24xx_i2c_get_platformdata
101 *
102 * get the platform data associated with the given device, or return
103 * the default if there is none
104*/
105
106static inline struct s3c2410_platform_i2c *s3c24xx_i2c_get_platformdata(struct device *dev)
107{
108	if (dev->platform_data != NULL)
109		return (struct s3c2410_platform_i2c *)dev->platform_data;
110
111	return &s3c24xx_i2c_default_platform;
112}
113
114/* s3c24xx_i2c_master_complete
115 *
116 * complete the message and wake up the caller, using the given return code,
117 * or zero to mean ok.
118*/
119
120static inline void s3c24xx_i2c_master_complete(struct s3c24xx_i2c *i2c, int ret)
121{
122	dev_dbg(i2c->dev, "master_complete %d\n", ret);
123
124	i2c->msg_ptr = 0;
125	i2c->msg = NULL;
126	i2c->msg_idx ++;
127	i2c->msg_num = 0;
128	if (ret)
129		i2c->msg_idx = ret;
130
131	wake_up(&i2c->wait);
132}
133
134static inline void s3c24xx_i2c_disable_ack(struct s3c24xx_i2c *i2c)
135{
136	unsigned long tmp;
137
138	tmp = readl(i2c->regs + S3C2410_IICCON);
139	writel(tmp & ~S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON);
140
141}
142
143static inline void s3c24xx_i2c_enable_ack(struct s3c24xx_i2c *i2c)
144{
145	unsigned long tmp;
146
147	tmp = readl(i2c->regs + S3C2410_IICCON);
148	writel(tmp | S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON);
149
150}
151
152/* irq enable/disable functions */
153
154static inline void s3c24xx_i2c_disable_irq(struct s3c24xx_i2c *i2c)
155{
156	unsigned long tmp;
157
158	tmp = readl(i2c->regs + S3C2410_IICCON);
159	writel(tmp & ~S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON);
160}
161
162static inline void s3c24xx_i2c_enable_irq(struct s3c24xx_i2c *i2c)
163{
164	unsigned long tmp;
165
166	tmp = readl(i2c->regs + S3C2410_IICCON);
167	writel(tmp | S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON);
168}
169
170
171/* s3c24xx_i2c_message_start
172 *
173 * put the start of a message onto the bus
174*/
175
176static void s3c24xx_i2c_message_start(struct s3c24xx_i2c *i2c,
177				      struct i2c_msg *msg)
178{
179	unsigned int addr = (msg->addr & 0x7f) << 1;
180	unsigned long stat;
181	unsigned long iiccon;
182
183	stat = 0;
184	stat |=  S3C2410_IICSTAT_TXRXEN;
185
186	if (msg->flags & I2C_M_RD) {
187		stat |= S3C2410_IICSTAT_MASTER_RX;
188		addr |= 1;
189	} else
190		stat |= S3C2410_IICSTAT_MASTER_TX;
191
192	if (msg->flags & I2C_M_REV_DIR_ADDR)
193		addr ^= 1;
194
195	// todo - check for wether ack wanted or not
196	s3c24xx_i2c_enable_ack(i2c);
197
198	iiccon = readl(i2c->regs + S3C2410_IICCON);
199	writel(stat, i2c->regs + S3C2410_IICSTAT);
200
201	dev_dbg(i2c->dev, "START: %08lx to IICSTAT, %02x to DS\n", stat, addr);
202	writeb(addr, i2c->regs + S3C2410_IICDS);
203
204	/* delay here to ensure the data byte has gotten onto the bus
205	 * before the transaction is started */
206
207	ndelay(i2c->tx_setup);
208
209	dev_dbg(i2c->dev, "iiccon, %08lx\n", iiccon);
210	writel(iiccon, i2c->regs + S3C2410_IICCON);
211
212	stat |=  S3C2410_IICSTAT_START;
213	writel(stat, i2c->regs + S3C2410_IICSTAT);
214}
215
216static inline void s3c24xx_i2c_stop(struct s3c24xx_i2c *i2c, int ret)
217{
218	unsigned long iicstat = readl(i2c->regs + S3C2410_IICSTAT);
219
220	dev_dbg(i2c->dev, "STOP\n");
221
222	/* stop the transfer */
223	iicstat &= ~ S3C2410_IICSTAT_START;
224	writel(iicstat, i2c->regs + S3C2410_IICSTAT);
225
226	i2c->state = STATE_STOP;
227
228	s3c24xx_i2c_master_complete(i2c, ret);
229	s3c24xx_i2c_disable_irq(i2c);
230}
231
232/* helper functions to determine the current state in the set of
233 * messages we are sending */
234
235/* is_lastmsg()
236 *
237 * returns TRUE if the current message is the last in the set
238*/
239
240static inline int is_lastmsg(struct s3c24xx_i2c *i2c)
241{
242	return i2c->msg_idx >= (i2c->msg_num - 1);
243}
244
245/* is_msglast
246 *
247 * returns TRUE if we this is the last byte in the current message
248*/
249
250static inline int is_msglast(struct s3c24xx_i2c *i2c)
251{
252	return i2c->msg_ptr == i2c->msg->len-1;
253}
254
255/* is_msgend
256 *
257 * returns TRUE if we reached the end of the current message
258*/
259
260static inline int is_msgend(struct s3c24xx_i2c *i2c)
261{
262	return i2c->msg_ptr >= i2c->msg->len;
263}
264
265/* i2s_s3c_irq_nextbyte
266 *
267 * process an interrupt and work out what to do
268 */
269
270static int i2s_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long iicstat)
271{
272	unsigned long tmp;
273	unsigned char byte;
274	int ret = 0;
275
276	switch (i2c->state) {
277
278	case STATE_IDLE:
279		dev_err(i2c->dev, "%s: called in STATE_IDLE\n", __FUNCTION__);
280		goto out;
281		break;
282
283	case STATE_STOP:
284		dev_err(i2c->dev, "%s: called in STATE_STOP\n", __FUNCTION__);
285		s3c24xx_i2c_disable_irq(i2c);
286		goto out_ack;
287
288	case STATE_START:
289		/* last thing we did was send a start condition on the
290		 * bus, or started a new i2c message
291		 */
292
293		if (iicstat  & S3C2410_IICSTAT_LASTBIT &&
294		    !(i2c->msg->flags & I2C_M_IGNORE_NAK)) {
295			/* ack was not received... */
296
297			dev_dbg(i2c->dev, "ack was not received\n");
298			s3c24xx_i2c_stop(i2c, -EREMOTEIO);
299			goto out_ack;
300		}
301
302		if (i2c->msg->flags & I2C_M_RD)
303			i2c->state = STATE_READ;
304		else
305			i2c->state = STATE_WRITE;
306
307		/* terminate the transfer if there is nothing to do
308		 * (used by the i2c probe to find devices */
309
310		if (is_lastmsg(i2c) && i2c->msg->len == 0) {
311			s3c24xx_i2c_stop(i2c, 0);
312			goto out_ack;
313		}
314
315		if (i2c->state == STATE_READ)
316			goto prepare_read;
317
318		/* fall through to the write state, as we will need to
319		 * send a byte as well */
320
321	case STATE_WRITE:
322		/* we are writing data to the device... check for the
323		 * end of the message, and if so, work out what to do
324		 */
325
326	retry_write:
327		if (!is_msgend(i2c)) {
328			byte = i2c->msg->buf[i2c->msg_ptr++];
329			writeb(byte, i2c->regs + S3C2410_IICDS);
330
331			/* delay after writing the byte to allow the
332			 * data setup time on the bus, as writing the
333			 * data to the register causes the first bit
334			 * to appear on SDA, and SCL will change as
335			 * soon as the interrupt is acknowledged */
336
337			ndelay(i2c->tx_setup);
338
339		} else if (!is_lastmsg(i2c)) {
340			/* we need to go to the next i2c message */
341
342			dev_dbg(i2c->dev, "WRITE: Next Message\n");
343
344			i2c->msg_ptr = 0;
345			i2c->msg_idx ++;
346			i2c->msg++;
347
348			/* check to see if we need to do another message */
349			if (i2c->msg->flags & I2C_M_NOSTART) {
350
351				if (i2c->msg->flags & I2C_M_RD) {
352					/* cannot do this, the controller
353					 * forces us to send a new START
354					 * when we change direction */
355
356					s3c24xx_i2c_stop(i2c, -EINVAL);
357				}
358
359				goto retry_write;
360			} else {
361
362				/* send the new start */
363				s3c24xx_i2c_message_start(i2c, i2c->msg);
364				i2c->state = STATE_START;
365			}
366
367		} else {
368			/* send stop */
369
370			s3c24xx_i2c_stop(i2c, 0);
371		}
372		break;
373
374	case STATE_READ:
375		/* we have a byte of data in the data register, do
376		 * something with it, and then work out wether we are
377		 * going to do any more read/write
378		 */
379
380		if (!(i2c->msg->flags & I2C_M_IGNORE_NAK) &&
381		    !(is_msglast(i2c) && is_lastmsg(i2c))) {
382
383			if (iicstat & S3C2410_IICSTAT_LASTBIT) {
384				dev_dbg(i2c->dev, "READ: No Ack\n");
385
386				s3c24xx_i2c_stop(i2c, -ECONNREFUSED);
387				goto out_ack;
388			}
389		}
390
391		byte = readb(i2c->regs + S3C2410_IICDS);
392		i2c->msg->buf[i2c->msg_ptr++] = byte;
393
394	prepare_read:
395		if (is_msglast(i2c)) {
396			/* last byte of buffer */
397
398			if (is_lastmsg(i2c))
399				s3c24xx_i2c_disable_ack(i2c);
400
401		} else if (is_msgend(i2c)) {
402			/* ok, we've read the entire buffer, see if there
403			 * is anything else we need to do */
404
405			if (is_lastmsg(i2c)) {
406				/* last message, send stop and complete */
407				dev_dbg(i2c->dev, "READ: Send Stop\n");
408
409				s3c24xx_i2c_stop(i2c, 0);
410			} else {
411				/* go to the next transfer */
412				dev_dbg(i2c->dev, "READ: Next Transfer\n");
413
414				i2c->msg_ptr = 0;
415				i2c->msg_idx++;
416				i2c->msg++;
417			}
418		}
419
420		break;
421	}
422
423	/* acknowlegde the IRQ and get back on with the work */
424
425 out_ack:
426	tmp = readl(i2c->regs + S3C2410_IICCON);
427	tmp &= ~S3C2410_IICCON_IRQPEND;
428	writel(tmp, i2c->regs + S3C2410_IICCON);
429 out:
430	return ret;
431}
432
433/* s3c24xx_i2c_irq
434 *
435 * top level IRQ servicing routine
436*/
437
438static irqreturn_t s3c24xx_i2c_irq(int irqno, void *dev_id)
439{
440	struct s3c24xx_i2c *i2c = dev_id;
441	unsigned long status;
442	unsigned long tmp;
443
444	status = readl(i2c->regs + S3C2410_IICSTAT);
445
446	if (status & S3C2410_IICSTAT_ARBITR) {
447		// deal with arbitration loss
448		dev_err(i2c->dev, "deal with arbitration loss\n");
449	}
450
451	if (i2c->state == STATE_IDLE) {
452		dev_dbg(i2c->dev, "IRQ: error i2c->state == IDLE\n");
453
454		tmp = readl(i2c->regs + S3C2410_IICCON);
455		tmp &= ~S3C2410_IICCON_IRQPEND;
456		writel(tmp, i2c->regs +  S3C2410_IICCON);
457		goto out;
458	}
459
460	/* pretty much this leaves us with the fact that we've
461	 * transmitted or received whatever byte we last sent */
462
463	i2s_s3c_irq_nextbyte(i2c, status);
464
465 out:
466	return IRQ_HANDLED;
467}
468
469
470/* s3c24xx_i2c_set_master
471 *
472 * get the i2c bus for a master transaction
473*/
474
475static int s3c24xx_i2c_set_master(struct s3c24xx_i2c *i2c)
476{
477	unsigned long iicstat;
478	int timeout = 400;
479
480	while (timeout-- > 0) {
481		iicstat = readl(i2c->regs + S3C2410_IICSTAT);
482
483		if (!(iicstat & S3C2410_IICSTAT_BUSBUSY))
484			return 0;
485
486		msleep(1);
487	}
488
489	dev_dbg(i2c->dev, "timeout: GPEDAT is %08x\n",
490		__raw_readl(S3C2410_GPEDAT));
491
492	return -ETIMEDOUT;
493}
494
495/* s3c24xx_i2c_doxfer
496 *
497 * this starts an i2c transfer
498*/
499
500static int s3c24xx_i2c_doxfer(struct s3c24xx_i2c *i2c, struct i2c_msg *msgs, int num)
501{
502	unsigned long timeout;
503	int ret;
504
505	ret = s3c24xx_i2c_set_master(i2c);
506	if (ret != 0) {
507		dev_err(i2c->dev, "cannot get bus (error %d)\n", ret);
508		ret = -EAGAIN;
509		goto out;
510	}
511
512	spin_lock_irq(&i2c->lock);
513
514	i2c->msg     = msgs;
515	i2c->msg_num = num;
516	i2c->msg_ptr = 0;
517	i2c->msg_idx = 0;
518	i2c->state   = STATE_START;
519
520	s3c24xx_i2c_enable_irq(i2c);
521	s3c24xx_i2c_message_start(i2c, msgs);
522	spin_unlock_irq(&i2c->lock);
523
524	timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5);
525
526	ret = i2c->msg_idx;
527
528	/* having these next two as dev_err() makes life very
529	 * noisy when doing an i2cdetect */
530
531	if (timeout == 0)
532		dev_dbg(i2c->dev, "timeout\n");
533	else if (ret != num)
534		dev_dbg(i2c->dev, "incomplete xfer (%d)\n", ret);
535
536	/* ensure the stop has been through the bus */
537
538	msleep(1);
539
540 out:
541	return ret;
542}
543
544/* s3c24xx_i2c_xfer
545 *
546 * first port of call from the i2c bus code when an message needs
547 * transferring across the i2c bus.
548*/
549
550static int s3c24xx_i2c_xfer(struct i2c_adapter *adap,
551			struct i2c_msg *msgs, int num)
552{
553	struct s3c24xx_i2c *i2c = (struct s3c24xx_i2c *)adap->algo_data;
554	int retry;
555	int ret;
556
557	for (retry = 0; retry < adap->retries; retry++) {
558
559		ret = s3c24xx_i2c_doxfer(i2c, msgs, num);
560
561		if (ret != -EAGAIN)
562			return ret;
563
564		dev_dbg(i2c->dev, "Retrying transmission (%d)\n", retry);
565
566		udelay(100);
567	}
568
569	return -EREMOTEIO;
570}
571
572/* declare our i2c functionality */
573static u32 s3c24xx_i2c_func(struct i2c_adapter *adap)
574{
575	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_PROTOCOL_MANGLING;
576}
577
578/* i2c bus registration info */
579
580static const struct i2c_algorithm s3c24xx_i2c_algorithm = {
581	.master_xfer		= s3c24xx_i2c_xfer,
582	.functionality		= s3c24xx_i2c_func,
583};
584
585static struct s3c24xx_i2c s3c24xx_i2c = {
586	.lock		= __SPIN_LOCK_UNLOCKED(s3c24xx_i2c.lock),
587	.wait		= __WAIT_QUEUE_HEAD_INITIALIZER(s3c24xx_i2c.wait),
588	.tx_setup	= 50,
589	.adap		= {
590		.name			= "s3c2410-i2c",
591		.owner			= THIS_MODULE,
592		.algo			= &s3c24xx_i2c_algorithm,
593		.retries		= 2,
594		.class			= I2C_CLASS_HWMON,
595	},
596};
597
598/* s3c24xx_i2c_calcdivisor
599 *
600 * return the divisor settings for a given frequency
601*/
602
603static int s3c24xx_i2c_calcdivisor(unsigned long clkin, unsigned int wanted,
604				   unsigned int *div1, unsigned int *divs)
605{
606	unsigned int calc_divs = clkin / wanted;
607	unsigned int calc_div1;
608
609	if (calc_divs > (16*16))
610		calc_div1 = 512;
611	else
612		calc_div1 = 16;
613
614	calc_divs += calc_div1-1;
615	calc_divs /= calc_div1;
616
617	if (calc_divs == 0)
618		calc_divs = 1;
619	if (calc_divs > 17)
620		calc_divs = 17;
621
622	*divs = calc_divs;
623	*div1 = calc_div1;
624
625	return clkin / (calc_divs * calc_div1);
626}
627
628/* freq_acceptable
629 *
630 * test wether a frequency is within the acceptable range of error
631*/
632
633static inline int freq_acceptable(unsigned int freq, unsigned int wanted)
634{
635	int diff = freq - wanted;
636
637	return (diff >= -2 && diff <= 2);
638}
639
640/* s3c24xx_i2c_getdivisor
641 *
642 * work out a divisor for the user requested frequency setting,
643 * either by the requested frequency, or scanning the acceptable
644 * range of frequencies until something is found
645*/
646
647static int s3c24xx_i2c_getdivisor(struct s3c24xx_i2c *i2c,
648				  struct s3c2410_platform_i2c *pdata,
649				  unsigned long *iicon,
650				  unsigned int *got)
651{
652	unsigned long clkin = clk_get_rate(i2c->clk);
653
654	unsigned int divs, div1;
655	int freq;
656	int start, end;
657
658	clkin /= 1000;		/* clkin now in KHz */
659
660	dev_dbg(i2c->dev,  "pdata %p, freq %lu %lu..%lu\n",
661		 pdata, pdata->bus_freq, pdata->min_freq, pdata->max_freq);
662
663	if (pdata->bus_freq != 0) {
664		freq = s3c24xx_i2c_calcdivisor(clkin, pdata->bus_freq/1000,
665					       &div1, &divs);
666		if (freq_acceptable(freq, pdata->bus_freq/1000))
667			goto found;
668	}
669
670	/* ok, we may have to search for something suitable... */
671
672	start = (pdata->max_freq == 0) ? pdata->bus_freq : pdata->max_freq;
673	end = pdata->min_freq;
674
675	start /= 1000;
676	end /= 1000;
677
678	/* search loop... */
679
680	for (; start > end; start--) {
681		freq = s3c24xx_i2c_calcdivisor(clkin, start, &div1, &divs);
682		if (freq_acceptable(freq, start))
683			goto found;
684	}
685
686	/* cannot find frequency spec */
687
688	return -EINVAL;
689
690 found:
691	*got = freq;
692	*iicon |= (divs-1);
693	*iicon |= (div1 == 512) ? S3C2410_IICCON_TXDIV_512 : 0;
694	return 0;
695}
696
697/* s3c24xx_i2c_init
698 *
699 * initialise the controller, set the IO lines and frequency
700*/
701
702static int s3c24xx_i2c_init(struct s3c24xx_i2c *i2c)
703{
704	unsigned long iicon = S3C2410_IICCON_IRQEN | S3C2410_IICCON_ACKEN;
705	struct s3c2410_platform_i2c *pdata;
706	unsigned int freq;
707
708	/* get the plafrom data */
709
710	pdata = s3c24xx_i2c_get_platformdata(i2c->adap.dev.parent);
711
712	/* inititalise the gpio */
713
714	s3c2410_gpio_cfgpin(S3C2410_GPE15, S3C2410_GPE15_IICSDA);
715	s3c2410_gpio_cfgpin(S3C2410_GPE14, S3C2410_GPE14_IICSCL);
716
717	/* write slave address */
718
719	writeb(pdata->slave_addr, i2c->regs + S3C2410_IICADD);
720
721	dev_info(i2c->dev, "slave address 0x%02x\n", pdata->slave_addr);
722
723	/* we need to work out the divisors for the clock... */
724
725	if (s3c24xx_i2c_getdivisor(i2c, pdata, &iicon, &freq) != 0) {
726		dev_err(i2c->dev, "cannot meet bus frequency required\n");
727		return -EINVAL;
728	}
729
730	/* todo - check that the i2c lines aren't being dragged anywhere */
731
732	dev_info(i2c->dev, "bus frequency set to %d KHz\n", freq);
733	dev_dbg(i2c->dev, "S3C2410_IICCON=0x%02lx\n", iicon);
734
735	writel(iicon, i2c->regs + S3C2410_IICCON);
736
737	/* check for s3c2440 i2c controller  */
738
739	if (s3c24xx_i2c_is2440(i2c)) {
740		dev_dbg(i2c->dev, "S3C2440_IICLC=%08x\n", pdata->sda_delay);
741
742		writel(pdata->sda_delay, i2c->regs + S3C2440_IICLC);
743	}
744
745	return 0;
746}
747
748/* s3c24xx_i2c_probe
749 *
750 * called by the bus driver when a suitable device is found
751*/
752
753static int s3c24xx_i2c_probe(struct platform_device *pdev)
754{
755	struct s3c24xx_i2c *i2c = &s3c24xx_i2c;
756	struct resource *res;
757	int ret;
758
759	/* find the clock and enable it */
760
761	i2c->dev = &pdev->dev;
762	i2c->clk = clk_get(&pdev->dev, "i2c");
763	if (IS_ERR(i2c->clk)) {
764		dev_err(&pdev->dev, "cannot get clock\n");
765		ret = -ENOENT;
766		goto err_noclk;
767	}
768
769	dev_dbg(&pdev->dev, "clock source %p\n", i2c->clk);
770
771	clk_enable(i2c->clk);
772
773	/* map the registers */
774
775	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
776	if (res == NULL) {
777		dev_err(&pdev->dev, "cannot find IO resource\n");
778		ret = -ENOENT;
779		goto err_clk;
780	}
781
782	i2c->ioarea = request_mem_region(res->start, (res->end-res->start)+1,
783					 pdev->name);
784
785	if (i2c->ioarea == NULL) {
786		dev_err(&pdev->dev, "cannot request IO\n");
787		ret = -ENXIO;
788		goto err_clk;
789	}
790
791	i2c->regs = ioremap(res->start, (res->end-res->start)+1);
792
793	if (i2c->regs == NULL) {
794		dev_err(&pdev->dev, "cannot map IO\n");
795		ret = -ENXIO;
796		goto err_ioarea;
797	}
798
799	dev_dbg(&pdev->dev, "registers %p (%p, %p)\n", i2c->regs, i2c->ioarea, res);
800
801	/* setup info block for the i2c core */
802
803	i2c->adap.algo_data = i2c;
804	i2c->adap.dev.parent = &pdev->dev;
805
806	/* initialise the i2c controller */
807
808	ret = s3c24xx_i2c_init(i2c);
809	if (ret != 0)
810		goto err_iomap;
811
812	/* find the IRQ for this unit (note, this relies on the init call to
813	 * ensure no current IRQs pending
814	 */
815
816	res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
817	if (res == NULL) {
818		dev_err(&pdev->dev, "cannot find IRQ\n");
819		ret = -ENOENT;
820		goto err_iomap;
821	}
822
823	ret = request_irq(res->start, s3c24xx_i2c_irq, IRQF_DISABLED,
824			  pdev->name, i2c);
825
826	if (ret != 0) {
827		dev_err(&pdev->dev, "cannot claim IRQ\n");
828		goto err_iomap;
829	}
830
831	i2c->irq = res;
832
833	dev_dbg(&pdev->dev, "irq resource %p (%lu)\n", res,
834		(unsigned long)res->start);
835
836	ret = i2c_add_adapter(&i2c->adap);
837	if (ret < 0) {
838		dev_err(&pdev->dev, "failed to add bus to i2c core\n");
839		goto err_irq;
840	}
841
842	platform_set_drvdata(pdev, i2c);
843
844	dev_info(&pdev->dev, "%s: S3C I2C adapter\n", i2c->adap.dev.bus_id);
845	return 0;
846
847 err_irq:
848	free_irq(i2c->irq->start, i2c);
849
850 err_iomap:
851	iounmap(i2c->regs);
852
853 err_ioarea:
854	release_resource(i2c->ioarea);
855	kfree(i2c->ioarea);
856
857 err_clk:
858	clk_disable(i2c->clk);
859	clk_put(i2c->clk);
860
861 err_noclk:
862	return ret;
863}
864
865/* s3c24xx_i2c_remove
866 *
867 * called when device is removed from the bus
868*/
869
870static int s3c24xx_i2c_remove(struct platform_device *pdev)
871{
872	struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev);
873
874	i2c_del_adapter(&i2c->adap);
875	free_irq(i2c->irq->start, i2c);
876
877	clk_disable(i2c->clk);
878	clk_put(i2c->clk);
879
880	iounmap(i2c->regs);
881
882	release_resource(i2c->ioarea);
883	kfree(i2c->ioarea);
884
885	return 0;
886}
887
888#ifdef CONFIG_PM
889static int s3c24xx_i2c_resume(struct platform_device *dev)
890{
891	struct s3c24xx_i2c *i2c = platform_get_drvdata(dev);
892
893	if (i2c != NULL)
894		s3c24xx_i2c_init(i2c);
895
896	return 0;
897}
898
899#else
900#define s3c24xx_i2c_resume NULL
901#endif
902
903/* device driver for platform bus bits */
904
905static struct platform_driver s3c2410_i2c_driver = {
906	.probe		= s3c24xx_i2c_probe,
907	.remove		= s3c24xx_i2c_remove,
908	.resume		= s3c24xx_i2c_resume,
909	.driver		= {
910		.owner	= THIS_MODULE,
911		.name	= "s3c2410-i2c",
912	},
913};
914
915static struct platform_driver s3c2440_i2c_driver = {
916	.probe		= s3c24xx_i2c_probe,
917	.remove		= s3c24xx_i2c_remove,
918	.resume		= s3c24xx_i2c_resume,
919	.driver		= {
920		.owner	= THIS_MODULE,
921		.name	= "s3c2440-i2c",
922	},
923};
924
925static int __init i2c_adap_s3c_init(void)
926{
927	int ret;
928
929	ret = platform_driver_register(&s3c2410_i2c_driver);
930	if (ret == 0) {
931		ret = platform_driver_register(&s3c2440_i2c_driver);
932		if (ret)
933			platform_driver_unregister(&s3c2410_i2c_driver);
934	}
935
936	return ret;
937}
938
939static void __exit i2c_adap_s3c_exit(void)
940{
941	platform_driver_unregister(&s3c2410_i2c_driver);
942	platform_driver_unregister(&s3c2440_i2c_driver);
943}
944
945module_init(i2c_adap_s3c_init);
946module_exit(i2c_adap_s3c_exit);
947
948MODULE_DESCRIPTION("S3C24XX I2C Bus driver");
949MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
950MODULE_LICENSE("GPL");
951