1/** 2 * \file drm.h 3 * Header for the Direct Rendering Manager 4 * 5 * \author Rickard E. (Rik) Faith <faith@valinux.com> 6 * 7 * \par Acknowledgments: 8 * Dec 1999, Richard Henderson <rth@twiddle.net>, move to generic \c cmpxchg. 9 */ 10 11/* 12 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. 13 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 14 * All rights reserved. 15 * 16 * Permission is hereby granted, free of charge, to any person obtaining a 17 * copy of this software and associated documentation files (the "Software"), 18 * to deal in the Software without restriction, including without limitation 19 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 20 * and/or sell copies of the Software, and to permit persons to whom the 21 * Software is furnished to do so, subject to the following conditions: 22 * 23 * The above copyright notice and this permission notice (including the next 24 * paragraph) shall be included in all copies or substantial portions of the 25 * Software. 26 * 27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 28 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 29 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 30 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 31 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 32 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 33 * OTHER DEALINGS IN THE SOFTWARE. 34 */ 35 36#ifndef _DRM_H_ 37#define _DRM_H_ 38 39#if defined(__linux__) 40#if defined(__KERNEL__) 41#endif 42#include <asm/ioctl.h> /* For _IO* macros */ 43#define DRM_IOCTL_NR(n) _IOC_NR(n) 44#define DRM_IOC_VOID _IOC_NONE 45#define DRM_IOC_READ _IOC_READ 46#define DRM_IOC_WRITE _IOC_WRITE 47#define DRM_IOC_READWRITE _IOC_READ|_IOC_WRITE 48#define DRM_IOC(dir, group, nr, size) _IOC(dir, group, nr, size) 49#elif defined(__FreeBSD__) || defined(__NetBSD__) || defined(__OpenBSD__) 50#if defined(__FreeBSD__) && defined(IN_MODULE) 51/* Prevent name collision when including sys/ioccom.h */ 52#undef ioctl 53#include <sys/ioccom.h> 54#define ioctl(a,b,c) xf86ioctl(a,b,c) 55#else 56#include <sys/ioccom.h> 57#endif /* __FreeBSD__ && xf86ioctl */ 58#define DRM_IOCTL_NR(n) ((n) & 0xff) 59#define DRM_IOC_VOID IOC_VOID 60#define DRM_IOC_READ IOC_OUT 61#define DRM_IOC_WRITE IOC_IN 62#define DRM_IOC_READWRITE IOC_INOUT 63#define DRM_IOC(dir, group, nr, size) _IOC(dir, group, nr, size) 64#endif 65 66#define XFREE86_VERSION(major,minor,patch,snap) \ 67 ((major << 16) | (minor << 8) | patch) 68 69#ifndef CONFIG_XFREE86_VERSION 70#define CONFIG_XFREE86_VERSION XFREE86_VERSION(4,1,0,0) 71#endif 72 73#if CONFIG_XFREE86_VERSION < XFREE86_VERSION(4,1,0,0) 74#define DRM_PROC_DEVICES "/proc/devices" 75#define DRM_PROC_MISC "/proc/misc" 76#define DRM_PROC_DRM "/proc/drm" 77#define DRM_DEV_DRM "/dev/drm" 78#define DRM_DEV_MODE (S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP) 79#define DRM_DEV_UID 0 80#define DRM_DEV_GID 0 81#endif 82 83#if CONFIG_XFREE86_VERSION >= XFREE86_VERSION(4,1,0,0) 84#define DRM_MAJOR 226 85#define DRM_MAX_MINOR 15 86#endif 87#define DRM_NAME "drm" /**< Name in kernel, /dev, and /proc */ 88#define DRM_MIN_ORDER 5 /**< At least 2^5 bytes = 32 bytes */ 89#define DRM_MAX_ORDER 22 /**< Up to 2^22 bytes = 4MB */ 90#define DRM_RAM_PERCENT 10 /**< How much system ram can we lock? */ 91 92#define _DRM_LOCK_HELD 0x80000000U /**< Hardware lock is held */ 93#define _DRM_LOCK_CONT 0x40000000U /**< Hardware lock is contended */ 94#define _DRM_LOCK_IS_HELD(lock) ((lock) & _DRM_LOCK_HELD) 95#define _DRM_LOCK_IS_CONT(lock) ((lock) & _DRM_LOCK_CONT) 96#define _DRM_LOCKING_CONTEXT(lock) ((lock) & ~(_DRM_LOCK_HELD|_DRM_LOCK_CONT)) 97 98typedef unsigned int drm_handle_t; 99typedef unsigned int drm_context_t; 100typedef unsigned int drm_drawable_t; 101typedef unsigned int drm_magic_t; 102 103/** 104 * Cliprect. 105 * 106 * \warning: If you change this structure, make sure you change 107 * XF86DRIClipRectRec in the server as well 108 * 109 * \note KW: Actually it's illegal to change either for 110 * backwards-compatibility reasons. 111 */ 112typedef struct drm_clip_rect { 113 unsigned short x1; 114 unsigned short y1; 115 unsigned short x2; 116 unsigned short y2; 117} drm_clip_rect_t; 118 119/** 120 * Drawable information. 121 */ 122typedef struct drm_drawable_info { 123 unsigned int num_rects; 124 drm_clip_rect_t *rects; 125} drm_drawable_info_t; 126 127/** 128 * Texture region, 129 */ 130typedef struct drm_tex_region { 131 unsigned char next; 132 unsigned char prev; 133 unsigned char in_use; 134 unsigned char padding; 135 unsigned int age; 136} drm_tex_region_t; 137 138/** 139 * Hardware lock. 140 * 141 * The lock structure is a simple cache-line aligned integer. To avoid 142 * processor bus contention on a multiprocessor system, there should not be any 143 * other data stored in the same cache line. 144 */ 145typedef struct drm_hw_lock { 146 __volatile__ unsigned int lock; /**< lock variable */ 147 char padding[60]; /**< Pad to cache line */ 148} drm_hw_lock_t; 149 150/** 151 * DRM_IOCTL_VERSION ioctl argument type. 152 * 153 * \sa drmGetVersion(). 154 */ 155typedef struct drm_version { 156 int version_major; /**< Major version */ 157 int version_minor; /**< Minor version */ 158 int version_patchlevel; /**< Patch level */ 159 size_t name_len; /**< Length of name buffer */ 160 char __user *name; /**< Name of driver */ 161 size_t date_len; /**< Length of date buffer */ 162 char __user *date; /**< User-space buffer to hold date */ 163 size_t desc_len; /**< Length of desc buffer */ 164 char __user *desc; /**< User-space buffer to hold desc */ 165} drm_version_t; 166 167/** 168 * DRM_IOCTL_GET_UNIQUE ioctl argument type. 169 * 170 * \sa drmGetBusid() and drmSetBusId(). 171 */ 172typedef struct drm_unique { 173 size_t unique_len; /**< Length of unique */ 174 char __user *unique; /**< Unique name for driver instantiation */ 175} drm_unique_t; 176 177typedef struct drm_list { 178 int count; /**< Length of user-space structures */ 179 drm_version_t __user *version; 180} drm_list_t; 181 182typedef struct drm_block { 183 int unused; 184} drm_block_t; 185 186/** 187 * DRM_IOCTL_CONTROL ioctl argument type. 188 * 189 * \sa drmCtlInstHandler() and drmCtlUninstHandler(). 190 */ 191typedef struct drm_control { 192 enum { 193 DRM_ADD_COMMAND, 194 DRM_RM_COMMAND, 195 DRM_INST_HANDLER, 196 DRM_UNINST_HANDLER 197 } func; 198 int irq; 199} drm_control_t; 200 201/** 202 * Type of memory to map. 203 */ 204typedef enum drm_map_type { 205 _DRM_FRAME_BUFFER = 0, /**< WC (no caching), no core dump */ 206 _DRM_REGISTERS = 1, /**< no caching, no core dump */ 207 _DRM_SHM = 2, /**< shared, cached */ 208 _DRM_AGP = 3, /**< AGP/GART */ 209 _DRM_SCATTER_GATHER = 4, /**< Scatter/gather memory for PCI DMA */ 210 _DRM_CONSISTENT = 5, /**< Consistent memory for PCI DMA */ 211} drm_map_type_t; 212 213/** 214 * Memory mapping flags. 215 */ 216typedef enum drm_map_flags { 217 _DRM_RESTRICTED = 0x01, /**< Cannot be mapped to user-virtual */ 218 _DRM_READ_ONLY = 0x02, 219 _DRM_LOCKED = 0x04, /**< shared, cached, locked */ 220 _DRM_KERNEL = 0x08, /**< kernel requires access */ 221 _DRM_WRITE_COMBINING = 0x10, /**< use write-combining if available */ 222 _DRM_CONTAINS_LOCK = 0x20, /**< SHM page that contains lock */ 223 _DRM_REMOVABLE = 0x40 /**< Removable mapping */ 224} drm_map_flags_t; 225 226typedef struct drm_ctx_priv_map { 227 unsigned int ctx_id; /**< Context requesting private mapping */ 228 void *handle; /**< Handle of map */ 229} drm_ctx_priv_map_t; 230 231/** 232 * DRM_IOCTL_GET_MAP, DRM_IOCTL_ADD_MAP and DRM_IOCTL_RM_MAP ioctls 233 * argument type. 234 * 235 * \sa drmAddMap(). 236 */ 237typedef struct drm_map { 238 unsigned long offset; /**< Requested physical address (0 for SAREA)*/ 239 unsigned long size; /**< Requested physical size (bytes) */ 240 drm_map_type_t type; /**< Type of memory to map */ 241 drm_map_flags_t flags; /**< Flags */ 242 void *handle; /**< User-space: "Handle" to pass to mmap() */ 243 /**< Kernel-space: kernel-virtual address */ 244 int mtrr; /**< MTRR slot used */ 245 /* Private data */ 246} drm_map_t; 247 248/** 249 * DRM_IOCTL_GET_CLIENT ioctl argument type. 250 */ 251typedef struct drm_client { 252 int idx; /**< Which client desired? */ 253 int auth; /**< Is client authenticated? */ 254 unsigned long pid; /**< Process ID */ 255 unsigned long uid; /**< User ID */ 256 unsigned long magic; /**< Magic */ 257 unsigned long iocs; /**< Ioctl count */ 258} drm_client_t; 259 260typedef enum { 261 _DRM_STAT_LOCK, 262 _DRM_STAT_OPENS, 263 _DRM_STAT_CLOSES, 264 _DRM_STAT_IOCTLS, 265 _DRM_STAT_LOCKS, 266 _DRM_STAT_UNLOCKS, 267 _DRM_STAT_VALUE, /**< Generic value */ 268 _DRM_STAT_BYTE, /**< Generic byte counter (1024bytes/K) */ 269 _DRM_STAT_COUNT, /**< Generic non-byte counter (1000/k) */ 270 271 _DRM_STAT_IRQ, /**< IRQ */ 272 _DRM_STAT_PRIMARY, /**< Primary DMA bytes */ 273 _DRM_STAT_SECONDARY, /**< Secondary DMA bytes */ 274 _DRM_STAT_DMA, /**< DMA */ 275 _DRM_STAT_SPECIAL, /**< Special DMA (e.g., priority or polled) */ 276 _DRM_STAT_MISSED /**< Missed DMA opportunity */ 277 /* Add to the *END* of the list */ 278} drm_stat_type_t; 279 280/** 281 * DRM_IOCTL_GET_STATS ioctl argument type. 282 */ 283typedef struct drm_stats { 284 unsigned long count; 285 struct { 286 unsigned long value; 287 drm_stat_type_t type; 288 } data[15]; 289} drm_stats_t; 290 291/** 292 * Hardware locking flags. 293 */ 294typedef enum drm_lock_flags { 295 _DRM_LOCK_READY = 0x01, /**< Wait until hardware is ready for DMA */ 296 _DRM_LOCK_QUIESCENT = 0x02, /**< Wait until hardware quiescent */ 297 _DRM_LOCK_FLUSH = 0x04, /**< Flush this context's DMA queue first */ 298 _DRM_LOCK_FLUSH_ALL = 0x08, /**< Flush all DMA queues first */ 299 /* These *HALT* flags aren't supported yet 300 -- they will be used to support the 301 full-screen DGA-like mode. */ 302 _DRM_HALT_ALL_QUEUES = 0x10, /**< Halt all current and future queues */ 303 _DRM_HALT_CUR_QUEUES = 0x20 /**< Halt all current queues */ 304} drm_lock_flags_t; 305 306/** 307 * DRM_IOCTL_LOCK, DRM_IOCTL_UNLOCK and DRM_IOCTL_FINISH ioctl argument type. 308 * 309 * \sa drmGetLock() and drmUnlock(). 310 */ 311typedef struct drm_lock { 312 int context; 313 drm_lock_flags_t flags; 314} drm_lock_t; 315 316/** 317 * DMA flags 318 * 319 * \warning 320 * These values \e must match xf86drm.h. 321 * 322 * \sa drm_dma. 323 */ 324typedef enum drm_dma_flags { 325 /* Flags for DMA buffer dispatch */ 326 _DRM_DMA_BLOCK = 0x01, /**< 327 * Block until buffer dispatched. 328 * 329 * \note The buffer may not yet have 330 * been processed by the hardware -- 331 * getting a hardware lock with the 332 * hardware quiescent will ensure 333 * that the buffer has been 334 * processed. 335 */ 336 _DRM_DMA_WHILE_LOCKED = 0x02, /**< Dispatch while lock held */ 337 _DRM_DMA_PRIORITY = 0x04, /**< High priority dispatch */ 338 339 /* Flags for DMA buffer request */ 340 _DRM_DMA_WAIT = 0x10, /**< Wait for free buffers */ 341 _DRM_DMA_SMALLER_OK = 0x20, /**< Smaller-than-requested buffers OK */ 342 _DRM_DMA_LARGER_OK = 0x40 /**< Larger-than-requested buffers OK */ 343} drm_dma_flags_t; 344 345/** 346 * DRM_IOCTL_ADD_BUFS and DRM_IOCTL_MARK_BUFS ioctl argument type. 347 * 348 * \sa drmAddBufs(). 349 */ 350typedef struct drm_buf_desc { 351 int count; /**< Number of buffers of this size */ 352 int size; /**< Size in bytes */ 353 int low_mark; /**< Low water mark */ 354 int high_mark; /**< High water mark */ 355 enum { 356 _DRM_PAGE_ALIGN = 0x01, /**< Align on page boundaries for DMA */ 357 _DRM_AGP_BUFFER = 0x02, /**< Buffer is in AGP space */ 358 _DRM_SG_BUFFER = 0x04, /**< Scatter/gather memory buffer */ 359 _DRM_FB_BUFFER = 0x08, /**< Buffer is in frame buffer */ 360 _DRM_PCI_BUFFER_RO = 0x10 /**< Map PCI DMA buffer read-only */ 361 } flags; 362 unsigned long agp_start; /**< 363 * Start address of where the AGP buffers are 364 * in the AGP aperture 365 */ 366} drm_buf_desc_t; 367 368/** 369 * DRM_IOCTL_INFO_BUFS ioctl argument type. 370 */ 371typedef struct drm_buf_info { 372 int count; /**< Entries in list */ 373 drm_buf_desc_t __user *list; 374} drm_buf_info_t; 375 376/** 377 * DRM_IOCTL_FREE_BUFS ioctl argument type. 378 */ 379typedef struct drm_buf_free { 380 int count; 381 int __user *list; 382} drm_buf_free_t; 383 384/** 385 * Buffer information 386 * 387 * \sa drm_buf_map. 388 */ 389typedef struct drm_buf_pub { 390 int idx; /**< Index into the master buffer list */ 391 int total; /**< Buffer size */ 392 int used; /**< Amount of buffer in use (for DMA) */ 393 void __user *address; /**< Address of buffer */ 394} drm_buf_pub_t; 395 396/** 397 * DRM_IOCTL_MAP_BUFS ioctl argument type. 398 */ 399typedef struct drm_buf_map { 400 int count; /**< Length of the buffer list */ 401 void __user *virtual; /**< Mmap'd area in user-virtual */ 402 drm_buf_pub_t __user *list; /**< Buffer information */ 403} drm_buf_map_t; 404 405/** 406 * DRM_IOCTL_DMA ioctl argument type. 407 * 408 * Indices here refer to the offset into the buffer list in drm_buf_get. 409 * 410 * \sa drmDMA(). 411 */ 412typedef struct drm_dma { 413 int context; /**< Context handle */ 414 int send_count; /**< Number of buffers to send */ 415 int __user *send_indices; /**< List of handles to buffers */ 416 int __user *send_sizes; /**< Lengths of data to send */ 417 drm_dma_flags_t flags; /**< Flags */ 418 int request_count; /**< Number of buffers requested */ 419 int request_size; /**< Desired size for buffers */ 420 int __user *request_indices; /**< Buffer information */ 421 int __user *request_sizes; 422 int granted_count; /**< Number of buffers granted */ 423} drm_dma_t; 424 425typedef enum { 426 _DRM_CONTEXT_PRESERVED = 0x01, 427 _DRM_CONTEXT_2DONLY = 0x02 428} drm_ctx_flags_t; 429 430/** 431 * DRM_IOCTL_ADD_CTX ioctl argument type. 432 * 433 * \sa drmCreateContext() and drmDestroyContext(). 434 */ 435typedef struct drm_ctx { 436 drm_context_t handle; 437 drm_ctx_flags_t flags; 438} drm_ctx_t; 439 440/** 441 * DRM_IOCTL_RES_CTX ioctl argument type. 442 */ 443typedef struct drm_ctx_res { 444 int count; 445 drm_ctx_t __user *contexts; 446} drm_ctx_res_t; 447 448/** 449 * DRM_IOCTL_ADD_DRAW and DRM_IOCTL_RM_DRAW ioctl argument type. 450 */ 451typedef struct drm_draw { 452 drm_drawable_t handle; 453} drm_draw_t; 454 455/** 456 * DRM_IOCTL_UPDATE_DRAW ioctl argument type. 457 */ 458typedef enum { 459 DRM_DRAWABLE_CLIPRECTS, 460} drm_drawable_info_type_t; 461 462typedef struct drm_update_draw { 463 drm_drawable_t handle; 464 unsigned int type; 465 unsigned int num; 466 unsigned long long data; 467} drm_update_draw_t; 468 469/** 470 * DRM_IOCTL_GET_MAGIC and DRM_IOCTL_AUTH_MAGIC ioctl argument type. 471 */ 472typedef struct drm_auth { 473 drm_magic_t magic; 474} drm_auth_t; 475 476/** 477 * DRM_IOCTL_IRQ_BUSID ioctl argument type. 478 * 479 * \sa drmGetInterruptFromBusID(). 480 */ 481typedef struct drm_irq_busid { 482 int irq; /**< IRQ number */ 483 int busnum; /**< bus number */ 484 int devnum; /**< device number */ 485 int funcnum; /**< function number */ 486} drm_irq_busid_t; 487 488typedef enum { 489 _DRM_VBLANK_ABSOLUTE = 0x0, /**< Wait for specific vblank sequence number */ 490 _DRM_VBLANK_RELATIVE = 0x1, /**< Wait for given number of vblanks */ 491 _DRM_VBLANK_NEXTONMISS = 0x10000000, /**< If missed, wait for next vblank */ 492 _DRM_VBLANK_SECONDARY = 0x20000000, /**< Secondary display controller */ 493 _DRM_VBLANK_SIGNAL = 0x40000000 /**< Send signal instead of blocking */ 494} drm_vblank_seq_type_t; 495 496#define _DRM_VBLANK_TYPES_MASK (_DRM_VBLANK_ABSOLUTE | _DRM_VBLANK_RELATIVE) 497#define _DRM_VBLANK_FLAGS_MASK (_DRM_VBLANK_SIGNAL | _DRM_VBLANK_SECONDARY | \ 498 _DRM_VBLANK_NEXTONMISS) 499 500struct drm_wait_vblank_request { 501 drm_vblank_seq_type_t type; 502 unsigned int sequence; 503 unsigned long signal; 504}; 505 506struct drm_wait_vblank_reply { 507 drm_vblank_seq_type_t type; 508 unsigned int sequence; 509 long tval_sec; 510 long tval_usec; 511}; 512 513/** 514 * DRM_IOCTL_WAIT_VBLANK ioctl argument type. 515 * 516 * \sa drmWaitVBlank(). 517 */ 518typedef union drm_wait_vblank { 519 struct drm_wait_vblank_request request; 520 struct drm_wait_vblank_reply reply; 521} drm_wait_vblank_t; 522 523/** 524 * DRM_IOCTL_AGP_ENABLE ioctl argument type. 525 * 526 * \sa drmAgpEnable(). 527 */ 528typedef struct drm_agp_mode { 529 unsigned long mode; /**< AGP mode */ 530} drm_agp_mode_t; 531 532/** 533 * DRM_IOCTL_AGP_ALLOC and DRM_IOCTL_AGP_FREE ioctls argument type. 534 * 535 * \sa drmAgpAlloc() and drmAgpFree(). 536 */ 537typedef struct drm_agp_buffer { 538 unsigned long size; /**< In bytes -- will round to page boundary */ 539 unsigned long handle; /**< Used for binding / unbinding */ 540 unsigned long type; /**< Type of memory to allocate */ 541 unsigned long physical; /**< Physical used by i810 */ 542} drm_agp_buffer_t; 543 544/** 545 * DRM_IOCTL_AGP_BIND and DRM_IOCTL_AGP_UNBIND ioctls argument type. 546 * 547 * \sa drmAgpBind() and drmAgpUnbind(). 548 */ 549typedef struct drm_agp_binding { 550 unsigned long handle; /**< From drm_agp_buffer */ 551 unsigned long offset; /**< In bytes -- will round to page boundary */ 552} drm_agp_binding_t; 553 554/** 555 * DRM_IOCTL_AGP_INFO ioctl argument type. 556 * 557 * \sa drmAgpVersionMajor(), drmAgpVersionMinor(), drmAgpGetMode(), 558 * drmAgpBase(), drmAgpSize(), drmAgpMemoryUsed(), drmAgpMemoryAvail(), 559 * drmAgpVendorId() and drmAgpDeviceId(). 560 */ 561typedef struct drm_agp_info { 562 int agp_version_major; 563 int agp_version_minor; 564 unsigned long mode; 565 unsigned long aperture_base; /* physical address */ 566 unsigned long aperture_size; /* bytes */ 567 unsigned long memory_allowed; /* bytes */ 568 unsigned long memory_used; 569 570 /* PCI information */ 571 unsigned short id_vendor; 572 unsigned short id_device; 573} drm_agp_info_t; 574 575/** 576 * DRM_IOCTL_SG_ALLOC ioctl argument type. 577 */ 578typedef struct drm_scatter_gather { 579 unsigned long size; /**< In bytes -- will round to page boundary */ 580 unsigned long handle; /**< Used for mapping / unmapping */ 581} drm_scatter_gather_t; 582 583/** 584 * DRM_IOCTL_SET_VERSION ioctl argument type. 585 */ 586typedef struct drm_set_version { 587 int drm_di_major; 588 int drm_di_minor; 589 int drm_dd_major; 590 int drm_dd_minor; 591} drm_set_version_t; 592 593#define DRM_IOCTL_BASE 'd' 594#define DRM_IO(nr) _IO(DRM_IOCTL_BASE,nr) 595#define DRM_IOR(nr,type) _IOR(DRM_IOCTL_BASE,nr,type) 596#define DRM_IOW(nr,type) _IOW(DRM_IOCTL_BASE,nr,type) 597#define DRM_IOWR(nr,type) _IOWR(DRM_IOCTL_BASE,nr,type) 598 599#define DRM_IOCTL_VERSION DRM_IOWR(0x00, drm_version_t) 600#define DRM_IOCTL_GET_UNIQUE DRM_IOWR(0x01, drm_unique_t) 601#define DRM_IOCTL_GET_MAGIC DRM_IOR( 0x02, drm_auth_t) 602#define DRM_IOCTL_IRQ_BUSID DRM_IOWR(0x03, drm_irq_busid_t) 603#define DRM_IOCTL_GET_MAP DRM_IOWR(0x04, drm_map_t) 604#define DRM_IOCTL_GET_CLIENT DRM_IOWR(0x05, drm_client_t) 605#define DRM_IOCTL_GET_STATS DRM_IOR( 0x06, drm_stats_t) 606#define DRM_IOCTL_SET_VERSION DRM_IOWR(0x07, drm_set_version_t) 607 608#define DRM_IOCTL_SET_UNIQUE DRM_IOW( 0x10, drm_unique_t) 609#define DRM_IOCTL_AUTH_MAGIC DRM_IOW( 0x11, drm_auth_t) 610#define DRM_IOCTL_BLOCK DRM_IOWR(0x12, drm_block_t) 611#define DRM_IOCTL_UNBLOCK DRM_IOWR(0x13, drm_block_t) 612#define DRM_IOCTL_CONTROL DRM_IOW( 0x14, drm_control_t) 613#define DRM_IOCTL_ADD_MAP DRM_IOWR(0x15, drm_map_t) 614#define DRM_IOCTL_ADD_BUFS DRM_IOWR(0x16, drm_buf_desc_t) 615#define DRM_IOCTL_MARK_BUFS DRM_IOW( 0x17, drm_buf_desc_t) 616#define DRM_IOCTL_INFO_BUFS DRM_IOWR(0x18, drm_buf_info_t) 617#define DRM_IOCTL_MAP_BUFS DRM_IOWR(0x19, drm_buf_map_t) 618#define DRM_IOCTL_FREE_BUFS DRM_IOW( 0x1a, drm_buf_free_t) 619 620#define DRM_IOCTL_RM_MAP DRM_IOW( 0x1b, drm_map_t) 621 622#define DRM_IOCTL_SET_SAREA_CTX DRM_IOW( 0x1c, drm_ctx_priv_map_t) 623#define DRM_IOCTL_GET_SAREA_CTX DRM_IOWR(0x1d, drm_ctx_priv_map_t) 624 625#define DRM_IOCTL_ADD_CTX DRM_IOWR(0x20, drm_ctx_t) 626#define DRM_IOCTL_RM_CTX DRM_IOWR(0x21, drm_ctx_t) 627#define DRM_IOCTL_MOD_CTX DRM_IOW( 0x22, drm_ctx_t) 628#define DRM_IOCTL_GET_CTX DRM_IOWR(0x23, drm_ctx_t) 629#define DRM_IOCTL_SWITCH_CTX DRM_IOW( 0x24, drm_ctx_t) 630#define DRM_IOCTL_NEW_CTX DRM_IOW( 0x25, drm_ctx_t) 631#define DRM_IOCTL_RES_CTX DRM_IOWR(0x26, drm_ctx_res_t) 632#define DRM_IOCTL_ADD_DRAW DRM_IOWR(0x27, drm_draw_t) 633#define DRM_IOCTL_RM_DRAW DRM_IOWR(0x28, drm_draw_t) 634#define DRM_IOCTL_DMA DRM_IOWR(0x29, drm_dma_t) 635#define DRM_IOCTL_LOCK DRM_IOW( 0x2a, drm_lock_t) 636#define DRM_IOCTL_UNLOCK DRM_IOW( 0x2b, drm_lock_t) 637#define DRM_IOCTL_FINISH DRM_IOW( 0x2c, drm_lock_t) 638 639#define DRM_IOCTL_AGP_ACQUIRE DRM_IO( 0x30) 640#define DRM_IOCTL_AGP_RELEASE DRM_IO( 0x31) 641#define DRM_IOCTL_AGP_ENABLE DRM_IOW( 0x32, drm_agp_mode_t) 642#define DRM_IOCTL_AGP_INFO DRM_IOR( 0x33, drm_agp_info_t) 643#define DRM_IOCTL_AGP_ALLOC DRM_IOWR(0x34, drm_agp_buffer_t) 644#define DRM_IOCTL_AGP_FREE DRM_IOW( 0x35, drm_agp_buffer_t) 645#define DRM_IOCTL_AGP_BIND DRM_IOW( 0x36, drm_agp_binding_t) 646#define DRM_IOCTL_AGP_UNBIND DRM_IOW( 0x37, drm_agp_binding_t) 647 648#define DRM_IOCTL_SG_ALLOC DRM_IOW( 0x38, drm_scatter_gather_t) 649#define DRM_IOCTL_SG_FREE DRM_IOW( 0x39, drm_scatter_gather_t) 650 651#define DRM_IOCTL_WAIT_VBLANK DRM_IOWR(0x3a, drm_wait_vblank_t) 652 653#define DRM_IOCTL_UPDATE_DRAW DRM_IOW(0x3f, drm_update_draw_t) 654 655/** 656 * Device specific ioctls should only be in their respective headers 657 * The device specific ioctl range is from 0x40 to 0x99. 658 * Generic IOCTLS restart at 0xA0. 659 * 660 * \sa drmCommandNone(), drmCommandRead(), drmCommandWrite(), and 661 * drmCommandReadWrite(). 662 */ 663#define DRM_COMMAND_BASE 0x40 664#define DRM_COMMAND_END 0xA0 665 666#endif 667