1/* 2 * Copyright 2001-2003 SuSE Labs. 3 * Distributed under the GNU public license, v2. 4 * 5 * This is a GART driver for the AMD Opteron/Athlon64 on-CPU northbridge. 6 * It also includes support for the AMD 8151 AGP bridge, 7 * although it doesn't actually do much, as all the real 8 * work is done in the northbridge(s). 9 */ 10 11#include <linux/module.h> 12#include <linux/pci.h> 13#include <linux/init.h> 14#include <linux/agp_backend.h> 15#include <linux/mmzone.h> 16#include <asm/page.h> /* PAGE_SIZE */ 17#include <asm/e820.h> 18#include <asm/k8.h> 19#include "agp.h" 20 21/* PTE bits. */ 22#define GPTE_VALID 1 23#define GPTE_COHERENT 2 24 25/* Aperture control register bits. */ 26#define GARTEN (1<<0) 27#define DISGARTCPU (1<<4) 28#define DISGARTIO (1<<5) 29 30/* GART cache control register bits. */ 31#define INVGART (1<<0) 32#define GARTPTEERR (1<<1) 33 34/* K8 On-cpu GART registers */ 35#define AMD64_GARTAPERTURECTL 0x90 36#define AMD64_GARTAPERTUREBASE 0x94 37#define AMD64_GARTTABLEBASE 0x98 38#define AMD64_GARTCACHECTL 0x9c 39#define AMD64_GARTEN (1<<0) 40 41/* NVIDIA K8 registers */ 42#define NVIDIA_X86_64_0_APBASE 0x10 43#define NVIDIA_X86_64_1_APBASE1 0x50 44#define NVIDIA_X86_64_1_APLIMIT1 0x54 45#define NVIDIA_X86_64_1_APSIZE 0xa8 46#define NVIDIA_X86_64_1_APBASE2 0xd8 47#define NVIDIA_X86_64_1_APLIMIT2 0xdc 48 49/* ULi K8 registers */ 50#define ULI_X86_64_BASE_ADDR 0x10 51#define ULI_X86_64_HTT_FEA_REG 0x50 52#define ULI_X86_64_ENU_SCR_REG 0x54 53 54static struct resource *aperture_resource; 55static int __initdata agp_try_unsupported = 1; 56 57static void amd64_tlbflush(struct agp_memory *temp) 58{ 59 k8_flush_garts(); 60} 61 62static int amd64_insert_memory(struct agp_memory *mem, off_t pg_start, int type) 63{ 64 int i, j, num_entries; 65 long long tmp; 66 int mask_type; 67 struct agp_bridge_data *bridge = mem->bridge; 68 u32 pte; 69 70 num_entries = agp_num_entries(); 71 72 if (type != mem->type) 73 return -EINVAL; 74 mask_type = bridge->driver->agp_type_to_mask_type(bridge, type); 75 if (mask_type != 0) 76 return -EINVAL; 77 78 79 /* Make sure we can fit the range in the gatt table. */ 80 if (((unsigned long)pg_start + mem->page_count) > num_entries) 81 return -EINVAL; 82 83 j = pg_start; 84 85 /* gatt table should be empty. */ 86 while (j < (pg_start + mem->page_count)) { 87 if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+j))) 88 return -EBUSY; 89 j++; 90 } 91 92 if (mem->is_flushed == FALSE) { 93 global_cache_flush(); 94 mem->is_flushed = TRUE; 95 } 96 97 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { 98 tmp = agp_bridge->driver->mask_memory(agp_bridge, 99 mem->memory[i], mask_type); 100 101 BUG_ON(tmp & 0xffffff0000000ffcULL); 102 pte = (tmp & 0x000000ff00000000ULL) >> 28; 103 pte |=(tmp & 0x00000000fffff000ULL); 104 pte |= GPTE_VALID | GPTE_COHERENT; 105 106 writel(pte, agp_bridge->gatt_table+j); 107 readl(agp_bridge->gatt_table+j); /* PCI Posting. */ 108 } 109 amd64_tlbflush(mem); 110 return 0; 111} 112 113/* 114 * This hack alters the order element according 115 * to the size of a long. It sucks. I totally disown this, even 116 * though it does appear to work for the most part. 117 */ 118static struct aper_size_info_32 amd64_aperture_sizes[7] = 119{ 120 {32, 8192, 3+(sizeof(long)/8), 0 }, 121 {64, 16384, 4+(sizeof(long)/8), 1<<1 }, 122 {128, 32768, 5+(sizeof(long)/8), 1<<2 }, 123 {256, 65536, 6+(sizeof(long)/8), 1<<1 | 1<<2 }, 124 {512, 131072, 7+(sizeof(long)/8), 1<<3 }, 125 {1024, 262144, 8+(sizeof(long)/8), 1<<1 | 1<<3}, 126 {2048, 524288, 9+(sizeof(long)/8), 1<<2 | 1<<3} 127}; 128 129 130/* 131 * Get the current Aperture size from the x86-64. 132 * Note, that there may be multiple x86-64's, but we just return 133 * the value from the first one we find. The set_size functions 134 * keep the rest coherent anyway. Or at least should do. 135 */ 136static int amd64_fetch_size(void) 137{ 138 struct pci_dev *dev; 139 int i; 140 u32 temp; 141 struct aper_size_info_32 *values; 142 143 dev = k8_northbridges[0]; 144 if (dev==NULL) 145 return 0; 146 147 pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &temp); 148 temp = (temp & 0xe); 149 values = A_SIZE_32(amd64_aperture_sizes); 150 151 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) { 152 if (temp == values[i].size_value) { 153 agp_bridge->previous_size = 154 agp_bridge->current_size = (void *) (values + i); 155 156 agp_bridge->aperture_size_idx = i; 157 return values[i].size; 158 } 159 } 160 return 0; 161} 162 163/* 164 * In a multiprocessor x86-64 system, this function gets 165 * called once for each CPU. 166 */ 167static u64 amd64_configure (struct pci_dev *hammer, u64 gatt_table) 168{ 169 u64 aperturebase; 170 u32 tmp; 171 u64 addr, aper_base; 172 173 /* Address to map to */ 174 pci_read_config_dword (hammer, AMD64_GARTAPERTUREBASE, &tmp); 175 aperturebase = tmp << 25; 176 aper_base = (aperturebase & PCI_BASE_ADDRESS_MEM_MASK); 177 178 /* address of the mappings table */ 179 addr = (u64) gatt_table; 180 addr >>= 12; 181 tmp = (u32) addr<<4; 182 tmp &= ~0xf; 183 pci_write_config_dword (hammer, AMD64_GARTTABLEBASE, tmp); 184 185 /* Enable GART translation for this hammer. */ 186 pci_read_config_dword(hammer, AMD64_GARTAPERTURECTL, &tmp); 187 tmp |= GARTEN; 188 tmp &= ~(DISGARTCPU | DISGARTIO); 189 pci_write_config_dword(hammer, AMD64_GARTAPERTURECTL, tmp); 190 191 return aper_base; 192} 193 194 195static const struct aper_size_info_32 amd_8151_sizes[7] = 196{ 197 {2048, 524288, 9, 0x00000000 }, /* 0 0 0 0 0 0 */ 198 {1024, 262144, 8, 0x00000400 }, /* 1 0 0 0 0 0 */ 199 {512, 131072, 7, 0x00000600 }, /* 1 1 0 0 0 0 */ 200 {256, 65536, 6, 0x00000700 }, /* 1 1 1 0 0 0 */ 201 {128, 32768, 5, 0x00000720 }, /* 1 1 1 1 0 0 */ 202 {64, 16384, 4, 0x00000730 }, /* 1 1 1 1 1 0 */ 203 {32, 8192, 3, 0x00000738 } /* 1 1 1 1 1 1 */ 204}; 205 206static int amd_8151_configure(void) 207{ 208 unsigned long gatt_bus = virt_to_gart(agp_bridge->gatt_table_real); 209 int i; 210 211 /* Configure AGP regs in each x86-64 host bridge. */ 212 for (i = 0; i < num_k8_northbridges; i++) { 213 agp_bridge->gart_bus_addr = 214 amd64_configure(k8_northbridges[i], gatt_bus); 215 } 216 k8_flush_garts(); 217 return 0; 218} 219 220 221static void amd64_cleanup(void) 222{ 223 u32 tmp; 224 int i; 225 for (i = 0; i < num_k8_northbridges; i++) { 226 struct pci_dev *dev = k8_northbridges[i]; 227 /* disable gart translation */ 228 pci_read_config_dword (dev, AMD64_GARTAPERTURECTL, &tmp); 229 tmp &= ~AMD64_GARTEN; 230 pci_write_config_dword (dev, AMD64_GARTAPERTURECTL, tmp); 231 } 232} 233 234 235static const struct agp_bridge_driver amd_8151_driver = { 236 .owner = THIS_MODULE, 237 .aperture_sizes = amd_8151_sizes, 238 .size_type = U32_APER_SIZE, 239 .num_aperture_sizes = 7, 240 .configure = amd_8151_configure, 241 .fetch_size = amd64_fetch_size, 242 .cleanup = amd64_cleanup, 243 .tlb_flush = amd64_tlbflush, 244 .mask_memory = agp_generic_mask_memory, 245 .masks = NULL, 246 .agp_enable = agp_generic_enable, 247 .cache_flush = global_cache_flush, 248 .create_gatt_table = agp_generic_create_gatt_table, 249 .free_gatt_table = agp_generic_free_gatt_table, 250 .insert_memory = amd64_insert_memory, 251 .remove_memory = agp_generic_remove_memory, 252 .alloc_by_type = agp_generic_alloc_by_type, 253 .free_by_type = agp_generic_free_by_type, 254 .agp_alloc_page = agp_generic_alloc_page, 255 .agp_destroy_page = agp_generic_destroy_page, 256 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 257}; 258 259/* Some basic sanity checks for the aperture. */ 260static int __devinit aperture_valid(u64 aper, u32 size) 261{ 262 if (aper == 0) { 263 printk(KERN_ERR PFX "No aperture\n"); 264 return 0; 265 } 266 if (size < 32*1024*1024) { 267 printk(KERN_ERR PFX "Aperture too small (%d MB)\n", size>>20); 268 return 0; 269 } 270 if ((u64)aper + size > 0x100000000ULL) { 271 printk(KERN_ERR PFX "Aperture out of bounds\n"); 272 return 0; 273 } 274 if (e820_any_mapped(aper, aper + size, E820_RAM)) { 275 printk(KERN_ERR PFX "Aperture pointing to RAM\n"); 276 return 0; 277 } 278 279 /* Request the Aperture. This catches cases when someone else 280 already put a mapping in there - happens with some very broken BIOS 281 282 Maybe better to use pci_assign_resource/pci_enable_device instead 283 trusting the bridges? */ 284 if (!aperture_resource && 285 !(aperture_resource = request_mem_region(aper, size, "aperture"))) { 286 printk(KERN_ERR PFX "Aperture conflicts with PCI mapping.\n"); 287 return 0; 288 } 289 return 1; 290} 291 292/* 293 * W*s centric BIOS sometimes only set up the aperture in the AGP 294 * bridge, not the northbridge. On AMD64 this is handled early 295 * in aperture.c, but when IOMMU is not enabled or we run 296 * on a 32bit kernel this needs to be redone. 297 * Unfortunately it is impossible to fix the aperture here because it's too late 298 * to allocate that much memory. But at least error out cleanly instead of 299 * crashing. 300 */ 301static __devinit int fix_northbridge(struct pci_dev *nb, struct pci_dev *agp, 302 u16 cap) 303{ 304 u32 aper_low, aper_hi; 305 u64 aper, nb_aper; 306 int order = 0; 307 u32 nb_order, nb_base; 308 u16 apsize; 309 310 pci_read_config_dword(nb, 0x90, &nb_order); 311 nb_order = (nb_order >> 1) & 7; 312 pci_read_config_dword(nb, 0x94, &nb_base); 313 nb_aper = nb_base << 25; 314 if (aperture_valid(nb_aper, (32*1024*1024)<<nb_order)) { 315 return 0; 316 } 317 318 /* Northbridge seems to contain crap. Try the AGP bridge. */ 319 320 pci_read_config_word(agp, cap+0x14, &apsize); 321 if (apsize == 0xffff) 322 return -1; 323 324 apsize &= 0xfff; 325 /* Some BIOS use weird encodings not in the AGPv3 table. */ 326 if (apsize & 0xff) 327 apsize |= 0xf00; 328 order = 7 - hweight16(apsize); 329 330 pci_read_config_dword(agp, 0x10, &aper_low); 331 pci_read_config_dword(agp, 0x14, &aper_hi); 332 aper = (aper_low & ~((1<<22)-1)) | ((u64)aper_hi << 32); 333 printk(KERN_INFO PFX "Aperture from AGP @ %Lx size %u MB\n", aper, 32 << order); 334 if (order < 0 || !aperture_valid(aper, (32*1024*1024)<<order)) 335 return -1; 336 337 pci_write_config_dword(nb, 0x90, order << 1); 338 pci_write_config_dword(nb, 0x94, aper >> 25); 339 340 return 0; 341} 342 343static __devinit int cache_nbs (struct pci_dev *pdev, u32 cap_ptr) 344{ 345 int i; 346 347 if (cache_k8_northbridges() < 0) 348 return -ENODEV; 349 350 i = 0; 351 for (i = 0; i < num_k8_northbridges; i++) { 352 struct pci_dev *dev = k8_northbridges[i]; 353 if (fix_northbridge(dev, pdev, cap_ptr) < 0) { 354 printk(KERN_ERR PFX "No usable aperture found.\n"); 355#ifdef __x86_64__ 356 /* should port this to i386 */ 357 printk(KERN_ERR PFX "Consider rebooting with iommu=memaper=2 to get a good aperture.\n"); 358#endif 359 return -1; 360 } 361 } 362 return 0; 363} 364 365/* Handle AMD 8151 quirks */ 366static void __devinit amd8151_init(struct pci_dev *pdev, struct agp_bridge_data *bridge) 367{ 368 char *revstring; 369 u8 rev_id; 370 371 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id); 372 switch (rev_id) { 373 case 0x01: revstring="A0"; break; 374 case 0x02: revstring="A1"; break; 375 case 0x11: revstring="B0"; break; 376 case 0x12: revstring="B1"; break; 377 case 0x13: revstring="B2"; break; 378 case 0x14: revstring="B3"; break; 379 default: revstring="??"; break; 380 } 381 382 printk (KERN_INFO PFX "Detected AMD 8151 AGP Bridge rev %s\n", revstring); 383 384 if (rev_id < 0x13) { 385 printk (KERN_INFO PFX "Correcting AGP revision (reports 3.5, is really 3.0)\n"); 386 bridge->major_version = 3; 387 bridge->minor_version = 0; 388 } 389} 390 391 392static const struct aper_size_info_32 uli_sizes[7] = 393{ 394 {256, 65536, 6, 10}, 395 {128, 32768, 5, 9}, 396 {64, 16384, 4, 8}, 397 {32, 8192, 3, 7}, 398 {16, 4096, 2, 6}, 399 {8, 2048, 1, 4}, 400 {4, 1024, 0, 3} 401}; 402static int __devinit uli_agp_init(struct pci_dev *pdev) 403{ 404 u32 httfea,baseaddr,enuscr; 405 struct pci_dev *dev1; 406 int i; 407 unsigned size = amd64_fetch_size(); 408 printk(KERN_INFO "Setting up ULi AGP.\n"); 409 dev1 = pci_get_slot (pdev->bus,PCI_DEVFN(0,0)); 410 if (dev1 == NULL) { 411 printk(KERN_INFO PFX "Detected a ULi chipset, " 412 "but could not fine the secondary device.\n"); 413 return -ENODEV; 414 } 415 416 for (i = 0; i < ARRAY_SIZE(uli_sizes); i++) 417 if (uli_sizes[i].size == size) 418 break; 419 420 if (i == ARRAY_SIZE(uli_sizes)) { 421 printk(KERN_INFO PFX "No ULi size found for %d\n", size); 422 return -ENODEV; 423 } 424 425 /* shadow x86-64 registers into ULi registers */ 426 pci_read_config_dword (k8_northbridges[0], AMD64_GARTAPERTUREBASE, &httfea); 427 428 /* if x86-64 aperture base is beyond 4G, exit here */ 429 if ((httfea & 0x7fff) >> (32 - 25)) 430 return -ENODEV; 431 432 httfea = (httfea& 0x7fff) << 25; 433 434 pci_read_config_dword(pdev, ULI_X86_64_BASE_ADDR, &baseaddr); 435 baseaddr&= ~PCI_BASE_ADDRESS_MEM_MASK; 436 baseaddr|= httfea; 437 pci_write_config_dword(pdev, ULI_X86_64_BASE_ADDR, baseaddr); 438 439 enuscr= httfea+ (size * 1024 * 1024) - 1; 440 pci_write_config_dword(dev1, ULI_X86_64_HTT_FEA_REG, httfea); 441 pci_write_config_dword(dev1, ULI_X86_64_ENU_SCR_REG, enuscr); 442 443 pci_dev_put(dev1); 444 return 0; 445} 446 447 448static const struct aper_size_info_32 nforce3_sizes[5] = 449{ 450 {512, 131072, 7, 0x00000000 }, 451 {256, 65536, 6, 0x00000008 }, 452 {128, 32768, 5, 0x0000000C }, 453 {64, 16384, 4, 0x0000000E }, 454 {32, 8192, 3, 0x0000000F } 455}; 456 457/* Handle shadow device of the Nvidia NForce3 */ 458/* CHECK-ME original 2.4 version set up some IORRs. Check if that is needed. */ 459static int nforce3_agp_init(struct pci_dev *pdev) 460{ 461 u32 tmp, apbase, apbar, aplimit; 462 struct pci_dev *dev1; 463 int i; 464 unsigned size = amd64_fetch_size(); 465 466 printk(KERN_INFO PFX "Setting up Nforce3 AGP.\n"); 467 468 dev1 = pci_get_slot(pdev->bus, PCI_DEVFN(11, 0)); 469 if (dev1 == NULL) { 470 printk(KERN_INFO PFX "agpgart: Detected an NVIDIA " 471 "nForce3 chipset, but could not find " 472 "the secondary device.\n"); 473 return -ENODEV; 474 } 475 476 for (i = 0; i < ARRAY_SIZE(nforce3_sizes); i++) 477 if (nforce3_sizes[i].size == size) 478 break; 479 480 if (i == ARRAY_SIZE(nforce3_sizes)) { 481 printk(KERN_INFO PFX "No NForce3 size found for %d\n", size); 482 return -ENODEV; 483 } 484 485 pci_read_config_dword(dev1, NVIDIA_X86_64_1_APSIZE, &tmp); 486 tmp &= ~(0xf); 487 tmp |= nforce3_sizes[i].size_value; 488 pci_write_config_dword(dev1, NVIDIA_X86_64_1_APSIZE, tmp); 489 490 /* shadow x86-64 registers into NVIDIA registers */ 491 pci_read_config_dword (k8_northbridges[0], AMD64_GARTAPERTUREBASE, &apbase); 492 493 /* if x86-64 aperture base is beyond 4G, exit here */ 494 if ( (apbase & 0x7fff) >> (32 - 25) ) { 495 printk(KERN_INFO PFX "aperture base > 4G\n"); 496 return -ENODEV; 497 } 498 499 apbase = (apbase & 0x7fff) << 25; 500 501 pci_read_config_dword(pdev, NVIDIA_X86_64_0_APBASE, &apbar); 502 apbar &= ~PCI_BASE_ADDRESS_MEM_MASK; 503 apbar |= apbase; 504 pci_write_config_dword(pdev, NVIDIA_X86_64_0_APBASE, apbar); 505 506 aplimit = apbase + (size * 1024 * 1024) - 1; 507 pci_write_config_dword(dev1, NVIDIA_X86_64_1_APBASE1, apbase); 508 pci_write_config_dword(dev1, NVIDIA_X86_64_1_APLIMIT1, aplimit); 509 pci_write_config_dword(dev1, NVIDIA_X86_64_1_APBASE2, apbase); 510 pci_write_config_dword(dev1, NVIDIA_X86_64_1_APLIMIT2, aplimit); 511 512 pci_dev_put(dev1); 513 514 return 0; 515} 516 517static int __devinit agp_amd64_probe(struct pci_dev *pdev, 518 const struct pci_device_id *ent) 519{ 520 struct agp_bridge_data *bridge; 521 u8 cap_ptr; 522 523 cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP); 524 if (!cap_ptr) 525 return -ENODEV; 526 527 /* Could check for AGPv3 here */ 528 529 bridge = agp_alloc_bridge(); 530 if (!bridge) 531 return -ENOMEM; 532 533 if (pdev->vendor == PCI_VENDOR_ID_AMD && 534 pdev->device == PCI_DEVICE_ID_AMD_8151_0) { 535 amd8151_init(pdev, bridge); 536 } else { 537 printk(KERN_INFO PFX "Detected AGP bridge %x\n", pdev->devfn); 538 } 539 540 bridge->driver = &amd_8151_driver; 541 bridge->dev = pdev; 542 bridge->capndx = cap_ptr; 543 544 /* Fill in the mode register */ 545 pci_read_config_dword(pdev, bridge->capndx+PCI_AGP_STATUS, &bridge->mode); 546 547 if (cache_nbs(pdev, cap_ptr) == -1) { 548 agp_put_bridge(bridge); 549 return -ENODEV; 550 } 551 552 if (pdev->vendor == PCI_VENDOR_ID_NVIDIA) { 553 int ret = nforce3_agp_init(pdev); 554 if (ret) { 555 agp_put_bridge(bridge); 556 return ret; 557 } 558 } 559 560 if (pdev->vendor == PCI_VENDOR_ID_AL) { 561 int ret = uli_agp_init(pdev); 562 if (ret) { 563 agp_put_bridge(bridge); 564 return ret; 565 } 566 } 567 568 pci_set_drvdata(pdev, bridge); 569 return agp_add_bridge(bridge); 570} 571 572static void __devexit agp_amd64_remove(struct pci_dev *pdev) 573{ 574 struct agp_bridge_data *bridge = pci_get_drvdata(pdev); 575 576 release_mem_region(virt_to_gart(bridge->gatt_table_real), 577 amd64_aperture_sizes[bridge->aperture_size_idx].size); 578 agp_remove_bridge(bridge); 579 agp_put_bridge(bridge); 580} 581 582#ifdef CONFIG_PM 583 584static int agp_amd64_suspend(struct pci_dev *pdev, pm_message_t state) 585{ 586 pci_save_state(pdev); 587 pci_set_power_state(pdev, pci_choose_state(pdev, state)); 588 589 return 0; 590} 591 592static int agp_amd64_resume(struct pci_dev *pdev) 593{ 594 pci_set_power_state(pdev, PCI_D0); 595 pci_restore_state(pdev); 596 597 if (pdev->vendor == PCI_VENDOR_ID_NVIDIA) 598 nforce3_agp_init(pdev); 599 600 return amd_8151_configure(); 601} 602 603#endif /* CONFIG_PM */ 604 605static struct pci_device_id agp_amd64_pci_table[] = { 606 { 607 .class = (PCI_CLASS_BRIDGE_HOST << 8), 608 .class_mask = ~0, 609 .vendor = PCI_VENDOR_ID_AMD, 610 .device = PCI_DEVICE_ID_AMD_8151_0, 611 .subvendor = PCI_ANY_ID, 612 .subdevice = PCI_ANY_ID, 613 }, 614 /* ULi M1689 */ 615 { 616 .class = (PCI_CLASS_BRIDGE_HOST << 8), 617 .class_mask = ~0, 618 .vendor = PCI_VENDOR_ID_AL, 619 .device = PCI_DEVICE_ID_AL_M1689, 620 .subvendor = PCI_ANY_ID, 621 .subdevice = PCI_ANY_ID, 622 }, 623 /* VIA K8T800Pro */ 624 { 625 .class = (PCI_CLASS_BRIDGE_HOST << 8), 626 .class_mask = ~0, 627 .vendor = PCI_VENDOR_ID_VIA, 628 .device = PCI_DEVICE_ID_VIA_K8T800PRO_0, 629 .subvendor = PCI_ANY_ID, 630 .subdevice = PCI_ANY_ID, 631 }, 632 /* VIA K8T800 */ 633 { 634 .class = (PCI_CLASS_BRIDGE_HOST << 8), 635 .class_mask = ~0, 636 .vendor = PCI_VENDOR_ID_VIA, 637 .device = PCI_DEVICE_ID_VIA_8385_0, 638 .subvendor = PCI_ANY_ID, 639 .subdevice = PCI_ANY_ID, 640 }, 641 /* VIA K8M800 / K8N800 */ 642 { 643 .class = (PCI_CLASS_BRIDGE_HOST << 8), 644 .class_mask = ~0, 645 .vendor = PCI_VENDOR_ID_VIA, 646 .device = PCI_DEVICE_ID_VIA_8380_0, 647 .subvendor = PCI_ANY_ID, 648 .subdevice = PCI_ANY_ID, 649 }, 650 /* VIA K8M890 / K8N890 */ 651 { 652 .class = (PCI_CLASS_BRIDGE_HOST << 8), 653 .class_mask = ~0, 654 .vendor = PCI_VENDOR_ID_VIA, 655 .device = PCI_DEVICE_ID_VIA_VT3336, 656 .subvendor = PCI_ANY_ID, 657 .subdevice = PCI_ANY_ID, 658 }, 659 /* VIA K8T890 */ 660 { 661 .class = (PCI_CLASS_BRIDGE_HOST << 8), 662 .class_mask = ~0, 663 .vendor = PCI_VENDOR_ID_VIA, 664 .device = PCI_DEVICE_ID_VIA_3238_0, 665 .subvendor = PCI_ANY_ID, 666 .subdevice = PCI_ANY_ID, 667 }, 668 /* VIA K8T800/K8M800/K8N800 */ 669 { 670 .class = (PCI_CLASS_BRIDGE_HOST << 8), 671 .class_mask = ~0, 672 .vendor = PCI_VENDOR_ID_VIA, 673 .device = PCI_DEVICE_ID_VIA_838X_1, 674 .subvendor = PCI_ANY_ID, 675 .subdevice = PCI_ANY_ID, 676 }, 677 /* NForce3 */ 678 { 679 .class = (PCI_CLASS_BRIDGE_HOST << 8), 680 .class_mask = ~0, 681 .vendor = PCI_VENDOR_ID_NVIDIA, 682 .device = PCI_DEVICE_ID_NVIDIA_NFORCE3, 683 .subvendor = PCI_ANY_ID, 684 .subdevice = PCI_ANY_ID, 685 }, 686 { 687 .class = (PCI_CLASS_BRIDGE_HOST << 8), 688 .class_mask = ~0, 689 .vendor = PCI_VENDOR_ID_NVIDIA, 690 .device = PCI_DEVICE_ID_NVIDIA_NFORCE3S, 691 .subvendor = PCI_ANY_ID, 692 .subdevice = PCI_ANY_ID, 693 }, 694 /* SIS 755 */ 695 { 696 .class = (PCI_CLASS_BRIDGE_HOST << 8), 697 .class_mask = ~0, 698 .vendor = PCI_VENDOR_ID_SI, 699 .device = PCI_DEVICE_ID_SI_755, 700 .subvendor = PCI_ANY_ID, 701 .subdevice = PCI_ANY_ID, 702 }, 703 /* SIS 760 */ 704 { 705 .class = (PCI_CLASS_BRIDGE_HOST << 8), 706 .class_mask = ~0, 707 .vendor = PCI_VENDOR_ID_SI, 708 .device = PCI_DEVICE_ID_SI_760, 709 .subvendor = PCI_ANY_ID, 710 .subdevice = PCI_ANY_ID, 711 }, 712 /* ALI/ULI M1695 */ 713 { 714 .class = (PCI_CLASS_BRIDGE_HOST << 8), 715 .class_mask = ~0, 716 .vendor = PCI_VENDOR_ID_AL, 717 .device = 0x1695, 718 .subvendor = PCI_ANY_ID, 719 .subdevice = PCI_ANY_ID, 720 }, 721 722 { } 723}; 724 725MODULE_DEVICE_TABLE(pci, agp_amd64_pci_table); 726 727static struct pci_driver agp_amd64_pci_driver = { 728 .name = "agpgart-amd64", 729 .id_table = agp_amd64_pci_table, 730 .probe = agp_amd64_probe, 731 .remove = agp_amd64_remove, 732#ifdef CONFIG_PM 733 .suspend = agp_amd64_suspend, 734 .resume = agp_amd64_resume, 735#endif 736}; 737 738 739/* Not static due to IOMMU code calling it early. */ 740int __init agp_amd64_init(void) 741{ 742 int err = 0; 743 744 if (agp_off) 745 return -EINVAL; 746 if (pci_register_driver(&agp_amd64_pci_driver) < 0) { 747 struct pci_dev *dev; 748 if (!agp_try_unsupported && !agp_try_unsupported_boot) { 749 printk(KERN_INFO PFX "No supported AGP bridge found.\n"); 750#ifdef MODULE 751 printk(KERN_INFO PFX "You can try agp_try_unsupported=1\n"); 752#else 753 printk(KERN_INFO PFX "You can boot with agp=try_unsupported\n"); 754#endif 755 return -ENODEV; 756 } 757 758 /* First check that we have at least one AMD64 NB */ 759 if (!pci_dev_present(k8_nb_ids)) 760 return -ENODEV; 761 762 /* Look for any AGP bridge */ 763 dev = NULL; 764 err = -ENODEV; 765 for_each_pci_dev(dev) { 766 if (!pci_find_capability(dev, PCI_CAP_ID_AGP)) 767 continue; 768 /* Only one bridge supported right now */ 769 if (agp_amd64_probe(dev, NULL) == 0) { 770 err = 0; 771 break; 772 } 773 } 774 } 775 return err; 776} 777 778static void __exit agp_amd64_cleanup(void) 779{ 780 if (aperture_resource) 781 release_resource(aperture_resource); 782 pci_unregister_driver(&agp_amd64_pci_driver); 783} 784 785/* On AMD64 the PCI driver needs to initialize this driver early 786 for the IOMMU, so it has to be called via a backdoor. */ 787#ifndef CONFIG_IOMMU 788module_init(agp_amd64_init); 789module_exit(agp_amd64_cleanup); 790#endif 791 792MODULE_AUTHOR("Dave Jones <davej@codemonkey.org.uk>, Andi Kleen"); 793module_param(agp_try_unsupported, bool, 0); 794MODULE_LICENSE("GPL"); 795