1/******************************************************************* 2 * ident "$Id: idt77252.h,v 1.1.1.1 2007/08/03 18:52:26 Exp $" 3 * 4 * $Author: rnuti $ 5 * $Date: 2007/08/03 18:52:26 $ 6 * 7 * Copyright (c) 2000 ATecoM GmbH 8 * 9 * The author may be reached at ecd@atecom.com. 10 * 11 * This program is free software; you can redistribute it and/or modify it 12 * under the terms of the GNU General Public License as published by the 13 * Free Software Foundation; either version 2 of the License, or (at your 14 * option) any later version. 15 * 16 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 19 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 22 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 23 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 * 27 * You should have received a copy of the GNU General Public License along 28 * with this program; if not, write to the Free Software Foundation, Inc., 29 * 675 Mass Ave, Cambridge, MA 02139, USA. 30 * 31 *******************************************************************/ 32 33#ifndef _IDT77252_H 34#define _IDT77252_H 1 35 36 37#include <linux/ptrace.h> 38#include <linux/skbuff.h> 39#include <linux/workqueue.h> 40#include <linux/mutex.h> 41 42/*****************************************************************************/ 43/* */ 44/* Makros */ 45/* */ 46/*****************************************************************************/ 47#define VPCI2VC(card, vpi, vci) \ 48 (((vpi) << card->vcibits) | ((vci) & card->vcimask)) 49 50/*****************************************************************************/ 51/* */ 52/* DEBUGGING definitions */ 53/* */ 54/*****************************************************************************/ 55 56#define DBG_RAW_CELL 0x00000400 57#define DBG_TINY 0x00000200 58#define DBG_GENERAL 0x00000100 59#define DBG_XGENERAL 0x00000080 60#define DBG_INIT 0x00000040 61#define DBG_DEINIT 0x00000020 62#define DBG_INTERRUPT 0x00000010 63#define DBG_OPEN_CONN 0x00000008 64#define DBG_CLOSE_CONN 0x00000004 65#define DBG_RX_DATA 0x00000002 66#define DBG_TX_DATA 0x00000001 67 68#ifdef CONFIG_ATM_IDT77252_DEBUG 69 70#define CPRINTK(args...) do { if (debug & DBG_CLOSE_CONN) printk(args); } while(0) 71#define OPRINTK(args...) do { if (debug & DBG_OPEN_CONN) printk(args); } while(0) 72#define IPRINTK(args...) do { if (debug & DBG_INIT) printk(args); } while(0) 73#define INTPRINTK(args...) do { if (debug & DBG_INTERRUPT) printk(args); } while(0) 74#define DIPRINTK(args...) do { if (debug & DBG_DEINIT) printk(args); } while(0) 75#define TXPRINTK(args...) do { if (debug & DBG_TX_DATA) printk(args); } while(0) 76#define RXPRINTK(args...) do { if (debug & DBG_RX_DATA) printk(args); } while(0) 77#define XPRINTK(args...) do { if (debug & DBG_XGENERAL) printk(args); } while(0) 78#define DPRINTK(args...) do { if (debug & DBG_GENERAL) printk(args); } while(0) 79#define NPRINTK(args...) do { if (debug & DBG_TINY) printk(args); } while(0) 80#define RPRINTK(args...) do { if (debug & DBG_RAW_CELL) printk(args); } while(0) 81 82#else 83 84#define CPRINTK(args...) do { } while(0) 85#define OPRINTK(args...) do { } while(0) 86#define IPRINTK(args...) do { } while(0) 87#define INTPRINTK(args...) do { } while(0) 88#define DIPRINTK(args...) do { } while(0) 89#define TXPRINTK(args...) do { } while(0) 90#define RXPRINTK(args...) do { } while(0) 91#define XPRINTK(args...) do { } while(0) 92#define DPRINTK(args...) do { } while(0) 93#define NPRINTK(args...) do { } while(0) 94#define RPRINTK(args...) do { } while(0) 95 96#endif 97 98#define SCHED_UBR0 0 99#define SCHED_UBR 1 100#define SCHED_VBR 2 101#define SCHED_ABR 3 102#define SCHED_CBR 4 103 104#define SCQFULL_TIMEOUT HZ 105 106/*****************************************************************************/ 107/* */ 108/* Free Buffer Queue Layout */ 109/* */ 110/*****************************************************************************/ 111#define SAR_FB_SIZE_0 (2048 - 256) 112#define SAR_FB_SIZE_1 (4096 - 256) 113#define SAR_FB_SIZE_2 (8192 - 256) 114#define SAR_FB_SIZE_3 (16384 - 256) 115 116#define SAR_FBQ0_LOW 4 117#define SAR_FBQ0_HIGH 8 118#define SAR_FBQ1_LOW 2 119#define SAR_FBQ1_HIGH 4 120#define SAR_FBQ2_LOW 1 121#define SAR_FBQ2_HIGH 2 122#define SAR_FBQ3_LOW 1 123#define SAR_FBQ3_HIGH 2 124 125#define SAR_TST_RESERVED 0 /* Num TST reserved for UBR/ABR/VBR */ 126 127#define TCT_CBR 0x00000000 128#define TCT_UBR 0x00000000 129#define TCT_VBR 0x40000000 130#define TCT_ABR 0x80000000 131#define TCT_TYPE 0xc0000000 132 133#define TCT_RR 0x20000000 134#define TCT_LMCR 0x08000000 135#define TCT_SCD_MASK 0x0007ffff 136 137#define TCT_TSIF 0x00004000 138#define TCT_HALT 0x80000000 139#define TCT_IDLE 0x40000000 140#define TCT_FLAG_UBR 0x80000000 141 142/*****************************************************************************/ 143/* */ 144/* Structure describing an IDT77252 */ 145/* */ 146/*****************************************************************************/ 147 148struct scqe 149{ 150 u32 word_1; 151 u32 word_2; 152 u32 word_3; 153 u32 word_4; 154}; 155 156#define SCQ_ENTRIES 64 157#define SCQ_SIZE (SCQ_ENTRIES * sizeof(struct scqe)) 158#define SCQ_MASK (SCQ_SIZE - 1) 159 160struct scq_info 161{ 162 struct scqe *base; 163 struct scqe *next; 164 struct scqe *last; 165 dma_addr_t paddr; 166 spinlock_t lock; 167 atomic_t used; 168 unsigned long trans_start; 169 unsigned long scd; 170 spinlock_t skblock; 171 struct sk_buff_head transmit; 172 struct sk_buff_head pending; 173}; 174 175struct rx_pool { 176 struct sk_buff *first; 177 struct sk_buff **last; 178 unsigned int len; 179 unsigned int count; 180}; 181 182struct aal1 { 183 unsigned int total; 184 unsigned int count; 185 struct sk_buff *data; 186 unsigned char sequence; 187}; 188 189struct rate_estimator { 190 struct timer_list timer; 191 unsigned int interval; 192 unsigned int ewma_log; 193 u64 cells; 194 u64 last_cells; 195 long avcps; 196 u32 cps; 197 u32 maxcps; 198}; 199 200struct vc_map { 201 unsigned int index; 202 unsigned long flags; 203#define VCF_TX 0 204#define VCF_RX 1 205#define VCF_IDLE 2 206#define VCF_RSV 3 207 unsigned int class; 208 u8 init_er; 209 u8 lacr; 210 u8 max_er; 211 unsigned int ntste; 212 spinlock_t lock; 213 struct atm_vcc *tx_vcc; 214 struct atm_vcc *rx_vcc; 215 struct idt77252_dev *card; 216 struct scq_info *scq; /* To keep track of the SCQ */ 217 struct rate_estimator *estimator; 218 int scd_index; 219 union { 220 struct rx_pool rx_pool; 221 struct aal1 aal1; 222 } rcv; 223}; 224 225/*****************************************************************************/ 226/* */ 227/* RCTE - Receive Connection Table Entry */ 228/* */ 229/*****************************************************************************/ 230 231struct rct_entry 232{ 233 u32 word_1; 234 u32 buffer_handle; 235 u32 dma_address; 236 u32 aal5_crc32; 237}; 238 239/*****************************************************************************/ 240/* */ 241/* RSQ - Receive Status Queue */ 242/* */ 243/*****************************************************************************/ 244 245#define SAR_RSQE_VALID 0x80000000 246#define SAR_RSQE_IDLE 0x40000000 247#define SAR_RSQE_BUF_MASK 0x00030000 248#define SAR_RSQE_BUF_ASGN 0x00008000 249#define SAR_RSQE_NZGFC 0x00004000 250#define SAR_RSQE_EPDU 0x00002000 251#define SAR_RSQE_BUF_CONT 0x00001000 252#define SAR_RSQE_EFCIE 0x00000800 253#define SAR_RSQE_CLP 0x00000400 254#define SAR_RSQE_CRC 0x00000200 255#define SAR_RSQE_CELLCNT 0x000001FF 256 257 258#define RSQSIZE 8192 259#define RSQ_NUM_ENTRIES (RSQSIZE / 16) 260#define RSQ_ALIGNMENT 8192 261 262struct rsq_entry { 263 u32 word_1; 264 u32 word_2; 265 u32 word_3; 266 u32 word_4; 267}; 268 269struct rsq_info { 270 struct rsq_entry *base; 271 struct rsq_entry *next; 272 struct rsq_entry *last; 273 dma_addr_t paddr; 274}; 275 276 277/*****************************************************************************/ 278/* */ 279/* TSQ - Transmit Status Queue */ 280/* */ 281/*****************************************************************************/ 282 283#define SAR_TSQE_INVALID 0x80000000 284#define SAR_TSQE_TIMESTAMP 0x00FFFFFF 285#define SAR_TSQE_TYPE 0x60000000 286#define SAR_TSQE_TYPE_TIMER 0x00000000 287#define SAR_TSQE_TYPE_TSR 0x20000000 288#define SAR_TSQE_TYPE_IDLE 0x40000000 289#define SAR_TSQE_TYPE_TBD_COMP 0x60000000 290 291#define SAR_TSQE_TAG(stat) (((stat) >> 24) & 0x1f) 292 293#define TSQSIZE 8192 294#define TSQ_NUM_ENTRIES 1024 295#define TSQ_ALIGNMENT 8192 296 297struct tsq_entry 298{ 299 u32 word_1; 300 u32 word_2; 301}; 302 303struct tsq_info 304{ 305 struct tsq_entry *base; 306 struct tsq_entry *next; 307 struct tsq_entry *last; 308 dma_addr_t paddr; 309}; 310 311struct tst_info 312{ 313 struct vc_map *vc; 314 u32 tste; 315}; 316 317#define TSTE_MASK 0x601fffff 318 319#define TSTE_OPC_MASK 0x60000000 320#define TSTE_OPC_NULL 0x00000000 321#define TSTE_OPC_CBR 0x20000000 322#define TSTE_OPC_VAR 0x40000000 323#define TSTE_OPC_JMP 0x60000000 324 325#define TSTE_PUSH_IDLE 0x01000000 326#define TSTE_PUSH_ACTIVE 0x02000000 327 328#define TST_SWITCH_DONE 0 329#define TST_SWITCH_PENDING 1 330#define TST_SWITCH_WAIT 2 331 332#define FBQ_SHIFT 9 333#define FBQ_SIZE (1 << FBQ_SHIFT) 334#define FBQ_MASK (FBQ_SIZE - 1) 335 336struct sb_pool 337{ 338 unsigned int index; 339 struct sk_buff *skb[FBQ_SIZE]; 340}; 341 342#define POOL_HANDLE(queue, index) (((queue + 1) << 16) | (index)) 343#define POOL_QUEUE(handle) (((handle) >> 16) - 1) 344#define POOL_INDEX(handle) ((handle) & 0xffff) 345 346struct idt77252_dev 347{ 348 struct tsq_info tsq; /* Transmit Status Queue */ 349 struct rsq_info rsq; /* Receive Status Queue */ 350 351 struct pci_dev *pcidev; /* PCI handle (desriptor) */ 352 struct atm_dev *atmdev; /* ATM device desriptor */ 353 354 void __iomem *membase; /* SAR's memory base address */ 355 unsigned long srambase; /* SAR's sram base address */ 356 void __iomem *fbq[4]; /* FBQ fill addresses */ 357 358 struct mutex mutex; 359 spinlock_t cmd_lock; /* for r/w utility/sram */ 360 361 unsigned long softstat; 362 unsigned long flags; /* see blow */ 363 364 struct work_struct tqueue; 365 366 unsigned long tct_base; /* TCT base address in SRAM */ 367 unsigned long rct_base; /* RCT base address in SRAM */ 368 unsigned long rt_base; /* Rate Table base in SRAM */ 369 unsigned long scd_base; /* SCD base address in SRAM */ 370 unsigned long tst[2]; /* TST base address in SRAM */ 371 unsigned long abrst_base; /* ABRST base address in SRAM */ 372 unsigned long fifo_base; /* RX FIFO base in SRAM */ 373 374 unsigned long irqstat[16]; 375 376 unsigned int sramsize; /* SAR's sram size */ 377 378 unsigned int tct_size; /* total TCT entries */ 379 unsigned int rct_size; /* total RCT entries */ 380 unsigned int scd_size; /* length of SCD */ 381 unsigned int tst_size; /* total TST entries */ 382 unsigned int tst_free; /* free TSTEs in TST */ 383 unsigned int abrst_size; /* size of ABRST in words */ 384 unsigned int fifo_size; /* size of RX FIFO in words */ 385 386 unsigned int vpibits; /* Bits used for VPI index */ 387 unsigned int vcibits; /* Bits used for VCI index */ 388 unsigned int vcimask; /* Mask for VCI index */ 389 390 unsigned int utopia_pcr; /* Utopia Itf's Cell Rate */ 391 unsigned int link_pcr; /* PHY's Peek Cell Rate */ 392 393 struct vc_map **vcs; /* Open Connections */ 394 struct vc_map **scd2vc; /* SCD to Connection map */ 395 396 struct tst_info *soft_tst; /* TST to Connection map */ 397 unsigned int tst_index; /* Current TST in use */ 398 struct timer_list tst_timer; 399 spinlock_t tst_lock; 400 unsigned long tst_state; 401 402 struct sb_pool sbpool[4]; /* Pool of RX skbuffs */ 403 struct sk_buff *raw_cell_head; /* Pointer to raw cell queue */ 404 u32 *raw_cell_hnd; /* Pointer to RCQ handle */ 405 dma_addr_t raw_cell_paddr; 406 407 int index; /* SAR's ID */ 408 int revision; /* chip revision */ 409 410 char name[16]; /* Device name */ 411 412 struct idt77252_dev *next; 413}; 414 415 416/* definition for flag field above */ 417#define IDT77252_BIT_INIT 1 418#define IDT77252_BIT_INTERRUPT 2 419 420 421#define ATM_CELL_PAYLOAD 48 422 423#define FREEBUF_ALIGNMENT 16 424 425/*****************************************************************************/ 426/* */ 427/* Makros */ 428/* */ 429/*****************************************************************************/ 430#define ALIGN_ADDRESS(addr, alignment) \ 431 ((((u32)(addr)) + (((u32)(alignment))-1)) & ~(((u32)(alignment)) - 1)) 432 433 434/*****************************************************************************/ 435/* */ 436/* ABR SAR Network operation Register */ 437/* */ 438/*****************************************************************************/ 439 440#define SAR_REG_DR0 (card->membase + 0x00) 441#define SAR_REG_DR1 (card->membase + 0x04) 442#define SAR_REG_DR2 (card->membase + 0x08) 443#define SAR_REG_DR3 (card->membase + 0x0C) 444#define SAR_REG_CMD (card->membase + 0x10) 445#define SAR_REG_CFG (card->membase + 0x14) 446#define SAR_REG_STAT (card->membase + 0x18) 447#define SAR_REG_RSQB (card->membase + 0x1C) 448#define SAR_REG_RSQT (card->membase + 0x20) 449#define SAR_REG_RSQH (card->membase + 0x24) 450#define SAR_REG_CDC (card->membase + 0x28) 451#define SAR_REG_VPEC (card->membase + 0x2C) 452#define SAR_REG_ICC (card->membase + 0x30) 453#define SAR_REG_RAWCT (card->membase + 0x34) 454#define SAR_REG_TMR (card->membase + 0x38) 455#define SAR_REG_TSTB (card->membase + 0x3C) 456#define SAR_REG_TSQB (card->membase + 0x40) 457#define SAR_REG_TSQT (card->membase + 0x44) 458#define SAR_REG_TSQH (card->membase + 0x48) 459#define SAR_REG_GP (card->membase + 0x4C) 460#define SAR_REG_VPM (card->membase + 0x50) 461#define SAR_REG_RXFD (card->membase + 0x54) 462#define SAR_REG_RXFT (card->membase + 0x58) 463#define SAR_REG_RXFH (card->membase + 0x5C) 464#define SAR_REG_RAWHND (card->membase + 0x60) 465#define SAR_REG_RXSTAT (card->membase + 0x64) 466#define SAR_REG_ABRSTD (card->membase + 0x68) 467#define SAR_REG_ABRRQ (card->membase + 0x6C) 468#define SAR_REG_VBRRQ (card->membase + 0x70) 469#define SAR_REG_RTBL (card->membase + 0x74) 470#define SAR_REG_MDFCT (card->membase + 0x78) 471#define SAR_REG_TXSTAT (card->membase + 0x7C) 472#define SAR_REG_TCMDQ (card->membase + 0x80) 473#define SAR_REG_IRCP (card->membase + 0x84) 474#define SAR_REG_FBQP0 (card->membase + 0x88) 475#define SAR_REG_FBQP1 (card->membase + 0x8C) 476#define SAR_REG_FBQP2 (card->membase + 0x90) 477#define SAR_REG_FBQP3 (card->membase + 0x94) 478#define SAR_REG_FBQS0 (card->membase + 0x98) 479#define SAR_REG_FBQS1 (card->membase + 0x9C) 480#define SAR_REG_FBQS2 (card->membase + 0xA0) 481#define SAR_REG_FBQS3 (card->membase + 0xA4) 482#define SAR_REG_FBQWP0 (card->membase + 0xA8) 483#define SAR_REG_FBQWP1 (card->membase + 0xAC) 484#define SAR_REG_FBQWP2 (card->membase + 0xB0) 485#define SAR_REG_FBQWP3 (card->membase + 0xB4) 486#define SAR_REG_NOW (card->membase + 0xB8) 487 488 489/*****************************************************************************/ 490/* */ 491/* Commands */ 492/* */ 493/*****************************************************************************/ 494 495#define SAR_CMD_NO_OPERATION 0x00000000 496#define SAR_CMD_OPENCLOSE_CONNECTION 0x20000000 497#define SAR_CMD_WRITE_SRAM 0x40000000 498#define SAR_CMD_READ_SRAM 0x50000000 499#define SAR_CMD_READ_UTILITY 0x80000000 500#define SAR_CMD_WRITE_UTILITY 0x90000000 501 502#define SAR_CMD_OPEN_CONNECTION (SAR_CMD_OPENCLOSE_CONNECTION | 0x00080000) 503#define SAR_CMD_CLOSE_CONNECTION SAR_CMD_OPENCLOSE_CONNECTION 504 505 506/*****************************************************************************/ 507/* */ 508/* Configuration Register bits */ 509/* */ 510/*****************************************************************************/ 511 512#define SAR_CFG_SWRST 0x80000000 /* Software reset */ 513#define SAR_CFG_LOOP 0x40000000 /* Internal Loopback */ 514#define SAR_CFG_RXPTH 0x20000000 /* Receive Path Enable */ 515#define SAR_CFG_IDLE_CLP 0x10000000 /* SAR set CLP Bits of Null Cells */ 516#define SAR_CFG_TX_FIFO_SIZE_1 0x04000000 /* TX FIFO Size = 1 cell */ 517#define SAR_CFG_TX_FIFO_SIZE_2 0x08000000 /* TX FIFO Size = 2 cells */ 518#define SAR_CFG_TX_FIFO_SIZE_4 0x0C000000 /* TX FIFO Size = 4 cells */ 519#define SAR_CFG_TX_FIFO_SIZE_9 0x00000000 /* TX FIFO Size = 9 cells (full) */ 520#define SAR_CFG_NO_IDLE 0x02000000 /* SAR sends no Null Cells */ 521#define SAR_CFG_RSVD1 0x01000000 /* Reserved */ 522#define SAR_CFG_RXSTQ_SIZE_2k 0x00000000 /* RX Stat Queue Size = 2048 byte */ 523#define SAR_CFG_RXSTQ_SIZE_4k 0x00400000 /* RX Stat Queue Size = 4096 byte */ 524#define SAR_CFG_RXSTQ_SIZE_8k 0x00800000 /* RX Stat Queue Size = 8192 byte */ 525#define SAR_CFG_RXSTQ_SIZE_R 0x00C00000 /* RX Stat Queue Size = reserved */ 526#define SAR_CFG_ICAPT 0x00200000 /* accept Invalid Cells */ 527#define SAR_CFG_IGGFC 0x00100000 /* Ignore GFC */ 528#define SAR_CFG_VPVCS_0 0x00000000 /* VPI/VCI Select bit range */ 529#define SAR_CFG_VPVCS_1 0x00040000 /* VPI/VCI Select bit range */ 530#define SAR_CFG_VPVCS_2 0x00080000 /* VPI/VCI Select bit range */ 531#define SAR_CFG_VPVCS_8 0x000C0000 /* VPI/VCI Select bit range */ 532#define SAR_CFG_CNTBL_1k 0x00000000 /* Connection Table Size */ 533#define SAR_CFG_CNTBL_4k 0x00010000 /* Connection Table Size */ 534#define SAR_CFG_CNTBL_16k 0x00020000 /* Connection Table Size */ 535#define SAR_CFG_CNTBL_512 0x00030000 /* Connection Table Size */ 536#define SAR_CFG_VPECA 0x00008000 /* VPI/VCI Error Cell Accept */ 537#define SAR_CFG_RXINT_NOINT 0x00000000 /* No Interrupt on PDU received */ 538#define SAR_CFG_RXINT_NODELAY 0x00001000 /* Interrupt without delay to host*/ 539#define SAR_CFG_RXINT_256US 0x00002000 /* Interrupt with delay 256 usec */ 540#define SAR_CFG_RXINT_505US 0x00003000 /* Interrupt with delay 505 usec */ 541#define SAR_CFG_RXINT_742US 0x00004000 /* Interrupt with delay 742 usec */ 542#define SAR_CFG_RAWIE 0x00000800 /* Raw Cell Queue Interrupt Enable*/ 543#define SAR_CFG_RQFIE 0x00000400 /* RSQ Almost Full Int Enable */ 544#define SAR_CFG_RSVD2 0x00000200 /* Reserved */ 545#define SAR_CFG_CACHE 0x00000100 /* DMA on Cache Line Boundary */ 546#define SAR_CFG_TMOIE 0x00000080 /* Timer Roll Over Int Enable */ 547#define SAR_CFG_FBIE 0x00000040 /* Free Buffer Queue Int Enable */ 548#define SAR_CFG_TXEN 0x00000020 /* Transmit Operation Enable */ 549#define SAR_CFG_TXINT 0x00000010 /* Transmit status Int Enable */ 550#define SAR_CFG_TXUIE 0x00000008 /* Transmit underrun Int Enable */ 551#define SAR_CFG_UMODE 0x00000004 /* Utopia Mode Select */ 552#define SAR_CFG_TXSFI 0x00000002 /* Transmit status Full Int Enable*/ 553#define SAR_CFG_PHYIE 0x00000001 /* PHY Interrupt Enable */ 554 555#define SAR_CFG_TX_FIFO_SIZE_MASK 0x0C000000 /* TX FIFO Size Mask */ 556#define SAR_CFG_RXSTQSIZE_MASK 0x00C00000 557#define SAR_CFG_CNTBL_MASK 0x00030000 558#define SAR_CFG_RXINT_MASK 0x00007000 559 560 561/*****************************************************************************/ 562/* */ 563/* Status Register bits */ 564/* */ 565/*****************************************************************************/ 566 567#define SAR_STAT_FRAC_3 0xF0000000 /* Fraction of Free Buffer Queue 3 */ 568#define SAR_STAT_FRAC_2 0x0F000000 /* Fraction of Free Buffer Queue 2 */ 569#define SAR_STAT_FRAC_1 0x00F00000 /* Fraction of Free Buffer Queue 1 */ 570#define SAR_STAT_FRAC_0 0x000F0000 /* Fraction of Free Buffer Queue 0 */ 571#define SAR_STAT_TSIF 0x00008000 /* Transmit Status Indicator */ 572#define SAR_STAT_TXICP 0x00004000 /* Transmit Status Indicator */ 573#define SAR_STAT_RSVD1 0x00002000 /* Reserved */ 574#define SAR_STAT_TSQF 0x00001000 /* Transmit Status Queue full */ 575#define SAR_STAT_TMROF 0x00000800 /* Timer overflow */ 576#define SAR_STAT_PHYI 0x00000400 /* PHY device Interrupt flag */ 577#define SAR_STAT_CMDBZ 0x00000200 /* ABR SAR Comand Busy Flag */ 578#define SAR_STAT_FBQ3A 0x00000100 /* Free Buffer Queue 3 Attention */ 579#define SAR_STAT_FBQ2A 0x00000080 /* Free Buffer Queue 2 Attention */ 580#define SAR_STAT_RSQF 0x00000040 /* Receive Status Queue full */ 581#define SAR_STAT_EPDU 0x00000020 /* End Of PDU Flag */ 582#define SAR_STAT_RAWCF 0x00000010 /* Raw Cell Flag */ 583#define SAR_STAT_FBQ1A 0x00000008 /* Free Buffer Queue 1 Attention */ 584#define SAR_STAT_FBQ0A 0x00000004 /* Free Buffer Queue 0 Attention */ 585#define SAR_STAT_RSQAF 0x00000002 /* Receive Status Queue almost full*/ 586#define SAR_STAT_RSVD2 0x00000001 /* Reserved */ 587 588 589/*****************************************************************************/ 590/* */ 591/* General Purpose Register bits */ 592/* */ 593/*****************************************************************************/ 594 595#define SAR_GP_TXNCC_MASK 0xff000000 /* Transmit Negative Credit Count */ 596#define SAR_GP_EEDI 0x00010000 /* EEPROM Data In */ 597#define SAR_GP_BIGE 0x00008000 /* Big Endian Operation */ 598#define SAR_GP_RM_NORMAL 0x00000000 /* Normal handling of RM cells */ 599#define SAR_GP_RM_TO_RCQ 0x00002000 /* put RM cells into Raw Cell Queue */ 600#define SAR_GP_RM_RSVD 0x00004000 /* Reserved */ 601#define SAR_GP_RM_INHIBIT 0x00006000 /* Inhibit update of Connection tab */ 602#define SAR_GP_PHY_RESET 0x00000008 /* PHY Reset */ 603#define SAR_GP_EESCLK 0x00000004 /* EEPROM SCLK */ 604#define SAR_GP_EECS 0x00000002 /* EEPROM Chip Select */ 605#define SAR_GP_EEDO 0x00000001 /* EEPROM Data Out */ 606 607 608/*****************************************************************************/ 609/* */ 610/* SAR local SRAM layout for 128k work SRAM */ 611/* */ 612/*****************************************************************************/ 613 614#define SAR_SRAM_SCD_SIZE 12 615#define SAR_SRAM_TCT_SIZE 8 616#define SAR_SRAM_RCT_SIZE 4 617 618#define SAR_SRAM_TCT_128_BASE 0x00000 619#define SAR_SRAM_TCT_128_TOP 0x01fff 620#define SAR_SRAM_RCT_128_BASE 0x02000 621#define SAR_SRAM_RCT_128_TOP 0x02fff 622#define SAR_SRAM_FB0_128_BASE 0x03000 623#define SAR_SRAM_FB0_128_TOP 0x033ff 624#define SAR_SRAM_FB1_128_BASE 0x03400 625#define SAR_SRAM_FB1_128_TOP 0x037ff 626#define SAR_SRAM_FB2_128_BASE 0x03800 627#define SAR_SRAM_FB2_128_TOP 0x03bff 628#define SAR_SRAM_FB3_128_BASE 0x03c00 629#define SAR_SRAM_FB3_128_TOP 0x03fff 630#define SAR_SRAM_SCD_128_BASE 0x04000 631#define SAR_SRAM_SCD_128_TOP 0x07fff 632#define SAR_SRAM_TST1_128_BASE 0x08000 633#define SAR_SRAM_TST1_128_TOP 0x0bfff 634#define SAR_SRAM_TST2_128_BASE 0x0c000 635#define SAR_SRAM_TST2_128_TOP 0x0ffff 636#define SAR_SRAM_ABRSTD_128_BASE 0x10000 637#define SAR_SRAM_ABRSTD_128_TOP 0x13fff 638#define SAR_SRAM_RT_128_BASE 0x14000 639#define SAR_SRAM_RT_128_TOP 0x15fff 640 641#define SAR_SRAM_FIFO_128_BASE 0x18000 642#define SAR_SRAM_FIFO_128_TOP 0x1ffff 643 644 645/*****************************************************************************/ 646/* */ 647/* SAR local SRAM layout for 32k work SRAM */ 648/* */ 649/*****************************************************************************/ 650 651#define SAR_SRAM_TCT_32_BASE 0x00000 652#define SAR_SRAM_TCT_32_TOP 0x00fff 653#define SAR_SRAM_RCT_32_BASE 0x01000 654#define SAR_SRAM_RCT_32_TOP 0x017ff 655#define SAR_SRAM_FB0_32_BASE 0x01800 656#define SAR_SRAM_FB0_32_TOP 0x01bff 657#define SAR_SRAM_FB1_32_BASE 0x01c00 658#define SAR_SRAM_FB1_32_TOP 0x01fff 659#define SAR_SRAM_FB2_32_BASE 0x02000 660#define SAR_SRAM_FB2_32_TOP 0x023ff 661#define SAR_SRAM_FB3_32_BASE 0x02400 662#define SAR_SRAM_FB3_32_TOP 0x027ff 663#define SAR_SRAM_SCD_32_BASE 0x02800 664#define SAR_SRAM_SCD_32_TOP 0x03fff 665#define SAR_SRAM_TST1_32_BASE 0x04000 666#define SAR_SRAM_TST1_32_TOP 0x04fff 667#define SAR_SRAM_TST2_32_BASE 0x05000 668#define SAR_SRAM_TST2_32_TOP 0x05fff 669#define SAR_SRAM_ABRSTD_32_BASE 0x06000 670#define SAR_SRAM_ABRSTD_32_TOP 0x067ff 671#define SAR_SRAM_RT_32_BASE 0x06800 672#define SAR_SRAM_RT_32_TOP 0x06fff 673#define SAR_SRAM_FIFO_32_BASE 0x07000 674#define SAR_SRAM_FIFO_32_TOP 0x07fff 675 676 677/*****************************************************************************/ 678/* */ 679/* TSR - Transmit Status Request */ 680/* */ 681/*****************************************************************************/ 682 683#define SAR_TSR_TYPE_TSR 0x80000000 684#define SAR_TSR_TYPE_TBD 0x00000000 685#define SAR_TSR_TSIF 0x20000000 686#define SAR_TSR_TAG_MASK 0x01F00000 687 688 689/*****************************************************************************/ 690/* */ 691/* TBD - Transmit Buffer Descriptor */ 692/* */ 693/*****************************************************************************/ 694 695#define SAR_TBD_EPDU 0x40000000 696#define SAR_TBD_TSIF 0x20000000 697#define SAR_TBD_OAM 0x10000000 698#define SAR_TBD_AAL0 0x00000000 699#define SAR_TBD_AAL34 0x04000000 700#define SAR_TBD_AAL5 0x08000000 701#define SAR_TBD_GTSI 0x02000000 702#define SAR_TBD_TAG_MASK 0x01F00000 703 704#define SAR_TBD_VPI_MASK 0x0FF00000 705#define SAR_TBD_VCI_MASK 0x000FFFF0 706#define SAR_TBD_VC_MASK (SAR_TBD_VPI_MASK | SAR_TBD_VCI_MASK) 707 708#define SAR_TBD_VPI_SHIFT 20 709#define SAR_TBD_VCI_SHIFT 4 710 711 712/*****************************************************************************/ 713/* */ 714/* RXFD - Receive FIFO Descriptor */ 715/* */ 716/*****************************************************************************/ 717 718#define SAR_RXFD_SIZE_MASK 0x0F000000 719#define SAR_RXFD_SIZE_512 0x00000000 /* 512 words */ 720#define SAR_RXFD_SIZE_1K 0x01000000 /* 1k words */ 721#define SAR_RXFD_SIZE_2K 0x02000000 /* 2k words */ 722#define SAR_RXFD_SIZE_4K 0x03000000 /* 4k words */ 723#define SAR_RXFD_SIZE_8K 0x04000000 /* 8k words */ 724#define SAR_RXFD_SIZE_16K 0x05000000 /* 16k words */ 725#define SAR_RXFD_SIZE_32K 0x06000000 /* 32k words */ 726#define SAR_RXFD_SIZE_64K 0x07000000 /* 64k words */ 727#define SAR_RXFD_SIZE_128K 0x08000000 /* 128k words */ 728#define SAR_RXFD_SIZE_256K 0x09000000 /* 256k words */ 729#define SAR_RXFD_ADDR_MASK 0x001ffc00 730 731 732/*****************************************************************************/ 733/* */ 734/* ABRSTD - ABR + VBR Schedule Tables */ 735/* */ 736/*****************************************************************************/ 737 738#define SAR_ABRSTD_SIZE_MASK 0x07000000 739#define SAR_ABRSTD_SIZE_512 0x00000000 /* 512 words */ 740#define SAR_ABRSTD_SIZE_1K 0x01000000 /* 1k words */ 741#define SAR_ABRSTD_SIZE_2K 0x02000000 /* 2k words */ 742#define SAR_ABRSTD_SIZE_4K 0x03000000 /* 4k words */ 743#define SAR_ABRSTD_SIZE_8K 0x04000000 /* 8k words */ 744#define SAR_ABRSTD_SIZE_16K 0x05000000 /* 16k words */ 745#define SAR_ABRSTD_ADDR_MASK 0x001ffc00 746 747 748/*****************************************************************************/ 749/* */ 750/* RCTE - Receive Connection Table Entry */ 751/* */ 752/*****************************************************************************/ 753 754#define SAR_RCTE_IL_MASK 0xE0000000 /* inactivity limit */ 755#define SAR_RCTE_IC_MASK 0x1C000000 /* inactivity count */ 756#define SAR_RCTE_RSVD 0x02000000 /* reserved */ 757#define SAR_RCTE_LCD 0x01000000 /* last cell data */ 758#define SAR_RCTE_CI_VC 0x00800000 /* EFCI in previous cell of VC */ 759#define SAR_RCTE_FBP_01 0x00000000 /* 1. cell->FBQ0, others->FBQ1 */ 760#define SAR_RCTE_FBP_1 0x00200000 /* use FBQ 1 for all cells */ 761#define SAR_RCTE_FBP_2 0x00400000 /* use FBQ 2 for all cells */ 762#define SAR_RCTE_FBP_3 0x00600000 /* use FBQ 3 for all cells */ 763#define SAR_RCTE_NZ_GFC 0x00100000 /* non zero GFC in all cell of VC */ 764#define SAR_RCTE_CONNECTOPEN 0x00080000 /* VC is open */ 765#define SAR_RCTE_AAL_MASK 0x00070000 /* mask for AAL type field s.b. */ 766#define SAR_RCTE_RAWCELLINTEN 0x00008000 /* raw cell interrupt enable */ 767#define SAR_RCTE_RXCONCELLADDR 0x00004000 /* RX constant cell address */ 768#define SAR_RCTE_BUFFSTAT_MASK 0x00003000 /* buffer status */ 769#define SAR_RCTE_EFCI 0x00000800 /* EFCI Congestion flag */ 770#define SAR_RCTE_CLP 0x00000400 /* Cell Loss Priority flag */ 771#define SAR_RCTE_CRC 0x00000200 /* Recieved CRC Error */ 772#define SAR_RCTE_CELLCNT_MASK 0x000001FF /* cell Count */ 773 774#define SAR_RCTE_AAL0 0x00000000 /* AAL types for ALL field */ 775#define SAR_RCTE_AAL34 0x00010000 776#define SAR_RCTE_AAL5 0x00020000 777#define SAR_RCTE_RCQ 0x00030000 778#define SAR_RCTE_OAM 0x00040000 779 780#define TCMDQ_START 0x01000000 781#define TCMDQ_LACR 0x02000000 782#define TCMDQ_START_LACR 0x03000000 783#define TCMDQ_INIT_ER 0x04000000 784#define TCMDQ_HALT 0x05000000 785 786 787struct idt77252_skb_prv { 788 struct scqe tbd; /* Transmit Buffer Descriptor */ 789 dma_addr_t paddr; /* DMA handle */ 790 u32 pool; /* sb_pool handle */ 791}; 792 793#define IDT77252_PRV_TBD(skb) \ 794 (((struct idt77252_skb_prv *)(ATM_SKB(skb)+1))->tbd) 795#define IDT77252_PRV_PADDR(skb) \ 796 (((struct idt77252_skb_prv *)(ATM_SKB(skb)+1))->paddr) 797#define IDT77252_PRV_POOL(skb) \ 798 (((struct idt77252_skb_prv *)(ATM_SKB(skb)+1))->pool) 799 800/*****************************************************************************/ 801/* */ 802/* PCI related items */ 803/* */ 804/*****************************************************************************/ 805 806#ifndef PCI_VENDOR_ID_IDT 807#define PCI_VENDOR_ID_IDT 0x111D 808#endif /* PCI_VENDOR_ID_IDT */ 809 810#ifndef PCI_DEVICE_ID_IDT_IDT77252 811#define PCI_DEVICE_ID_IDT_IDT77252 0x0003 812#endif /* PCI_DEVICE_ID_IDT_IDT772052 */ 813 814 815#endif /* !(_IDT77252_H) */ 816