1/* 2 * sata_sil24.c - Driver for Silicon Image 3124/3132 SATA-2 controllers 3 * 4 * Copyright 2005 Tejun Heo 5 * 6 * Based on preview driver from Silicon Image. 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License as published by the 10 * Free Software Foundation; either version 2, or (at your option) any 11 * later version. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * General Public License for more details. 17 * 18 */ 19 20#include <linux/kernel.h> 21#include <linux/module.h> 22#include <linux/pci.h> 23#include <linux/blkdev.h> 24#include <linux/delay.h> 25#include <linux/interrupt.h> 26#include <linux/dma-mapping.h> 27#include <linux/device.h> 28#include <scsi/scsi_host.h> 29#include <scsi/scsi_cmnd.h> 30#include <linux/libata.h> 31 32#define DRV_NAME "sata_sil24" 33#define DRV_VERSION "0.9" 34 35/* 36 * Port request block (PRB) 32 bytes 37 */ 38struct sil24_prb { 39 __le16 ctrl; 40 __le16 prot; 41 __le32 rx_cnt; 42 u8 fis[6 * 4]; 43}; 44 45/* 46 * Scatter gather entry (SGE) 16 bytes 47 */ 48struct sil24_sge { 49 __le64 addr; 50 __le32 cnt; 51 __le32 flags; 52}; 53 54/* 55 * Port multiplier 56 */ 57struct sil24_port_multiplier { 58 __le32 diag; 59 __le32 sactive; 60}; 61 62enum { 63 SIL24_HOST_BAR = 0, 64 SIL24_PORT_BAR = 2, 65 66 /* 67 * Global controller registers (128 bytes @ BAR0) 68 */ 69 /* 32 bit regs */ 70 HOST_SLOT_STAT = 0x00, /* 32 bit slot stat * 4 */ 71 HOST_CTRL = 0x40, 72 HOST_IRQ_STAT = 0x44, 73 HOST_PHY_CFG = 0x48, 74 HOST_BIST_CTRL = 0x50, 75 HOST_BIST_PTRN = 0x54, 76 HOST_BIST_STAT = 0x58, 77 HOST_MEM_BIST_STAT = 0x5c, 78 HOST_FLASH_CMD = 0x70, 79 /* 8 bit regs */ 80 HOST_FLASH_DATA = 0x74, 81 HOST_TRANSITION_DETECT = 0x75, 82 HOST_GPIO_CTRL = 0x76, 83 HOST_I2C_ADDR = 0x78, /* 32 bit */ 84 HOST_I2C_DATA = 0x7c, 85 HOST_I2C_XFER_CNT = 0x7e, 86 HOST_I2C_CTRL = 0x7f, 87 88 /* HOST_SLOT_STAT bits */ 89 HOST_SSTAT_ATTN = (1 << 31), 90 91 /* HOST_CTRL bits */ 92 HOST_CTRL_M66EN = (1 << 16), /* M66EN PCI bus signal */ 93 HOST_CTRL_TRDY = (1 << 17), /* latched PCI TRDY */ 94 HOST_CTRL_STOP = (1 << 18), /* latched PCI STOP */ 95 HOST_CTRL_DEVSEL = (1 << 19), /* latched PCI DEVSEL */ 96 HOST_CTRL_REQ64 = (1 << 20), /* latched PCI REQ64 */ 97 HOST_CTRL_GLOBAL_RST = (1 << 31), /* global reset */ 98 99 /* 100 * Port registers 101 * (8192 bytes @ +0x0000, +0x2000, +0x4000 and +0x6000 @ BAR2) 102 */ 103 PORT_REGS_SIZE = 0x2000, 104 105 PORT_LRAM = 0x0000, /* 31 LRAM slots and PMP regs */ 106 PORT_LRAM_SLOT_SZ = 0x0080, /* 32 bytes PRB + 2 SGE, ACT... */ 107 108 PORT_PMP = 0x0f80, /* 8 bytes PMP * 16 (128 bytes) */ 109 PORT_PMP_STATUS = 0x0000, /* port device status offset */ 110 PORT_PMP_QACTIVE = 0x0004, /* port device QActive offset */ 111 PORT_PMP_SIZE = 0x0008, /* 8 bytes per PMP */ 112 113 /* 32 bit regs */ 114 PORT_CTRL_STAT = 0x1000, /* write: ctrl-set, read: stat */ 115 PORT_CTRL_CLR = 0x1004, /* write: ctrl-clear */ 116 PORT_IRQ_STAT = 0x1008, /* high: status, low: interrupt */ 117 PORT_IRQ_ENABLE_SET = 0x1010, /* write: enable-set */ 118 PORT_IRQ_ENABLE_CLR = 0x1014, /* write: enable-clear */ 119 PORT_ACTIVATE_UPPER_ADDR= 0x101c, 120 PORT_EXEC_FIFO = 0x1020, /* command execution fifo */ 121 PORT_CMD_ERR = 0x1024, /* command error number */ 122 PORT_FIS_CFG = 0x1028, 123 PORT_FIFO_THRES = 0x102c, 124 /* 16 bit regs */ 125 PORT_DECODE_ERR_CNT = 0x1040, 126 PORT_DECODE_ERR_THRESH = 0x1042, 127 PORT_CRC_ERR_CNT = 0x1044, 128 PORT_CRC_ERR_THRESH = 0x1046, 129 PORT_HSHK_ERR_CNT = 0x1048, 130 PORT_HSHK_ERR_THRESH = 0x104a, 131 /* 32 bit regs */ 132 PORT_PHY_CFG = 0x1050, 133 PORT_SLOT_STAT = 0x1800, 134 PORT_CMD_ACTIVATE = 0x1c00, /* 64 bit cmd activate * 31 (248 bytes) */ 135 PORT_CONTEXT = 0x1e04, 136 PORT_EXEC_DIAG = 0x1e00, /* 32bit exec diag * 16 (64 bytes, 0-10 used on 3124) */ 137 PORT_PSD_DIAG = 0x1e40, /* 32bit psd diag * 16 (64 bytes, 0-8 used on 3124) */ 138 PORT_SCONTROL = 0x1f00, 139 PORT_SSTATUS = 0x1f04, 140 PORT_SERROR = 0x1f08, 141 PORT_SACTIVE = 0x1f0c, 142 143 /* PORT_CTRL_STAT bits */ 144 PORT_CS_PORT_RST = (1 << 0), /* port reset */ 145 PORT_CS_DEV_RST = (1 << 1), /* device reset */ 146 PORT_CS_INIT = (1 << 2), /* port initialize */ 147 PORT_CS_IRQ_WOC = (1 << 3), /* interrupt write one to clear */ 148 PORT_CS_CDB16 = (1 << 5), /* 0=12b cdb, 1=16b cdb */ 149 PORT_CS_PMP_RESUME = (1 << 6), /* PMP resume */ 150 PORT_CS_32BIT_ACTV = (1 << 10), /* 32-bit activation */ 151 PORT_CS_PMP_EN = (1 << 13), /* port multiplier enable */ 152 PORT_CS_RDY = (1 << 31), /* port ready to accept commands */ 153 154 /* PORT_IRQ_STAT/ENABLE_SET/CLR */ 155 /* bits[11:0] are masked */ 156 PORT_IRQ_COMPLETE = (1 << 0), /* command(s) completed */ 157 PORT_IRQ_ERROR = (1 << 1), /* command execution error */ 158 PORT_IRQ_PORTRDY_CHG = (1 << 2), /* port ready change */ 159 PORT_IRQ_PWR_CHG = (1 << 3), /* power management change */ 160 PORT_IRQ_PHYRDY_CHG = (1 << 4), /* PHY ready change */ 161 PORT_IRQ_COMWAKE = (1 << 5), /* COMWAKE received */ 162 PORT_IRQ_UNK_FIS = (1 << 6), /* unknown FIS received */ 163 PORT_IRQ_DEV_XCHG = (1 << 7), /* device exchanged */ 164 PORT_IRQ_8B10B = (1 << 8), /* 8b/10b decode error threshold */ 165 PORT_IRQ_CRC = (1 << 9), /* CRC error threshold */ 166 PORT_IRQ_HANDSHAKE = (1 << 10), /* handshake error threshold */ 167 PORT_IRQ_SDB_NOTIFY = (1 << 11), /* SDB notify received */ 168 169 DEF_PORT_IRQ = PORT_IRQ_COMPLETE | PORT_IRQ_ERROR | 170 PORT_IRQ_PHYRDY_CHG | PORT_IRQ_DEV_XCHG | 171 PORT_IRQ_UNK_FIS, 172 173 /* bits[27:16] are unmasked (raw) */ 174 PORT_IRQ_RAW_SHIFT = 16, 175 PORT_IRQ_MASKED_MASK = 0x7ff, 176 PORT_IRQ_RAW_MASK = (0x7ff << PORT_IRQ_RAW_SHIFT), 177 178 /* ENABLE_SET/CLR specific, intr steering - 2 bit field */ 179 PORT_IRQ_STEER_SHIFT = 30, 180 PORT_IRQ_STEER_MASK = (3 << PORT_IRQ_STEER_SHIFT), 181 182 /* PORT_CMD_ERR constants */ 183 PORT_CERR_DEV = 1, /* Error bit in D2H Register FIS */ 184 PORT_CERR_SDB = 2, /* Error bit in SDB FIS */ 185 PORT_CERR_DATA = 3, /* Error in data FIS not detected by dev */ 186 PORT_CERR_SEND = 4, /* Initial cmd FIS transmission failure */ 187 PORT_CERR_INCONSISTENT = 5, /* Protocol mismatch */ 188 PORT_CERR_DIRECTION = 6, /* Data direction mismatch */ 189 PORT_CERR_UNDERRUN = 7, /* Ran out of SGEs while writing */ 190 PORT_CERR_OVERRUN = 8, /* Ran out of SGEs while reading */ 191 PORT_CERR_PKT_PROT = 11, /* DIR invalid in 1st PIO setup of ATAPI */ 192 PORT_CERR_SGT_BOUNDARY = 16, /* PLD ecode 00 - SGT not on qword boundary */ 193 PORT_CERR_SGT_TGTABRT = 17, /* PLD ecode 01 - target abort */ 194 PORT_CERR_SGT_MSTABRT = 18, /* PLD ecode 10 - master abort */ 195 PORT_CERR_SGT_PCIPERR = 19, /* PLD ecode 11 - PCI parity err while fetching SGT */ 196 PORT_CERR_CMD_BOUNDARY = 24, /* ctrl[15:13] 001 - PRB not on qword boundary */ 197 PORT_CERR_CMD_TGTABRT = 25, /* ctrl[15:13] 010 - target abort */ 198 PORT_CERR_CMD_MSTABRT = 26, /* ctrl[15:13] 100 - master abort */ 199 PORT_CERR_CMD_PCIPERR = 27, /* ctrl[15:13] 110 - PCI parity err while fetching PRB */ 200 PORT_CERR_XFR_UNDEF = 32, /* PSD ecode 00 - undefined */ 201 PORT_CERR_XFR_TGTABRT = 33, /* PSD ecode 01 - target abort */ 202 PORT_CERR_XFR_MSTABRT = 34, /* PSD ecode 10 - master abort */ 203 PORT_CERR_XFR_PCIPERR = 35, /* PSD ecode 11 - PCI prity err during transfer */ 204 PORT_CERR_SENDSERVICE = 36, /* FIS received while sending service */ 205 206 /* bits of PRB control field */ 207 PRB_CTRL_PROTOCOL = (1 << 0), /* override def. ATA protocol */ 208 PRB_CTRL_PACKET_READ = (1 << 4), /* PACKET cmd read */ 209 PRB_CTRL_PACKET_WRITE = (1 << 5), /* PACKET cmd write */ 210 PRB_CTRL_NIEN = (1 << 6), /* Mask completion irq */ 211 PRB_CTRL_SRST = (1 << 7), /* Soft reset request (ign BSY?) */ 212 213 /* PRB protocol field */ 214 PRB_PROT_PACKET = (1 << 0), 215 PRB_PROT_TCQ = (1 << 1), 216 PRB_PROT_NCQ = (1 << 2), 217 PRB_PROT_READ = (1 << 3), 218 PRB_PROT_WRITE = (1 << 4), 219 PRB_PROT_TRANSPARENT = (1 << 5), 220 221 /* 222 * Other constants 223 */ 224 SGE_TRM = (1 << 31), /* Last SGE in chain */ 225 SGE_LNK = (1 << 30), /* linked list 226 Points to SGT, not SGE */ 227 SGE_DRD = (1 << 29), /* discard data read (/dev/null) 228 data address ignored */ 229 230 SIL24_MAX_CMDS = 31, 231 232 /* board id */ 233 BID_SIL3124 = 0, 234 BID_SIL3132 = 1, 235 BID_SIL3131 = 2, 236 237 /* host flags */ 238 SIL24_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | 239 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA | 240 ATA_FLAG_NCQ | ATA_FLAG_SKIP_D2H_BSY | 241 ATA_FLAG_ACPI_SATA, 242 SIL24_FLAG_PCIX_IRQ_WOC = (1 << 24), /* IRQ loss errata on PCI-X */ 243 244 IRQ_STAT_4PORTS = 0xf, 245}; 246 247struct sil24_ata_block { 248 struct sil24_prb prb; 249 struct sil24_sge sge[LIBATA_MAX_PRD]; 250}; 251 252struct sil24_atapi_block { 253 struct sil24_prb prb; 254 u8 cdb[16]; 255 struct sil24_sge sge[LIBATA_MAX_PRD - 1]; 256}; 257 258union sil24_cmd_block { 259 struct sil24_ata_block ata; 260 struct sil24_atapi_block atapi; 261}; 262 263static struct sil24_cerr_info { 264 unsigned int err_mask, action; 265 const char *desc; 266} sil24_cerr_db[] = { 267 [0] = { AC_ERR_DEV, ATA_EH_REVALIDATE, 268 "device error" }, 269 [PORT_CERR_DEV] = { AC_ERR_DEV, ATA_EH_REVALIDATE, 270 "device error via D2H FIS" }, 271 [PORT_CERR_SDB] = { AC_ERR_DEV, ATA_EH_REVALIDATE, 272 "device error via SDB FIS" }, 273 [PORT_CERR_DATA] = { AC_ERR_ATA_BUS, ATA_EH_SOFTRESET, 274 "error in data FIS" }, 275 [PORT_CERR_SEND] = { AC_ERR_ATA_BUS, ATA_EH_SOFTRESET, 276 "failed to transmit command FIS" }, 277 [PORT_CERR_INCONSISTENT] = { AC_ERR_HSM, ATA_EH_SOFTRESET, 278 "protocol mismatch" }, 279 [PORT_CERR_DIRECTION] = { AC_ERR_HSM, ATA_EH_SOFTRESET, 280 "data directon mismatch" }, 281 [PORT_CERR_UNDERRUN] = { AC_ERR_HSM, ATA_EH_SOFTRESET, 282 "ran out of SGEs while writing" }, 283 [PORT_CERR_OVERRUN] = { AC_ERR_HSM, ATA_EH_SOFTRESET, 284 "ran out of SGEs while reading" }, 285 [PORT_CERR_PKT_PROT] = { AC_ERR_HSM, ATA_EH_SOFTRESET, 286 "invalid data directon for ATAPI CDB" }, 287 [PORT_CERR_SGT_BOUNDARY] = { AC_ERR_SYSTEM, ATA_EH_SOFTRESET, 288 "SGT no on qword boundary" }, 289 [PORT_CERR_SGT_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET, 290 "PCI target abort while fetching SGT" }, 291 [PORT_CERR_SGT_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET, 292 "PCI master abort while fetching SGT" }, 293 [PORT_CERR_SGT_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET, 294 "PCI parity error while fetching SGT" }, 295 [PORT_CERR_CMD_BOUNDARY] = { AC_ERR_SYSTEM, ATA_EH_SOFTRESET, 296 "PRB not on qword boundary" }, 297 [PORT_CERR_CMD_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET, 298 "PCI target abort while fetching PRB" }, 299 [PORT_CERR_CMD_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET, 300 "PCI master abort while fetching PRB" }, 301 [PORT_CERR_CMD_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET, 302 "PCI parity error while fetching PRB" }, 303 [PORT_CERR_XFR_UNDEF] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET, 304 "undefined error while transferring data" }, 305 [PORT_CERR_XFR_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET, 306 "PCI target abort while transferring data" }, 307 [PORT_CERR_XFR_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET, 308 "PCI master abort while transferring data" }, 309 [PORT_CERR_XFR_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET, 310 "PCI parity error while transferring data" }, 311 [PORT_CERR_SENDSERVICE] = { AC_ERR_HSM, ATA_EH_SOFTRESET, 312 "FIS received while sending service FIS" }, 313}; 314 315/* 316 * ap->private_data 317 * 318 * The preview driver always returned 0 for status. We emulate it 319 * here from the previous interrupt. 320 */ 321struct sil24_port_priv { 322 union sil24_cmd_block *cmd_block; /* 32 cmd blocks */ 323 dma_addr_t cmd_block_dma; /* DMA base addr for them */ 324 struct ata_taskfile tf; /* Cached taskfile registers */ 325}; 326 327static void sil24_dev_config(struct ata_device *dev); 328static u8 sil24_check_status(struct ata_port *ap); 329static u32 sil24_scr_read(struct ata_port *ap, unsigned sc_reg); 330static void sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val); 331static void sil24_tf_read(struct ata_port *ap, struct ata_taskfile *tf); 332static void sil24_qc_prep(struct ata_queued_cmd *qc); 333static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc); 334static void sil24_irq_clear(struct ata_port *ap); 335static void sil24_freeze(struct ata_port *ap); 336static void sil24_thaw(struct ata_port *ap); 337static void sil24_error_handler(struct ata_port *ap); 338static void sil24_post_internal_cmd(struct ata_queued_cmd *qc); 339static int sil24_port_start(struct ata_port *ap); 340static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent); 341#ifdef CONFIG_PM 342static int sil24_pci_device_resume(struct pci_dev *pdev); 343#endif 344 345static const struct pci_device_id sil24_pci_tbl[] = { 346 { PCI_VDEVICE(CMD, 0x3124), BID_SIL3124 }, 347 { PCI_VDEVICE(INTEL, 0x3124), BID_SIL3124 }, 348 { PCI_VDEVICE(CMD, 0x3132), BID_SIL3132 }, 349 { PCI_VDEVICE(CMD, 0x0242), BID_SIL3132 }, 350 { PCI_VDEVICE(CMD, 0x3131), BID_SIL3131 }, 351 { PCI_VDEVICE(CMD, 0x3531), BID_SIL3131 }, 352 353 { } /* terminate list */ 354}; 355 356static struct pci_driver sil24_pci_driver = { 357 .name = DRV_NAME, 358 .id_table = sil24_pci_tbl, 359 .probe = sil24_init_one, 360 .remove = ata_pci_remove_one, 361#ifdef CONFIG_PM 362 .suspend = ata_pci_device_suspend, 363 .resume = sil24_pci_device_resume, 364#endif 365}; 366 367static struct scsi_host_template sil24_sht = { 368 .module = THIS_MODULE, 369 .name = DRV_NAME, 370 .ioctl = ata_scsi_ioctl, 371 .queuecommand = ata_scsi_queuecmd, 372 .change_queue_depth = ata_scsi_change_queue_depth, 373 .can_queue = SIL24_MAX_CMDS, 374 .this_id = ATA_SHT_THIS_ID, 375 .sg_tablesize = LIBATA_MAX_PRD, 376 .cmd_per_lun = ATA_SHT_CMD_PER_LUN, 377 .emulated = ATA_SHT_EMULATED, 378 .use_clustering = ATA_SHT_USE_CLUSTERING, 379 .proc_name = DRV_NAME, 380 .dma_boundary = ATA_DMA_BOUNDARY, 381 .slave_configure = ata_scsi_slave_config, 382 .slave_destroy = ata_scsi_slave_destroy, 383 .bios_param = ata_std_bios_param, 384}; 385 386static const struct ata_port_operations sil24_ops = { 387 .port_disable = ata_port_disable, 388 389 .dev_config = sil24_dev_config, 390 391 .check_status = sil24_check_status, 392 .check_altstatus = sil24_check_status, 393 .dev_select = ata_noop_dev_select, 394 395 .tf_read = sil24_tf_read, 396 397 .qc_prep = sil24_qc_prep, 398 .qc_issue = sil24_qc_issue, 399 400 .irq_clear = sil24_irq_clear, 401 .irq_on = ata_dummy_irq_on, 402 .irq_ack = ata_dummy_irq_ack, 403 404 .scr_read = sil24_scr_read, 405 .scr_write = sil24_scr_write, 406 407 .freeze = sil24_freeze, 408 .thaw = sil24_thaw, 409 .error_handler = sil24_error_handler, 410 .post_internal_cmd = sil24_post_internal_cmd, 411 412 .port_start = sil24_port_start, 413}; 414 415/* 416 * Use bits 30-31 of port_flags to encode available port numbers. 417 * Current maxium is 4. 418 */ 419#define SIL24_NPORTS2FLAG(nports) ((((unsigned)(nports) - 1) & 0x3) << 30) 420#define SIL24_FLAG2NPORTS(flag) ((((flag) >> 30) & 0x3) + 1) 421 422static const struct ata_port_info sil24_port_info[] = { 423 /* sil_3124 */ 424 { 425 .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(4) | 426 SIL24_FLAG_PCIX_IRQ_WOC, 427 .pio_mask = 0x1f, /* pio0-4 */ 428 .mwdma_mask = 0x07, /* mwdma0-2 */ 429 .udma_mask = 0x3f, /* udma0-5 */ 430 .port_ops = &sil24_ops, 431 }, 432 /* sil_3132 */ 433 { 434 .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(2), 435 .pio_mask = 0x1f, /* pio0-4 */ 436 .mwdma_mask = 0x07, /* mwdma0-2 */ 437 .udma_mask = 0x3f, /* udma0-5 */ 438 .port_ops = &sil24_ops, 439 }, 440 /* sil_3131/sil_3531 */ 441 { 442 .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(1), 443 .pio_mask = 0x1f, /* pio0-4 */ 444 .mwdma_mask = 0x07, /* mwdma0-2 */ 445 .udma_mask = 0x3f, /* udma0-5 */ 446 .port_ops = &sil24_ops, 447 }, 448}; 449 450static int sil24_tag(int tag) 451{ 452 if (unlikely(ata_tag_internal(tag))) 453 return 0; 454 return tag; 455} 456 457static void sil24_dev_config(struct ata_device *dev) 458{ 459 void __iomem *port = dev->ap->ioaddr.cmd_addr; 460 461 if (dev->cdb_len == 16) 462 writel(PORT_CS_CDB16, port + PORT_CTRL_STAT); 463 else 464 writel(PORT_CS_CDB16, port + PORT_CTRL_CLR); 465} 466 467static inline void sil24_update_tf(struct ata_port *ap) 468{ 469 struct sil24_port_priv *pp = ap->private_data; 470 void __iomem *port = ap->ioaddr.cmd_addr; 471 struct sil24_prb __iomem *prb = port; 472 u8 fis[6 * 4]; 473 474 memcpy_fromio(fis, prb->fis, 6 * 4); 475 ata_tf_from_fis(fis, &pp->tf); 476} 477 478static u8 sil24_check_status(struct ata_port *ap) 479{ 480 struct sil24_port_priv *pp = ap->private_data; 481 return pp->tf.command; 482} 483 484static int sil24_scr_map[] = { 485 [SCR_CONTROL] = 0, 486 [SCR_STATUS] = 1, 487 [SCR_ERROR] = 2, 488 [SCR_ACTIVE] = 3, 489}; 490 491static u32 sil24_scr_read(struct ata_port *ap, unsigned sc_reg) 492{ 493 void __iomem *scr_addr = ap->ioaddr.scr_addr; 494 if (sc_reg < ARRAY_SIZE(sil24_scr_map)) { 495 void __iomem *addr; 496 addr = scr_addr + sil24_scr_map[sc_reg] * 4; 497 return readl(scr_addr + sil24_scr_map[sc_reg] * 4); 498 } 499 return 0xffffffffU; 500} 501 502static void sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val) 503{ 504 void __iomem *scr_addr = ap->ioaddr.scr_addr; 505 if (sc_reg < ARRAY_SIZE(sil24_scr_map)) { 506 void __iomem *addr; 507 addr = scr_addr + sil24_scr_map[sc_reg] * 4; 508 writel(val, scr_addr + sil24_scr_map[sc_reg] * 4); 509 } 510} 511 512static void sil24_tf_read(struct ata_port *ap, struct ata_taskfile *tf) 513{ 514 struct sil24_port_priv *pp = ap->private_data; 515 *tf = pp->tf; 516} 517 518static int sil24_init_port(struct ata_port *ap) 519{ 520 void __iomem *port = ap->ioaddr.cmd_addr; 521 u32 tmp; 522 523 writel(PORT_CS_INIT, port + PORT_CTRL_STAT); 524 ata_wait_register(port + PORT_CTRL_STAT, 525 PORT_CS_INIT, PORT_CS_INIT, 10, 100); 526 tmp = ata_wait_register(port + PORT_CTRL_STAT, 527 PORT_CS_RDY, 0, 10, 100); 528 529 if ((tmp & (PORT_CS_INIT | PORT_CS_RDY)) != PORT_CS_RDY) 530 return -EIO; 531 return 0; 532} 533 534static int sil24_softreset(struct ata_port *ap, unsigned int *class, 535 unsigned long deadline) 536{ 537 void __iomem *port = ap->ioaddr.cmd_addr; 538 struct sil24_port_priv *pp = ap->private_data; 539 struct sil24_prb *prb = &pp->cmd_block[0].ata.prb; 540 dma_addr_t paddr = pp->cmd_block_dma; 541 u32 mask, irq_stat; 542 const char *reason; 543 544 DPRINTK("ENTER\n"); 545 546 if (ata_port_offline(ap)) { 547 DPRINTK("PHY reports no device\n"); 548 *class = ATA_DEV_NONE; 549 goto out; 550 } 551 552 /* put the port into known state */ 553 if (sil24_init_port(ap)) { 554 reason ="port not ready"; 555 goto err; 556 } 557 558 /* do SRST */ 559 prb->ctrl = cpu_to_le16(PRB_CTRL_SRST); 560 prb->fis[1] = 0; /* no PMP yet */ 561 562 writel((u32)paddr, port + PORT_CMD_ACTIVATE); 563 writel((u64)paddr >> 32, port + PORT_CMD_ACTIVATE + 4); 564 565 mask = (PORT_IRQ_COMPLETE | PORT_IRQ_ERROR) << PORT_IRQ_RAW_SHIFT; 566 irq_stat = ata_wait_register(port + PORT_IRQ_STAT, mask, 0x0, 567 100, jiffies_to_msecs(deadline - jiffies)); 568 569 writel(irq_stat, port + PORT_IRQ_STAT); /* clear IRQs */ 570 irq_stat >>= PORT_IRQ_RAW_SHIFT; 571 572 if (!(irq_stat & PORT_IRQ_COMPLETE)) { 573 if (irq_stat & PORT_IRQ_ERROR) 574 reason = "SRST command error"; 575 else 576 reason = "timeout"; 577 goto err; 578 } 579 580 sil24_update_tf(ap); 581 *class = ata_dev_classify(&pp->tf); 582 583 if (*class == ATA_DEV_UNKNOWN) 584 *class = ATA_DEV_NONE; 585 586 out: 587 DPRINTK("EXIT, class=%u\n", *class); 588 return 0; 589 590 err: 591 ata_port_printk(ap, KERN_ERR, "softreset failed (%s)\n", reason); 592 return -EIO; 593} 594 595static int sil24_hardreset(struct ata_port *ap, unsigned int *class, 596 unsigned long deadline) 597{ 598 void __iomem *port = ap->ioaddr.cmd_addr; 599 const char *reason; 600 int tout_msec, rc; 601 u32 tmp; 602 603 /* sil24 does the right thing(tm) without any protection */ 604 sata_set_spd(ap); 605 606 tout_msec = 100; 607 if (ata_port_online(ap)) 608 tout_msec = 5000; 609 610 writel(PORT_CS_DEV_RST, port + PORT_CTRL_STAT); 611 tmp = ata_wait_register(port + PORT_CTRL_STAT, 612 PORT_CS_DEV_RST, PORT_CS_DEV_RST, 10, tout_msec); 613 614 /* SStatus oscillates between zero and valid status after 615 * DEV_RST, debounce it. 616 */ 617 rc = sata_phy_debounce(ap, sata_deb_timing_long, deadline); 618 if (rc) { 619 reason = "PHY debouncing failed"; 620 goto err; 621 } 622 623 if (tmp & PORT_CS_DEV_RST) { 624 if (ata_port_offline(ap)) 625 return 0; 626 reason = "link not ready"; 627 goto err; 628 } 629 630 /* Sil24 doesn't store signature FIS after hardreset, so we 631 * can't wait for BSY to clear. Some devices take a long time 632 * to get ready and those devices will choke if we don't wait 633 * for BSY clearance here. Tell libata to perform follow-up 634 * softreset. 635 */ 636 return -EAGAIN; 637 638 err: 639 ata_port_printk(ap, KERN_ERR, "hardreset failed (%s)\n", reason); 640 return -EIO; 641} 642 643static inline void sil24_fill_sg(struct ata_queued_cmd *qc, 644 struct sil24_sge *sge) 645{ 646 struct scatterlist *sg; 647 648 ata_for_each_sg(sg, qc) { 649 sge->addr = cpu_to_le64(sg_dma_address(sg)); 650 sge->cnt = cpu_to_le32(sg_dma_len(sg)); 651 if (ata_sg_is_last(sg, qc)) 652 sge->flags = cpu_to_le32(SGE_TRM); 653 else 654 sge->flags = 0; 655 sge++; 656 } 657} 658 659static void sil24_qc_prep(struct ata_queued_cmd *qc) 660{ 661 struct ata_port *ap = qc->ap; 662 struct sil24_port_priv *pp = ap->private_data; 663 union sil24_cmd_block *cb; 664 struct sil24_prb *prb; 665 struct sil24_sge *sge; 666 u16 ctrl = 0; 667 668 cb = &pp->cmd_block[sil24_tag(qc->tag)]; 669 670 switch (qc->tf.protocol) { 671 case ATA_PROT_PIO: 672 case ATA_PROT_DMA: 673 case ATA_PROT_NCQ: 674 case ATA_PROT_NODATA: 675 prb = &cb->ata.prb; 676 sge = cb->ata.sge; 677 break; 678 679 case ATA_PROT_ATAPI: 680 case ATA_PROT_ATAPI_DMA: 681 case ATA_PROT_ATAPI_NODATA: 682 prb = &cb->atapi.prb; 683 sge = cb->atapi.sge; 684 memset(cb->atapi.cdb, 0, 32); 685 memcpy(cb->atapi.cdb, qc->cdb, qc->dev->cdb_len); 686 687 if (qc->tf.protocol != ATA_PROT_ATAPI_NODATA) { 688 if (qc->tf.flags & ATA_TFLAG_WRITE) 689 ctrl = PRB_CTRL_PACKET_WRITE; 690 else 691 ctrl = PRB_CTRL_PACKET_READ; 692 } 693 break; 694 695 default: 696 prb = NULL; /* shut up, gcc */ 697 sge = NULL; 698 BUG(); 699 } 700 701 prb->ctrl = cpu_to_le16(ctrl); 702 ata_tf_to_fis(&qc->tf, prb->fis, 0); 703 704 if (qc->flags & ATA_QCFLAG_DMAMAP) 705 sil24_fill_sg(qc, sge); 706} 707 708static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc) 709{ 710 struct ata_port *ap = qc->ap; 711 struct sil24_port_priv *pp = ap->private_data; 712 void __iomem *port = ap->ioaddr.cmd_addr; 713 unsigned int tag = sil24_tag(qc->tag); 714 dma_addr_t paddr; 715 void __iomem *activate; 716 717 paddr = pp->cmd_block_dma + tag * sizeof(*pp->cmd_block); 718 activate = port + PORT_CMD_ACTIVATE + tag * 8; 719 720 writel((u32)paddr, activate); 721 writel((u64)paddr >> 32, activate + 4); 722 723 return 0; 724} 725 726static void sil24_irq_clear(struct ata_port *ap) 727{ 728 /* unused */ 729} 730 731static void sil24_freeze(struct ata_port *ap) 732{ 733 void __iomem *port = ap->ioaddr.cmd_addr; 734 735 /* Port-wide IRQ mask in HOST_CTRL doesn't really work, clear 736 * PORT_IRQ_ENABLE instead. 737 */ 738 writel(0xffff, port + PORT_IRQ_ENABLE_CLR); 739} 740 741static void sil24_thaw(struct ata_port *ap) 742{ 743 void __iomem *port = ap->ioaddr.cmd_addr; 744 u32 tmp; 745 746 /* clear IRQ */ 747 tmp = readl(port + PORT_IRQ_STAT); 748 writel(tmp, port + PORT_IRQ_STAT); 749 750 /* turn IRQ back on */ 751 writel(DEF_PORT_IRQ, port + PORT_IRQ_ENABLE_SET); 752} 753 754static void sil24_error_intr(struct ata_port *ap) 755{ 756 void __iomem *port = ap->ioaddr.cmd_addr; 757 struct ata_eh_info *ehi = &ap->eh_info; 758 int freeze = 0; 759 u32 irq_stat; 760 761 /* on error, we need to clear IRQ explicitly */ 762 irq_stat = readl(port + PORT_IRQ_STAT); 763 writel(irq_stat, port + PORT_IRQ_STAT); 764 765 /* first, analyze and record host port events */ 766 ata_ehi_clear_desc(ehi); 767 768 ata_ehi_push_desc(ehi, "irq_stat 0x%08x", irq_stat); 769 770 if (irq_stat & (PORT_IRQ_PHYRDY_CHG | PORT_IRQ_DEV_XCHG)) { 771 ata_ehi_hotplugged(ehi); 772 ata_ehi_push_desc(ehi, ", %s", 773 irq_stat & PORT_IRQ_PHYRDY_CHG ? 774 "PHY RDY changed" : "device exchanged"); 775 freeze = 1; 776 } 777 778 if (irq_stat & PORT_IRQ_UNK_FIS) { 779 ehi->err_mask |= AC_ERR_HSM; 780 ehi->action |= ATA_EH_SOFTRESET; 781 ata_ehi_push_desc(ehi , ", unknown FIS"); 782 freeze = 1; 783 } 784 785 /* deal with command error */ 786 if (irq_stat & PORT_IRQ_ERROR) { 787 struct sil24_cerr_info *ci = NULL; 788 unsigned int err_mask = 0, action = 0; 789 struct ata_queued_cmd *qc; 790 u32 cerr; 791 792 /* analyze CMD_ERR */ 793 cerr = readl(port + PORT_CMD_ERR); 794 if (cerr < ARRAY_SIZE(sil24_cerr_db)) 795 ci = &sil24_cerr_db[cerr]; 796 797 if (ci && ci->desc) { 798 err_mask |= ci->err_mask; 799 action |= ci->action; 800 ata_ehi_push_desc(ehi, ", %s", ci->desc); 801 } else { 802 err_mask |= AC_ERR_OTHER; 803 action |= ATA_EH_SOFTRESET; 804 ata_ehi_push_desc(ehi, ", unknown command error %d", 805 cerr); 806 } 807 808 /* record error info */ 809 qc = ata_qc_from_tag(ap, ap->active_tag); 810 if (qc) { 811 sil24_update_tf(ap); 812 qc->err_mask |= err_mask; 813 } else 814 ehi->err_mask |= err_mask; 815 816 ehi->action |= action; 817 } 818 819 /* freeze or abort */ 820 if (freeze) 821 ata_port_freeze(ap); 822 else 823 ata_port_abort(ap); 824} 825 826static void sil24_finish_qc(struct ata_queued_cmd *qc) 827{ 828 if (qc->flags & ATA_QCFLAG_RESULT_TF) 829 sil24_update_tf(qc->ap); 830} 831 832static inline void sil24_host_intr(struct ata_port *ap) 833{ 834 void __iomem *port = ap->ioaddr.cmd_addr; 835 u32 slot_stat, qc_active; 836 int rc; 837 838 slot_stat = readl(port + PORT_SLOT_STAT); 839 840 if (unlikely(slot_stat & HOST_SSTAT_ATTN)) { 841 sil24_error_intr(ap); 842 return; 843 } 844 845 if (ap->flags & SIL24_FLAG_PCIX_IRQ_WOC) 846 writel(PORT_IRQ_COMPLETE, port + PORT_IRQ_STAT); 847 848 qc_active = slot_stat & ~HOST_SSTAT_ATTN; 849 rc = ata_qc_complete_multiple(ap, qc_active, sil24_finish_qc); 850 if (rc > 0) 851 return; 852 if (rc < 0) { 853 struct ata_eh_info *ehi = &ap->eh_info; 854 ehi->err_mask |= AC_ERR_HSM; 855 ehi->action |= ATA_EH_SOFTRESET; 856 ata_port_freeze(ap); 857 return; 858 } 859 860 if (ata_ratelimit()) 861 ata_port_printk(ap, KERN_INFO, "spurious interrupt " 862 "(slot_stat 0x%x active_tag %d sactive 0x%x)\n", 863 slot_stat, ap->active_tag, ap->sactive); 864} 865 866static irqreturn_t sil24_interrupt(int irq, void *dev_instance) 867{ 868 struct ata_host *host = dev_instance; 869 void __iomem *host_base = host->iomap[SIL24_HOST_BAR]; 870 unsigned handled = 0; 871 u32 status; 872 int i; 873 874 status = readl(host_base + HOST_IRQ_STAT); 875 876 if (status == 0xffffffff) { 877 printk(KERN_ERR DRV_NAME ": IRQ status == 0xffffffff, " 878 "PCI fault or device removal?\n"); 879 goto out; 880 } 881 882 if (!(status & IRQ_STAT_4PORTS)) 883 goto out; 884 885 spin_lock(&host->lock); 886 887 for (i = 0; i < host->n_ports; i++) 888 if (status & (1 << i)) { 889 struct ata_port *ap = host->ports[i]; 890 if (ap && !(ap->flags & ATA_FLAG_DISABLED)) { 891 sil24_host_intr(host->ports[i]); 892 handled++; 893 } else 894 printk(KERN_ERR DRV_NAME 895 ": interrupt from disabled port %d\n", i); 896 } 897 898 spin_unlock(&host->lock); 899 out: 900 return IRQ_RETVAL(handled); 901} 902 903static void sil24_error_handler(struct ata_port *ap) 904{ 905 struct ata_eh_context *ehc = &ap->eh_context; 906 907 if (sil24_init_port(ap)) { 908 ata_eh_freeze_port(ap); 909 ehc->i.action |= ATA_EH_HARDRESET; 910 } 911 912 /* perform recovery */ 913 ata_do_eh(ap, ata_std_prereset, sil24_softreset, sil24_hardreset, 914 ata_std_postreset); 915} 916 917static void sil24_post_internal_cmd(struct ata_queued_cmd *qc) 918{ 919 struct ata_port *ap = qc->ap; 920 921 /* make DMA engine forget about the failed command */ 922 if (qc->flags & ATA_QCFLAG_FAILED) 923 sil24_init_port(ap); 924} 925 926static int sil24_port_start(struct ata_port *ap) 927{ 928 struct device *dev = ap->host->dev; 929 struct sil24_port_priv *pp; 930 union sil24_cmd_block *cb; 931 size_t cb_size = sizeof(*cb) * SIL24_MAX_CMDS; 932 dma_addr_t cb_dma; 933 int rc; 934 935 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); 936 if (!pp) 937 return -ENOMEM; 938 939 pp->tf.command = ATA_DRDY; 940 941 cb = dmam_alloc_coherent(dev, cb_size, &cb_dma, GFP_KERNEL); 942 if (!cb) 943 return -ENOMEM; 944 memset(cb, 0, cb_size); 945 946 rc = ata_pad_alloc(ap, dev); 947 if (rc) 948 return rc; 949 950 pp->cmd_block = cb; 951 pp->cmd_block_dma = cb_dma; 952 953 ap->private_data = pp; 954 955 return 0; 956} 957 958static void sil24_init_controller(struct ata_host *host) 959{ 960 void __iomem *host_base = host->iomap[SIL24_HOST_BAR]; 961 void __iomem *port_base = host->iomap[SIL24_PORT_BAR]; 962 u32 tmp; 963 int i; 964 965 /* GPIO off */ 966 writel(0, host_base + HOST_FLASH_CMD); 967 968 /* clear global reset & mask interrupts during initialization */ 969 writel(0, host_base + HOST_CTRL); 970 971 /* init ports */ 972 for (i = 0; i < host->n_ports; i++) { 973 void __iomem *port = port_base + i * PORT_REGS_SIZE; 974 975 /* Initial PHY setting */ 976 writel(0x20c, port + PORT_PHY_CFG); 977 978 /* Clear port RST */ 979 tmp = readl(port + PORT_CTRL_STAT); 980 if (tmp & PORT_CS_PORT_RST) { 981 writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR); 982 tmp = ata_wait_register(port + PORT_CTRL_STAT, 983 PORT_CS_PORT_RST, 984 PORT_CS_PORT_RST, 10, 100); 985 if (tmp & PORT_CS_PORT_RST) 986 dev_printk(KERN_ERR, host->dev, 987 "failed to clear port RST\n"); 988 } 989 990 /* Configure IRQ WoC */ 991 if (host->ports[0]->flags & SIL24_FLAG_PCIX_IRQ_WOC) 992 writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_STAT); 993 else 994 writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_CLR); 995 996 /* Zero error counters. */ 997 writel(0x8000, port + PORT_DECODE_ERR_THRESH); 998 writel(0x8000, port + PORT_CRC_ERR_THRESH); 999 writel(0x8000, port + PORT_HSHK_ERR_THRESH); 1000 writel(0x0000, port + PORT_DECODE_ERR_CNT); 1001 writel(0x0000, port + PORT_CRC_ERR_CNT); 1002 writel(0x0000, port + PORT_HSHK_ERR_CNT); 1003 1004 /* Always use 64bit activation */ 1005 writel(PORT_CS_32BIT_ACTV, port + PORT_CTRL_CLR); 1006 1007 /* Clear port multiplier enable and resume bits */ 1008 writel(PORT_CS_PMP_EN | PORT_CS_PMP_RESUME, 1009 port + PORT_CTRL_CLR); 1010 } 1011 1012 /* Turn on interrupts */ 1013 writel(IRQ_STAT_4PORTS, host_base + HOST_CTRL); 1014} 1015 1016static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 1017{ 1018 static int printed_version = 0; 1019 struct ata_port_info pi = sil24_port_info[ent->driver_data]; 1020 const struct ata_port_info *ppi[] = { &pi, NULL }; 1021 void __iomem * const *iomap; 1022 struct ata_host *host; 1023 int i, rc; 1024 u32 tmp; 1025 1026 if (!printed_version++) 1027 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); 1028 1029 /* acquire resources */ 1030 rc = pcim_enable_device(pdev); 1031 if (rc) 1032 return rc; 1033 1034 rc = pcim_iomap_regions(pdev, 1035 (1 << SIL24_HOST_BAR) | (1 << SIL24_PORT_BAR), 1036 DRV_NAME); 1037 if (rc) 1038 return rc; 1039 iomap = pcim_iomap_table(pdev); 1040 1041 if (pi.flags & SIL24_FLAG_PCIX_IRQ_WOC) { 1042 tmp = readl(iomap[SIL24_HOST_BAR] + HOST_CTRL); 1043 if (tmp & (HOST_CTRL_TRDY | HOST_CTRL_STOP | HOST_CTRL_DEVSEL)) 1044 dev_printk(KERN_INFO, &pdev->dev, 1045 "Applying completion IRQ loss on PCI-X " 1046 "errata fix\n"); 1047 else 1048 pi.flags &= ~SIL24_FLAG_PCIX_IRQ_WOC; 1049 } 1050 1051 /* allocate and fill host */ 1052 host = ata_host_alloc_pinfo(&pdev->dev, ppi, 1053 SIL24_FLAG2NPORTS(ppi[0]->flags)); 1054 if (!host) 1055 return -ENOMEM; 1056 host->iomap = iomap; 1057 1058 for (i = 0; i < host->n_ports; i++) { 1059 void __iomem *port = iomap[SIL24_PORT_BAR] + i * PORT_REGS_SIZE; 1060 1061 host->ports[i]->ioaddr.cmd_addr = port; 1062 host->ports[i]->ioaddr.scr_addr = port + PORT_SCONTROL; 1063 1064 ata_std_ports(&host->ports[i]->ioaddr); 1065 } 1066 1067 /* configure and activate the device */ 1068 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) { 1069 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK); 1070 if (rc) { 1071 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); 1072 if (rc) { 1073 dev_printk(KERN_ERR, &pdev->dev, 1074 "64-bit DMA enable failed\n"); 1075 return rc; 1076 } 1077 } 1078 } else { 1079 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK); 1080 if (rc) { 1081 dev_printk(KERN_ERR, &pdev->dev, 1082 "32-bit DMA enable failed\n"); 1083 return rc; 1084 } 1085 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); 1086 if (rc) { 1087 dev_printk(KERN_ERR, &pdev->dev, 1088 "32-bit consistent DMA enable failed\n"); 1089 return rc; 1090 } 1091 } 1092 1093 sil24_init_controller(host); 1094 1095 pci_set_master(pdev); 1096 return ata_host_activate(host, pdev->irq, sil24_interrupt, IRQF_SHARED, 1097 &sil24_sht); 1098} 1099 1100#ifdef CONFIG_PM 1101static int sil24_pci_device_resume(struct pci_dev *pdev) 1102{ 1103 struct ata_host *host = dev_get_drvdata(&pdev->dev); 1104 void __iomem *host_base = host->iomap[SIL24_HOST_BAR]; 1105 int rc; 1106 1107 rc = ata_pci_device_do_resume(pdev); 1108 if (rc) 1109 return rc; 1110 1111 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) 1112 writel(HOST_CTRL_GLOBAL_RST, host_base + HOST_CTRL); 1113 1114 sil24_init_controller(host); 1115 1116 ata_host_resume(host); 1117 1118 return 0; 1119} 1120#endif 1121 1122static int __init sil24_init(void) 1123{ 1124 return pci_register_driver(&sil24_pci_driver); 1125} 1126 1127static void __exit sil24_exit(void) 1128{ 1129 pci_unregister_driver(&sil24_pci_driver); 1130} 1131 1132MODULE_AUTHOR("Tejun Heo"); 1133MODULE_DESCRIPTION("Silicon Image 3124/3132 SATA low-level driver"); 1134MODULE_LICENSE("GPL"); 1135MODULE_DEVICE_TABLE(pci, sil24_pci_tbl); 1136 1137module_init(sil24_init); 1138module_exit(sil24_exit); 1139