1/* 2 * pata_sis.c - SiS ATA driver 3 * 4 * (C) 2005 Red Hat <alan@redhat.com> 5 * 6 * Based upon linux/drivers/ide/pci/sis5513.c 7 * Copyright (C) 1999-2000 Andre Hedrick <andre@linux-ide.org> 8 * Copyright (C) 2002 Lionel Bouton <Lionel.Bouton@inet6.fr>, Maintainer 9 * Copyright (C) 2003 Vojtech Pavlik <vojtech@suse.cz> 10 * SiS Taiwan : for direct support and hardware. 11 * Daniela Engert : for initial ATA100 advices and numerous others. 12 * John Fremlin, Manfred Spraul, Dave Morgan, Peter Kjellerstedt : 13 * for checking code correctness, providing patches. 14 * Original tests and design on the SiS620 chipset. 15 * ATA100 tests and design on the SiS735 chipset. 16 * ATA16/33 support from specs 17 * ATA133 support for SiS961/962 by L.C. Chang <lcchang@sis.com.tw> 18 * 19 * 20 * TODO 21 * Check MWDMA on drives that don't support MWDMA speed pio cycles ? 22 * More Testing 23 */ 24 25#include <linux/kernel.h> 26#include <linux/module.h> 27#include <linux/pci.h> 28#include <linux/init.h> 29#include <linux/blkdev.h> 30#include <linux/delay.h> 31#include <linux/device.h> 32#include <scsi/scsi_host.h> 33#include <linux/libata.h> 34#include <linux/ata.h> 35#include "sis.h" 36 37#define DRV_NAME "pata_sis" 38#define DRV_VERSION "0.5.1" 39 40struct sis_chipset { 41 u16 device; /* PCI host ID */ 42 const struct ata_port_info *info; /* Info block */ 43 /* Probably add family, cable detect type etc here to clean 44 up code later */ 45}; 46 47struct sis_laptop { 48 u16 device; 49 u16 subvendor; 50 u16 subdevice; 51}; 52 53static const struct sis_laptop sis_laptop[] = { 54 /* devid, subvendor, subdev */ 55 { 0x5513, 0x1043, 0x1107 }, /* ASUS A6K */ 56 /* end marker */ 57 { 0, } 58}; 59 60static int sis_short_ata40(struct pci_dev *dev) 61{ 62 const struct sis_laptop *lap = &sis_laptop[0]; 63 64 while (lap->device) { 65 if (lap->device == dev->device && 66 lap->subvendor == dev->subsystem_vendor && 67 lap->subdevice == dev->subsystem_device) 68 return 1; 69 lap++; 70 } 71 72 return 0; 73} 74 75/** 76 * sis_old_port_base - return PCI configuration base for dev 77 * @adev: device 78 * 79 * Returns the base of the PCI configuration registers for this port 80 * number. 81 */ 82 83static int sis_old_port_base(struct ata_device *adev) 84{ 85 return 0x40 + (4 * adev->ap->port_no) + (2 * adev->devno); 86} 87 88/** 89 * sis_133_cable_detect - check for 40/80 pin 90 * @ap: Port 91 * @deadline: deadline jiffies for the operation 92 * 93 * Perform cable detection for the later UDMA133 capable 94 * SiS chipset. 95 */ 96 97static int sis_133_cable_detect(struct ata_port *ap) 98{ 99 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 100 u16 tmp; 101 102 /* The top bit of this register is the cable detect bit */ 103 pci_read_config_word(pdev, 0x50 + 2 * ap->port_no, &tmp); 104 if ((tmp & 0x8000) && !sis_short_ata40(pdev)) 105 return ATA_CBL_PATA40; 106 return ATA_CBL_PATA80; 107} 108 109/** 110 * sis_66_cable_detect - check for 40/80 pin 111 * @ap: Port 112 * @deadline: deadline jiffies for the operation 113 * 114 * Perform cable detection on the UDMA66, UDMA100 and early UDMA133 115 * SiS IDE controllers. 116 */ 117 118static int sis_66_cable_detect(struct ata_port *ap) 119{ 120 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 121 u8 tmp; 122 123 /* Older chips keep cable detect in bits 4/5 of reg 0x48 */ 124 pci_read_config_byte(pdev, 0x48, &tmp); 125 tmp >>= ap->port_no; 126 if ((tmp & 0x10) && !sis_short_ata40(pdev)) 127 return ATA_CBL_PATA40; 128 return ATA_CBL_PATA80; 129} 130 131 132/** 133 * sis_pre_reset - probe begin 134 * @ap: ATA port 135 * @deadline: deadline jiffies for the operation 136 * 137 * Set up cable type and use generic probe init 138 */ 139 140static int sis_pre_reset(struct ata_port *ap, unsigned long deadline) 141{ 142 static const struct pci_bits sis_enable_bits[] = { 143 { 0x4aU, 1U, 0x02UL, 0x02UL }, /* port 0 */ 144 { 0x4aU, 1U, 0x04UL, 0x04UL }, /* port 1 */ 145 }; 146 147 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 148 149 if (!pci_test_config_bits(pdev, &sis_enable_bits[ap->port_no])) 150 return -ENOENT; 151 152 return ata_std_prereset(ap, deadline); 153} 154 155 156/** 157 * sis_error_handler - Probe specified port on PATA host controller 158 * @ap: Port to probe 159 * 160 * LOCKING: 161 * None (inherited from caller). 162 */ 163 164static void sis_error_handler(struct ata_port *ap) 165{ 166 ata_bmdma_drive_eh(ap, sis_pre_reset, ata_std_softreset, NULL, ata_std_postreset); 167} 168 169/** 170 * sis_set_fifo - Set RWP fifo bits for this device 171 * @ap: Port 172 * @adev: Device 173 * 174 * SIS chipsets implement prefetch/postwrite bits for each device 175 * on both channels. This functionality is not ATAPI compatible and 176 * must be configured according to the class of device present 177 */ 178 179static void sis_set_fifo(struct ata_port *ap, struct ata_device *adev) 180{ 181 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 182 u8 fifoctrl; 183 u8 mask = 0x11; 184 185 mask <<= (2 * ap->port_no); 186 mask <<= adev->devno; 187 188 /* This holds various bits including the FIFO control */ 189 pci_read_config_byte(pdev, 0x4B, &fifoctrl); 190 fifoctrl &= ~mask; 191 192 /* Enable for ATA (disk) only */ 193 if (adev->class == ATA_DEV_ATA) 194 fifoctrl |= mask; 195 pci_write_config_byte(pdev, 0x4B, fifoctrl); 196} 197 198/** 199 * sis_old_set_piomode - Initialize host controller PATA PIO timings 200 * @ap: Port whose timings we are configuring 201 * @adev: Device we are configuring for. 202 * 203 * Set PIO mode for device, in host controller PCI config space. This 204 * function handles PIO set up for all chips that are pre ATA100 and 205 * also early ATA100 devices. 206 * 207 * LOCKING: 208 * None (inherited from caller). 209 */ 210 211static void sis_old_set_piomode (struct ata_port *ap, struct ata_device *adev) 212{ 213 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 214 int port = sis_old_port_base(adev); 215 u8 t1, t2; 216 int speed = adev->pio_mode - XFER_PIO_0; 217 218 const u8 active[] = { 0x00, 0x07, 0x04, 0x03, 0x01 }; 219 const u8 recovery[] = { 0x00, 0x06, 0x04, 0x03, 0x03 }; 220 221 sis_set_fifo(ap, adev); 222 223 pci_read_config_byte(pdev, port, &t1); 224 pci_read_config_byte(pdev, port + 1, &t2); 225 226 t1 &= ~0x0F; /* Clear active/recovery timings */ 227 t2 &= ~0x07; 228 229 t1 |= active[speed]; 230 t2 |= recovery[speed]; 231 232 pci_write_config_byte(pdev, port, t1); 233 pci_write_config_byte(pdev, port + 1, t2); 234} 235 236/** 237 * sis_100_set_pioode - Initialize host controller PATA PIO timings 238 * @ap: Port whose timings we are configuring 239 * @adev: Device we are configuring for. 240 * 241 * Set PIO mode for device, in host controller PCI config space. This 242 * function handles PIO set up for ATA100 devices and early ATA133. 243 * 244 * LOCKING: 245 * None (inherited from caller). 246 */ 247 248static void sis_100_set_piomode (struct ata_port *ap, struct ata_device *adev) 249{ 250 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 251 int port = sis_old_port_base(adev); 252 int speed = adev->pio_mode - XFER_PIO_0; 253 254 const u8 actrec[] = { 0x00, 0x67, 0x44, 0x33, 0x31 }; 255 256 sis_set_fifo(ap, adev); 257 258 pci_write_config_byte(pdev, port, actrec[speed]); 259} 260 261/** 262 * sis_133_set_pioode - Initialize host controller PATA PIO timings 263 * @ap: Port whose timings we are configuring 264 * @adev: Device we are configuring for. 265 * 266 * Set PIO mode for device, in host controller PCI config space. This 267 * function handles PIO set up for the later ATA133 devices. 268 * 269 * LOCKING: 270 * None (inherited from caller). 271 */ 272 273static void sis_133_set_piomode (struct ata_port *ap, struct ata_device *adev) 274{ 275 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 276 int port = 0x40; 277 u32 t1; 278 u32 reg54; 279 int speed = adev->pio_mode - XFER_PIO_0; 280 281 const u32 timing133[] = { 282 0x28269000, /* Recovery << 24 | Act << 16 | Ini << 12 */ 283 0x0C266000, 284 0x04263000, 285 0x0C0A3000, 286 0x05093000 287 }; 288 const u32 timing100[] = { 289 0x1E1C6000, /* Recovery << 24 | Act << 16 | Ini << 12 */ 290 0x091C4000, 291 0x031C2000, 292 0x09072000, 293 0x04062000 294 }; 295 296 sis_set_fifo(ap, adev); 297 298 /* If bit 14 is set then the registers are mapped at 0x70 not 0x40 */ 299 pci_read_config_dword(pdev, 0x54, ®54); 300 if (reg54 & 0x40000000) 301 port = 0x70; 302 port += 8 * ap->port_no + 4 * adev->devno; 303 304 pci_read_config_dword(pdev, port, &t1); 305 t1 &= 0xC0C00FFF; /* Mask out timing */ 306 307 if (t1 & 0x08) /* 100 or 133 ? */ 308 t1 |= timing133[speed]; 309 else 310 t1 |= timing100[speed]; 311 pci_write_config_byte(pdev, port, t1); 312} 313 314/** 315 * sis_old_set_dmamode - Initialize host controller PATA DMA timings 316 * @ap: Port whose timings we are configuring 317 * @adev: Device to program 318 * 319 * Set UDMA/MWDMA mode for device, in host controller PCI config space. 320 * Handles pre UDMA and UDMA33 devices. Supports MWDMA as well unlike 321 * the old ide/pci driver. 322 * 323 * LOCKING: 324 * None (inherited from caller). 325 */ 326 327static void sis_old_set_dmamode (struct ata_port *ap, struct ata_device *adev) 328{ 329 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 330 int speed = adev->dma_mode - XFER_MW_DMA_0; 331 int drive_pci = sis_old_port_base(adev); 332 u16 timing; 333 334 const u16 mwdma_bits[] = { 0x707, 0x202, 0x202 }; 335 const u16 udma_bits[] = { 0xE000, 0xC000, 0xA000 }; 336 337 pci_read_config_word(pdev, drive_pci, &timing); 338 339 if (adev->dma_mode < XFER_UDMA_0) { 340 /* bits 3-0 hold recovery timing bits 8-10 active timing and 341 the higer bits are dependant on the device */ 342 timing &= ~ 0x870F; 343 timing |= mwdma_bits[speed]; 344 pci_write_config_word(pdev, drive_pci, timing); 345 } else { 346 /* Bit 15 is UDMA on/off, bit 13-14 are cycle time */ 347 speed = adev->dma_mode - XFER_UDMA_0; 348 timing &= ~0x6000; 349 timing |= udma_bits[speed]; 350 } 351} 352 353/** 354 * sis_66_set_dmamode - Initialize host controller PATA DMA timings 355 * @ap: Port whose timings we are configuring 356 * @adev: Device to program 357 * 358 * Set UDMA/MWDMA mode for device, in host controller PCI config space. 359 * Handles UDMA66 and early UDMA100 devices. Supports MWDMA as well unlike 360 * the old ide/pci driver. 361 * 362 * LOCKING: 363 * None (inherited from caller). 364 */ 365 366static void sis_66_set_dmamode (struct ata_port *ap, struct ata_device *adev) 367{ 368 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 369 int speed = adev->dma_mode - XFER_MW_DMA_0; 370 int drive_pci = sis_old_port_base(adev); 371 u16 timing; 372 373 const u16 mwdma_bits[] = { 0x707, 0x202, 0x202 }; 374 const u16 udma_bits[] = { 0xF000, 0xD000, 0xB000, 0xA000, 0x9000}; 375 376 pci_read_config_word(pdev, drive_pci, &timing); 377 378 if (adev->dma_mode < XFER_UDMA_0) { 379 /* bits 3-0 hold recovery timing bits 8-10 active timing and 380 the higer bits are dependant on the device, bit 15 udma */ 381 timing &= ~0x870F; 382 timing |= mwdma_bits[speed]; 383 } else { 384 /* Bit 15 is UDMA on/off, bit 12-14 are cycle time */ 385 speed = adev->dma_mode - XFER_UDMA_0; 386 timing &= ~0xF000; 387 timing |= udma_bits[speed]; 388 } 389 pci_write_config_word(pdev, drive_pci, timing); 390} 391 392/** 393 * sis_100_set_dmamode - Initialize host controller PATA DMA timings 394 * @ap: Port whose timings we are configuring 395 * @adev: Device to program 396 * 397 * Set UDMA/MWDMA mode for device, in host controller PCI config space. 398 * Handles UDMA66 and early UDMA100 devices. 399 * 400 * LOCKING: 401 * None (inherited from caller). 402 */ 403 404static void sis_100_set_dmamode (struct ata_port *ap, struct ata_device *adev) 405{ 406 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 407 int speed = adev->dma_mode - XFER_MW_DMA_0; 408 int drive_pci = sis_old_port_base(adev); 409 u8 timing; 410 411 const u8 udma_bits[] = { 0x8B, 0x87, 0x85, 0x83, 0x82, 0x81}; 412 413 pci_read_config_byte(pdev, drive_pci + 1, &timing); 414 415 if (adev->dma_mode < XFER_UDMA_0) { 416 /* NOT SUPPORTED YET: NEED DATA SHEET. DITTO IN OLD DRIVER */ 417 } else { 418 /* Bit 7 is UDMA on/off, bit 0-3 are cycle time */ 419 speed = adev->dma_mode - XFER_UDMA_0; 420 timing &= ~0x8F; 421 timing |= udma_bits[speed]; 422 } 423 pci_write_config_byte(pdev, drive_pci + 1, timing); 424} 425 426/** 427 * sis_133_early_set_dmamode - Initialize host controller PATA DMA timings 428 * @ap: Port whose timings we are configuring 429 * @adev: Device to program 430 * 431 * Set UDMA/MWDMA mode for device, in host controller PCI config space. 432 * Handles early SiS 961 bridges. Supports MWDMA as well unlike 433 * the old ide/pci driver. 434 * 435 * LOCKING: 436 * None (inherited from caller). 437 */ 438 439static void sis_133_early_set_dmamode (struct ata_port *ap, struct ata_device *adev) 440{ 441 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 442 int speed = adev->dma_mode - XFER_MW_DMA_0; 443 int drive_pci = sis_old_port_base(adev); 444 u8 timing; 445 /* Low 4 bits are timing */ 446 static const u8 udma_bits[] = { 0x8F, 0x8A, 0x87, 0x85, 0x83, 0x82, 0x81}; 447 448 pci_read_config_byte(pdev, drive_pci + 1, &timing); 449 450 if (adev->dma_mode < XFER_UDMA_0) { 451 /* NOT SUPPORTED YET: NEED DATA SHEET. DITTO IN OLD DRIVER */ 452 } else { 453 /* Bit 7 is UDMA on/off, bit 0-3 are cycle time */ 454 speed = adev->dma_mode - XFER_UDMA_0; 455 timing &= ~0x8F; 456 timing |= udma_bits[speed]; 457 } 458 pci_write_config_byte(pdev, drive_pci + 1, timing); 459} 460 461/** 462 * sis_133_set_dmamode - Initialize host controller PATA DMA timings 463 * @ap: Port whose timings we are configuring 464 * @adev: Device to program 465 * 466 * Set UDMA/MWDMA mode for device, in host controller PCI config space. 467 * Handles early SiS 961 bridges. Supports MWDMA as well unlike 468 * the old ide/pci driver. 469 * 470 * LOCKING: 471 * None (inherited from caller). 472 */ 473 474static void sis_133_set_dmamode (struct ata_port *ap, struct ata_device *adev) 475{ 476 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 477 int speed = adev->dma_mode - XFER_MW_DMA_0; 478 int port = 0x40; 479 u32 t1; 480 u32 reg54; 481 482 /* bits 4- cycle time 8 - cvs time */ 483 static const u32 timing_u100[] = { 0x6B0, 0x470, 0x350, 0x140, 0x120, 0x110, 0x000 }; 484 static const u32 timing_u133[] = { 0x9F0, 0x6A0, 0x470, 0x250, 0x230, 0x220, 0x210 }; 485 486 /* If bit 14 is set then the registers are mapped at 0x70 not 0x40 */ 487 pci_read_config_dword(pdev, 0x54, ®54); 488 if (reg54 & 0x40000000) 489 port = 0x70; 490 port += (8 * ap->port_no) + (4 * adev->devno); 491 492 pci_read_config_dword(pdev, port, &t1); 493 494 if (adev->dma_mode < XFER_UDMA_0) { 495 t1 &= ~0x00000004; 496 } else { 497 speed = adev->dma_mode - XFER_UDMA_0; 498 /* if & 8 no UDMA133 - need info for ... */ 499 t1 &= ~0x00000FF0; 500 t1 |= 0x00000004; 501 if (t1 & 0x08) 502 t1 |= timing_u133[speed]; 503 else 504 t1 |= timing_u100[speed]; 505 } 506 pci_write_config_dword(pdev, port, t1); 507} 508 509static struct scsi_host_template sis_sht = { 510 .module = THIS_MODULE, 511 .name = DRV_NAME, 512 .ioctl = ata_scsi_ioctl, 513 .queuecommand = ata_scsi_queuecmd, 514 .can_queue = ATA_DEF_QUEUE, 515 .this_id = ATA_SHT_THIS_ID, 516 .sg_tablesize = LIBATA_MAX_PRD, 517 .cmd_per_lun = ATA_SHT_CMD_PER_LUN, 518 .emulated = ATA_SHT_EMULATED, 519 .use_clustering = ATA_SHT_USE_CLUSTERING, 520 .proc_name = DRV_NAME, 521 .dma_boundary = ATA_DMA_BOUNDARY, 522 .slave_configure = ata_scsi_slave_config, 523 .slave_destroy = ata_scsi_slave_destroy, 524 .bios_param = ata_std_bios_param, 525}; 526 527static const struct ata_port_operations sis_133_ops = { 528 .port_disable = ata_port_disable, 529 .set_piomode = sis_133_set_piomode, 530 .set_dmamode = sis_133_set_dmamode, 531 .mode_filter = ata_pci_default_filter, 532 533 .tf_load = ata_tf_load, 534 .tf_read = ata_tf_read, 535 .check_status = ata_check_status, 536 .exec_command = ata_exec_command, 537 .dev_select = ata_std_dev_select, 538 539 .freeze = ata_bmdma_freeze, 540 .thaw = ata_bmdma_thaw, 541 .error_handler = sis_error_handler, 542 .post_internal_cmd = ata_bmdma_post_internal_cmd, 543 .cable_detect = sis_133_cable_detect, 544 545 .bmdma_setup = ata_bmdma_setup, 546 .bmdma_start = ata_bmdma_start, 547 .bmdma_stop = ata_bmdma_stop, 548 .bmdma_status = ata_bmdma_status, 549 .qc_prep = ata_qc_prep, 550 .qc_issue = ata_qc_issue_prot, 551 .data_xfer = ata_data_xfer, 552 553 .irq_handler = ata_interrupt, 554 .irq_clear = ata_bmdma_irq_clear, 555 .irq_on = ata_irq_on, 556 .irq_ack = ata_irq_ack, 557 558 .port_start = ata_port_start, 559}; 560 561static const struct ata_port_operations sis_133_for_sata_ops = { 562 .port_disable = ata_port_disable, 563 .set_piomode = sis_133_set_piomode, 564 .set_dmamode = sis_133_set_dmamode, 565 .mode_filter = ata_pci_default_filter, 566 567 .tf_load = ata_tf_load, 568 .tf_read = ata_tf_read, 569 .check_status = ata_check_status, 570 .exec_command = ata_exec_command, 571 .dev_select = ata_std_dev_select, 572 573 .freeze = ata_bmdma_freeze, 574 .thaw = ata_bmdma_thaw, 575 .error_handler = ata_bmdma_error_handler, 576 .post_internal_cmd = ata_bmdma_post_internal_cmd, 577 .cable_detect = sis_133_cable_detect, 578 579 .bmdma_setup = ata_bmdma_setup, 580 .bmdma_start = ata_bmdma_start, 581 .bmdma_stop = ata_bmdma_stop, 582 .bmdma_status = ata_bmdma_status, 583 .qc_prep = ata_qc_prep, 584 .qc_issue = ata_qc_issue_prot, 585 .data_xfer = ata_data_xfer, 586 587 .irq_handler = ata_interrupt, 588 .irq_clear = ata_bmdma_irq_clear, 589 .irq_on = ata_irq_on, 590 .irq_ack = ata_irq_ack, 591 592 .port_start = ata_port_start, 593}; 594 595static const struct ata_port_operations sis_133_early_ops = { 596 .port_disable = ata_port_disable, 597 .set_piomode = sis_100_set_piomode, 598 .set_dmamode = sis_133_early_set_dmamode, 599 .mode_filter = ata_pci_default_filter, 600 601 .tf_load = ata_tf_load, 602 .tf_read = ata_tf_read, 603 .check_status = ata_check_status, 604 .exec_command = ata_exec_command, 605 .dev_select = ata_std_dev_select, 606 607 .freeze = ata_bmdma_freeze, 608 .thaw = ata_bmdma_thaw, 609 .error_handler = sis_error_handler, 610 .post_internal_cmd = ata_bmdma_post_internal_cmd, 611 .cable_detect = sis_66_cable_detect, 612 613 .bmdma_setup = ata_bmdma_setup, 614 .bmdma_start = ata_bmdma_start, 615 .bmdma_stop = ata_bmdma_stop, 616 .bmdma_status = ata_bmdma_status, 617 .qc_prep = ata_qc_prep, 618 .qc_issue = ata_qc_issue_prot, 619 .data_xfer = ata_data_xfer, 620 621 .irq_handler = ata_interrupt, 622 .irq_clear = ata_bmdma_irq_clear, 623 .irq_on = ata_irq_on, 624 .irq_ack = ata_irq_ack, 625 626 .port_start = ata_port_start, 627}; 628 629static const struct ata_port_operations sis_100_ops = { 630 .port_disable = ata_port_disable, 631 .set_piomode = sis_100_set_piomode, 632 .set_dmamode = sis_100_set_dmamode, 633 .mode_filter = ata_pci_default_filter, 634 635 .tf_load = ata_tf_load, 636 .tf_read = ata_tf_read, 637 .check_status = ata_check_status, 638 .exec_command = ata_exec_command, 639 .dev_select = ata_std_dev_select, 640 641 .freeze = ata_bmdma_freeze, 642 .thaw = ata_bmdma_thaw, 643 .error_handler = sis_error_handler, 644 .post_internal_cmd = ata_bmdma_post_internal_cmd, 645 .cable_detect = sis_66_cable_detect, 646 647 .bmdma_setup = ata_bmdma_setup, 648 .bmdma_start = ata_bmdma_start, 649 .bmdma_stop = ata_bmdma_stop, 650 .bmdma_status = ata_bmdma_status, 651 .qc_prep = ata_qc_prep, 652 .qc_issue = ata_qc_issue_prot, 653 .data_xfer = ata_data_xfer, 654 655 .irq_handler = ata_interrupt, 656 .irq_clear = ata_bmdma_irq_clear, 657 .irq_on = ata_irq_on, 658 .irq_ack = ata_irq_ack, 659 660 .port_start = ata_port_start, 661}; 662 663static const struct ata_port_operations sis_66_ops = { 664 .port_disable = ata_port_disable, 665 .set_piomode = sis_old_set_piomode, 666 .set_dmamode = sis_66_set_dmamode, 667 .mode_filter = ata_pci_default_filter, 668 669 .tf_load = ata_tf_load, 670 .tf_read = ata_tf_read, 671 .check_status = ata_check_status, 672 .exec_command = ata_exec_command, 673 .dev_select = ata_std_dev_select, 674 .cable_detect = sis_66_cable_detect, 675 676 .freeze = ata_bmdma_freeze, 677 .thaw = ata_bmdma_thaw, 678 .error_handler = sis_error_handler, 679 .post_internal_cmd = ata_bmdma_post_internal_cmd, 680 681 .bmdma_setup = ata_bmdma_setup, 682 .bmdma_start = ata_bmdma_start, 683 .bmdma_stop = ata_bmdma_stop, 684 .bmdma_status = ata_bmdma_status, 685 .qc_prep = ata_qc_prep, 686 .qc_issue = ata_qc_issue_prot, 687 .data_xfer = ata_data_xfer, 688 689 .irq_handler = ata_interrupt, 690 .irq_clear = ata_bmdma_irq_clear, 691 .irq_on = ata_irq_on, 692 .irq_ack = ata_irq_ack, 693 694 .port_start = ata_port_start, 695}; 696 697static const struct ata_port_operations sis_old_ops = { 698 .port_disable = ata_port_disable, 699 .set_piomode = sis_old_set_piomode, 700 .set_dmamode = sis_old_set_dmamode, 701 .mode_filter = ata_pci_default_filter, 702 703 .tf_load = ata_tf_load, 704 .tf_read = ata_tf_read, 705 .check_status = ata_check_status, 706 .exec_command = ata_exec_command, 707 .dev_select = ata_std_dev_select, 708 709 .freeze = ata_bmdma_freeze, 710 .thaw = ata_bmdma_thaw, 711 .error_handler = sis_error_handler, 712 .post_internal_cmd = ata_bmdma_post_internal_cmd, 713 .cable_detect = ata_cable_40wire, 714 715 .bmdma_setup = ata_bmdma_setup, 716 .bmdma_start = ata_bmdma_start, 717 .bmdma_stop = ata_bmdma_stop, 718 .bmdma_status = ata_bmdma_status, 719 .qc_prep = ata_qc_prep, 720 .qc_issue = ata_qc_issue_prot, 721 .data_xfer = ata_data_xfer, 722 723 .irq_handler = ata_interrupt, 724 .irq_clear = ata_bmdma_irq_clear, 725 .irq_on = ata_irq_on, 726 .irq_ack = ata_irq_ack, 727 728 .port_start = ata_port_start, 729}; 730 731static const struct ata_port_info sis_info = { 732 .sht = &sis_sht, 733 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST, 734 .pio_mask = 0x1f, /* pio0-4 */ 735 .mwdma_mask = 0x07, 736 .udma_mask = 0, 737 .port_ops = &sis_old_ops, 738}; 739static const struct ata_port_info sis_info33 = { 740 .sht = &sis_sht, 741 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST, 742 .pio_mask = 0x1f, /* pio0-4 */ 743 .mwdma_mask = 0x07, 744 .udma_mask = ATA_UDMA2, /* UDMA 33 */ 745 .port_ops = &sis_old_ops, 746}; 747static const struct ata_port_info sis_info66 = { 748 .sht = &sis_sht, 749 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST, 750 .pio_mask = 0x1f, /* pio0-4 */ 751 .udma_mask = ATA_UDMA4, /* UDMA 66 */ 752 .port_ops = &sis_66_ops, 753}; 754static const struct ata_port_info sis_info100 = { 755 .sht = &sis_sht, 756 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST, 757 .pio_mask = 0x1f, /* pio0-4 */ 758 .udma_mask = ATA_UDMA5, 759 .port_ops = &sis_100_ops, 760}; 761static const struct ata_port_info sis_info100_early = { 762 .sht = &sis_sht, 763 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST, 764 .udma_mask = ATA_UDMA5, 765 .pio_mask = 0x1f, /* pio0-4 */ 766 .port_ops = &sis_66_ops, 767}; 768static const struct ata_port_info sis_info133 = { 769 .sht = &sis_sht, 770 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST, 771 .pio_mask = 0x1f, /* pio0-4 */ 772 .udma_mask = ATA_UDMA6, 773 .port_ops = &sis_133_ops, 774}; 775const struct ata_port_info sis_info133_for_sata = { 776 .sht = &sis_sht, 777 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST, 778 .pio_mask = 0x1f, /* pio0-4 */ 779 .udma_mask = ATA_UDMA6, 780 .port_ops = &sis_133_for_sata_ops, 781}; 782static const struct ata_port_info sis_info133_early = { 783 .sht = &sis_sht, 784 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST, 785 .pio_mask = 0x1f, /* pio0-4 */ 786 .udma_mask = ATA_UDMA6, 787 .port_ops = &sis_133_early_ops, 788}; 789 790/* Privately shared with the SiS180 SATA driver, not for use elsewhere */ 791EXPORT_SYMBOL_GPL(sis_info133_for_sata); 792 793static void sis_fixup(struct pci_dev *pdev, struct sis_chipset *sis) 794{ 795 u16 regw; 796 u8 reg; 797 798 if (sis->info == &sis_info133) { 799 pci_read_config_word(pdev, 0x50, ®w); 800 if (regw & 0x08) 801 pci_write_config_word(pdev, 0x50, regw & ~0x08); 802 pci_read_config_word(pdev, 0x52, ®w); 803 if (regw & 0x08) 804 pci_write_config_word(pdev, 0x52, regw & ~0x08); 805 return; 806 } 807 808 if (sis->info == &sis_info133_early || sis->info == &sis_info100) { 809 /* Fix up latency */ 810 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x80); 811 /* Set compatibility bit */ 812 pci_read_config_byte(pdev, 0x49, ®); 813 if (!(reg & 0x01)) 814 pci_write_config_byte(pdev, 0x49, reg | 0x01); 815 return; 816 } 817 818 if (sis->info == &sis_info66 || sis->info == &sis_info100_early) { 819 /* Fix up latency */ 820 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x80); 821 /* Set compatibility bit */ 822 pci_read_config_byte(pdev, 0x52, ®); 823 if (!(reg & 0x04)) 824 pci_write_config_byte(pdev, 0x52, reg | 0x04); 825 return; 826 } 827 828 if (sis->info == &sis_info33) { 829 pci_read_config_byte(pdev, PCI_CLASS_PROG, ®); 830 if (( reg & 0x0F ) != 0x00) 831 pci_write_config_byte(pdev, PCI_CLASS_PROG, reg & 0xF0); 832 /* Fall through to ATA16 fixup below */ 833 } 834 835 if (sis->info == &sis_info || sis->info == &sis_info33) { 836 /* force per drive recovery and active timings 837 needed on ATA_33 and below chips */ 838 pci_read_config_byte(pdev, 0x52, ®); 839 if (!(reg & 0x08)) 840 pci_write_config_byte(pdev, 0x52, reg|0x08); 841 return; 842 } 843 844 BUG(); 845} 846 847/** 848 * sis_init_one - Register SiS ATA PCI device with kernel services 849 * @pdev: PCI device to register 850 * @ent: Entry in sis_pci_tbl matching with @pdev 851 * 852 * Called from kernel PCI layer. We probe for combined mode (sigh), 853 * and then hand over control to libata, for it to do the rest. 854 * 855 * LOCKING: 856 * Inherited from PCI layer (may sleep). 857 * 858 * RETURNS: 859 * Zero on success, or -ERRNO value. 860 */ 861 862static int sis_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) 863{ 864 static int printed_version; 865 struct ata_port_info port; 866 const struct ata_port_info *ppi[] = { &port, NULL }; 867 struct pci_dev *host = NULL; 868 struct sis_chipset *chipset = NULL; 869 struct sis_chipset *sets; 870 871 static struct sis_chipset sis_chipsets[] = { 872 873 { 0x0968, &sis_info133 }, 874 { 0x0966, &sis_info133 }, 875 { 0x0965, &sis_info133 }, 876 { 0x0745, &sis_info100 }, 877 { 0x0735, &sis_info100 }, 878 { 0x0733, &sis_info100 }, 879 { 0x0635, &sis_info100 }, 880 { 0x0633, &sis_info100 }, 881 882 { 0x0730, &sis_info100_early }, /* 100 with ATA 66 layout */ 883 { 0x0550, &sis_info100_early }, /* 100 with ATA 66 layout */ 884 885 { 0x0640, &sis_info66 }, 886 { 0x0630, &sis_info66 }, 887 { 0x0620, &sis_info66 }, 888 { 0x0540, &sis_info66 }, 889 { 0x0530, &sis_info66 }, 890 891 { 0x5600, &sis_info33 }, 892 { 0x5598, &sis_info33 }, 893 { 0x5597, &sis_info33 }, 894 { 0x5591, &sis_info33 }, 895 { 0x5582, &sis_info33 }, 896 { 0x5581, &sis_info33 }, 897 898 { 0x5596, &sis_info }, 899 { 0x5571, &sis_info }, 900 { 0x5517, &sis_info }, 901 { 0x5511, &sis_info }, 902 903 {0} 904 }; 905 static struct sis_chipset sis133_early = { 906 0x0, &sis_info133_early 907 }; 908 static struct sis_chipset sis133 = { 909 0x0, &sis_info133 910 }; 911 static struct sis_chipset sis100_early = { 912 0x0, &sis_info100_early 913 }; 914 static struct sis_chipset sis100 = { 915 0x0, &sis_info100 916 }; 917 918 if (!printed_version++) 919 dev_printk(KERN_DEBUG, &pdev->dev, 920 "version " DRV_VERSION "\n"); 921 922 /* We have to find the bridge first */ 923 924 for (sets = &sis_chipsets[0]; sets->device; sets++) { 925 host = pci_get_device(PCI_VENDOR_ID_SI, sets->device, NULL); 926 if (host != NULL) { 927 chipset = sets; /* Match found */ 928 if (sets->device == 0x630) { /* SIS630 */ 929 u8 host_rev; 930 pci_read_config_byte(host, PCI_REVISION_ID, &host_rev); 931 if (host_rev >= 0x30) /* 630 ET */ 932 chipset = &sis100_early; 933 } 934 break; 935 } 936 } 937 938 /* Look for concealed bridges */ 939 if (chipset == NULL) { 940 /* Second check */ 941 u32 idemisc; 942 u16 trueid; 943 944 /* Disable ID masking and register remapping then 945 see what the real ID is */ 946 947 pci_read_config_dword(pdev, 0x54, &idemisc); 948 pci_write_config_dword(pdev, 0x54, idemisc & 0x7fffffff); 949 pci_read_config_word(pdev, PCI_DEVICE_ID, &trueid); 950 pci_write_config_dword(pdev, 0x54, idemisc); 951 952 switch(trueid) { 953 case 0x5518: /* SIS 962/963 */ 954 chipset = &sis133; 955 if ((idemisc & 0x40000000) == 0) { 956 pci_write_config_dword(pdev, 0x54, idemisc | 0x40000000); 957 printk(KERN_INFO "SIS5513: Switching to 5513 register mapping\n"); 958 } 959 break; 960 case 0x0180: /* SIS 965/965L */ 961 chipset = &sis133; 962 break; 963 case 0x1180: /* SIS 966/966L */ 964 chipset = &sis133; 965 break; 966 } 967 } 968 969 /* Further check */ 970 if (chipset == NULL) { 971 struct pci_dev *lpc_bridge; 972 u16 trueid; 973 u8 prefctl; 974 u8 idecfg; 975 u8 sbrev; 976 977 /* Try the second unmasking technique */ 978 pci_read_config_byte(pdev, 0x4a, &idecfg); 979 pci_write_config_byte(pdev, 0x4a, idecfg | 0x10); 980 pci_read_config_word(pdev, PCI_DEVICE_ID, &trueid); 981 pci_write_config_byte(pdev, 0x4a, idecfg); 982 983 switch(trueid) { 984 case 0x5517: 985 lpc_bridge = pci_get_slot(pdev->bus, 0x10); /* Bus 0 Dev 2 Fn 0 */ 986 if (lpc_bridge == NULL) 987 break; 988 pci_read_config_byte(lpc_bridge, PCI_REVISION_ID, &sbrev); 989 pci_read_config_byte(pdev, 0x49, &prefctl); 990 pci_dev_put(lpc_bridge); 991 992 if (sbrev == 0x10 && (prefctl & 0x80)) { 993 chipset = &sis133_early; 994 break; 995 } 996 chipset = &sis100; 997 break; 998 } 999 } 1000 pci_dev_put(host); 1001 1002 /* No chipset info, no support */ 1003 if (chipset == NULL) 1004 return -ENODEV; 1005 1006 port = *chipset->info; 1007 port.private_data = chipset; 1008 1009 sis_fixup(pdev, chipset); 1010 1011 return ata_pci_init_one(pdev, ppi); 1012} 1013 1014static const struct pci_device_id sis_pci_tbl[] = { 1015 { PCI_VDEVICE(SI, 0x5513), }, /* SiS 5513 */ 1016 { PCI_VDEVICE(SI, 0x5518), }, /* SiS 5518 */ 1017 { PCI_VDEVICE(SI, 0x1180), }, /* SiS 1180 */ 1018 1019 { } 1020}; 1021 1022static struct pci_driver sis_pci_driver = { 1023 .name = DRV_NAME, 1024 .id_table = sis_pci_tbl, 1025 .probe = sis_init_one, 1026 .remove = ata_pci_remove_one, 1027#ifdef CONFIG_PM 1028 .suspend = ata_pci_device_suspend, 1029 .resume = ata_pci_device_resume, 1030#endif 1031}; 1032 1033static int __init sis_init(void) 1034{ 1035 return pci_register_driver(&sis_pci_driver); 1036} 1037 1038static void __exit sis_exit(void) 1039{ 1040 pci_unregister_driver(&sis_pci_driver); 1041} 1042 1043module_init(sis_init); 1044module_exit(sis_exit); 1045 1046MODULE_AUTHOR("Alan Cox"); 1047MODULE_DESCRIPTION("SCSI low-level driver for SiS ATA"); 1048MODULE_LICENSE("GPL"); 1049MODULE_DEVICE_TABLE(pci, sis_pci_tbl); 1050MODULE_VERSION(DRV_VERSION); 1051