1/* pci_fire.c: Sun4u platform PCI-E controller support. 2 * 3 * Copyright (C) 2007 David S. Miller (davem@davemloft.net) 4 */ 5#include <linux/kernel.h> 6#include <linux/pci.h> 7#include <linux/slab.h> 8#include <linux/init.h> 9 10#include <asm/oplib.h> 11#include <asm/prom.h> 12 13#include "pci_impl.h" 14 15#define fire_read(__reg) \ 16({ u64 __ret; \ 17 __asm__ __volatile__("ldxa [%1] %2, %0" \ 18 : "=r" (__ret) \ 19 : "r" (__reg), "i" (ASI_PHYS_BYPASS_EC_E) \ 20 : "memory"); \ 21 __ret; \ 22}) 23#define fire_write(__reg, __val) \ 24 __asm__ __volatile__("stxa %0, [%1] %2" \ 25 : /* no outputs */ \ 26 : "r" (__val), "r" (__reg), \ 27 "i" (ASI_PHYS_BYPASS_EC_E) \ 28 : "memory") 29 30static void pci_fire_scan_bus(struct pci_pbm_info *pbm) 31{ 32 pbm->pci_bus = pci_scan_one_pbm(pbm); 33 34} 35 36#define FIRE_IOMMU_CONTROL 0x40000UL 37#define FIRE_IOMMU_TSBBASE 0x40008UL 38#define FIRE_IOMMU_FLUSH 0x40100UL 39#define FIRE_IOMMU_FLUSHINV 0x40108UL 40 41static void pci_fire_pbm_iommu_init(struct pci_pbm_info *pbm) 42{ 43 struct iommu *iommu = pbm->iommu; 44 u32 vdma[2], dma_mask; 45 u64 control; 46 int tsbsize; 47 48 /* No virtual-dma property on these guys, use largest size. */ 49 vdma[0] = 0xc0000000; /* base */ 50 vdma[1] = 0x40000000; /* size */ 51 dma_mask = 0xffffffff; 52 tsbsize = 128; 53 54 /* Register addresses. */ 55 iommu->iommu_control = pbm->pbm_regs + FIRE_IOMMU_CONTROL; 56 iommu->iommu_tsbbase = pbm->pbm_regs + FIRE_IOMMU_TSBBASE; 57 iommu->iommu_flush = pbm->pbm_regs + FIRE_IOMMU_FLUSH; 58 iommu->iommu_flushinv = pbm->pbm_regs + FIRE_IOMMU_FLUSHINV; 59 60 /* We use the main control/status register of FIRE as the write 61 * completion register. 62 */ 63 iommu->write_complete_reg = pbm->controller_regs + 0x410000UL; 64 65 /* 66 * Invalidate TLB Entries. 67 */ 68 fire_write(iommu->iommu_flushinv, ~(u64)0); 69 70 pci_iommu_table_init(iommu, tsbsize * 8 * 1024, vdma[0], dma_mask); 71 72 fire_write(iommu->iommu_tsbbase, __pa(iommu->page_table) | 0x7UL); 73 74 control = fire_read(iommu->iommu_control); 75 control |= (0x00000400 /* TSB cache snoop enable */ | 76 0x00000300 /* Cache mode */ | 77 0x00000002 /* Bypass enable */ | 78 0x00000001 /* Translation enable */); 79 fire_write(iommu->iommu_control, control); 80} 81 82/* Based at pbm->controller_regs */ 83#define FIRE_PARITY_CONTROL 0x470010UL 84#define FIRE_PARITY_ENAB 0x8000000000000000UL 85#define FIRE_FATAL_RESET_CTL 0x471028UL 86#define FIRE_FATAL_RESET_SPARE 0x0000000004000000UL 87#define FIRE_FATAL_RESET_MB 0x0000000002000000UL 88#define FIRE_FATAL_RESET_CPE 0x0000000000008000UL 89#define FIRE_FATAL_RESET_APE 0x0000000000004000UL 90#define FIRE_FATAL_RESET_PIO 0x0000000000000040UL 91#define FIRE_FATAL_RESET_JW 0x0000000000000004UL 92#define FIRE_FATAL_RESET_JI 0x0000000000000002UL 93#define FIRE_FATAL_RESET_JR 0x0000000000000001UL 94#define FIRE_CORE_INTR_ENABLE 0x471800UL 95 96/* Based at pbm->pbm_regs */ 97#define FIRE_TLU_CTRL 0x80000UL 98#define FIRE_TLU_CTRL_TIM 0x00000000da000000UL 99#define FIRE_TLU_CTRL_QDET 0x0000000000000100UL 100#define FIRE_TLU_CTRL_CFG 0x0000000000000001UL 101#define FIRE_TLU_DEV_CTRL 0x90008UL 102#define FIRE_TLU_LINK_CTRL 0x90020UL 103#define FIRE_TLU_LINK_CTRL_CLK 0x0000000000000040UL 104#define FIRE_LPU_RESET 0xe2008UL 105#define FIRE_LPU_LLCFG 0xe2200UL 106#define FIRE_LPU_LLCFG_VC0 0x0000000000000100UL 107#define FIRE_LPU_FCTRL_UCTRL 0xe2240UL 108#define FIRE_LPU_FCTRL_UCTRL_N 0x0000000000000002UL 109#define FIRE_LPU_FCTRL_UCTRL_P 0x0000000000000001UL 110#define FIRE_LPU_TXL_FIFOP 0xe2430UL 111#define FIRE_LPU_LTSSM_CFG2 0xe2788UL 112#define FIRE_LPU_LTSSM_CFG3 0xe2790UL 113#define FIRE_LPU_LTSSM_CFG4 0xe2798UL 114#define FIRE_LPU_LTSSM_CFG5 0xe27a0UL 115#define FIRE_DMC_IENAB 0x31800UL 116#define FIRE_DMC_DBG_SEL_A 0x53000UL 117#define FIRE_DMC_DBG_SEL_B 0x53008UL 118#define FIRE_PEC_IENAB 0x51800UL 119 120static void pci_fire_hw_init(struct pci_pbm_info *pbm) 121{ 122 u64 val; 123 124 fire_write(pbm->controller_regs + FIRE_PARITY_CONTROL, 125 FIRE_PARITY_ENAB); 126 127 fire_write(pbm->controller_regs + FIRE_FATAL_RESET_CTL, 128 (FIRE_FATAL_RESET_SPARE | 129 FIRE_FATAL_RESET_MB | 130 FIRE_FATAL_RESET_CPE | 131 FIRE_FATAL_RESET_APE | 132 FIRE_FATAL_RESET_PIO | 133 FIRE_FATAL_RESET_JW | 134 FIRE_FATAL_RESET_JI | 135 FIRE_FATAL_RESET_JR)); 136 137 fire_write(pbm->controller_regs + FIRE_CORE_INTR_ENABLE, ~(u64)0); 138 139 val = fire_read(pbm->pbm_regs + FIRE_TLU_CTRL); 140 val |= (FIRE_TLU_CTRL_TIM | 141 FIRE_TLU_CTRL_QDET | 142 FIRE_TLU_CTRL_CFG); 143 fire_write(pbm->pbm_regs + FIRE_TLU_CTRL, val); 144 fire_write(pbm->pbm_regs + FIRE_TLU_DEV_CTRL, 0); 145 fire_write(pbm->pbm_regs + FIRE_TLU_LINK_CTRL, 146 FIRE_TLU_LINK_CTRL_CLK); 147 148 fire_write(pbm->pbm_regs + FIRE_LPU_RESET, 0); 149 fire_write(pbm->pbm_regs + FIRE_LPU_LLCFG, 150 FIRE_LPU_LLCFG_VC0); 151 fire_write(pbm->pbm_regs + FIRE_LPU_FCTRL_UCTRL, 152 (FIRE_LPU_FCTRL_UCTRL_N | 153 FIRE_LPU_FCTRL_UCTRL_P)); 154 fire_write(pbm->pbm_regs + FIRE_LPU_TXL_FIFOP, 155 ((0xffff << 16) | (0x0000 << 0))); 156 fire_write(pbm->pbm_regs + FIRE_LPU_LTSSM_CFG2, 3000000); 157 fire_write(pbm->pbm_regs + FIRE_LPU_LTSSM_CFG3, 500000); 158 fire_write(pbm->pbm_regs + FIRE_LPU_LTSSM_CFG4, 159 (2 << 16) | (140 << 8)); 160 fire_write(pbm->pbm_regs + FIRE_LPU_LTSSM_CFG5, 0); 161 162 fire_write(pbm->pbm_regs + FIRE_DMC_IENAB, ~(u64)0); 163 fire_write(pbm->pbm_regs + FIRE_DMC_DBG_SEL_A, 0); 164 fire_write(pbm->pbm_regs + FIRE_DMC_DBG_SEL_B, 0); 165 166 fire_write(pbm->pbm_regs + FIRE_PEC_IENAB, ~(u64)0); 167} 168 169static void pci_fire_pbm_init(struct pci_controller_info *p, 170 struct device_node *dp, u32 portid) 171{ 172 const struct linux_prom64_registers *regs; 173 struct pci_pbm_info *pbm; 174 175 if ((portid & 1) == 0) 176 pbm = &p->pbm_A; 177 else 178 pbm = &p->pbm_B; 179 180 pbm->next = pci_pbm_root; 181 pci_pbm_root = pbm; 182 183 pbm->scan_bus = pci_fire_scan_bus; 184 pbm->pci_ops = &sun4u_pci_ops; 185 pbm->config_space_reg_bits = 12; 186 187 pbm->index = pci_num_pbms++; 188 189 pbm->portid = portid; 190 pbm->parent = p; 191 pbm->prom_node = dp; 192 pbm->name = dp->full_name; 193 194 regs = of_get_property(dp, "reg", NULL); 195 pbm->pbm_regs = regs[0].phys_addr; 196 pbm->controller_regs = regs[1].phys_addr - 0x410000UL; 197 198 printk("%s: SUN4U PCIE Bus Module\n", pbm->name); 199 200 pci_determine_mem_io_space(pbm); 201 202 pci_get_pbm_props(pbm); 203 204 pci_fire_hw_init(pbm); 205 pci_fire_pbm_iommu_init(pbm); 206} 207 208static inline int portid_compare(u32 x, u32 y) 209{ 210 if (x == (y ^ 1)) 211 return 1; 212 return 0; 213} 214 215void fire_pci_init(struct device_node *dp, const char *model_name) 216{ 217 struct pci_controller_info *p; 218 u32 portid = of_getintprop_default(dp, "portid", 0xff); 219 struct iommu *iommu; 220 struct pci_pbm_info *pbm; 221 222 for (pbm = pci_pbm_root; pbm; pbm = pbm->next) { 223 if (portid_compare(pbm->portid, portid)) { 224 pci_fire_pbm_init(pbm->parent, dp, portid); 225 return; 226 } 227 } 228 229 p = kzalloc(sizeof(struct pci_controller_info), GFP_ATOMIC); 230 if (!p) 231 goto fatal_memory_error; 232 233 iommu = kzalloc(sizeof(struct iommu), GFP_ATOMIC); 234 if (!iommu) 235 goto fatal_memory_error; 236 237 p->pbm_A.iommu = iommu; 238 239 iommu = kzalloc(sizeof(struct iommu), GFP_ATOMIC); 240 if (!iommu) 241 goto fatal_memory_error; 242 243 p->pbm_B.iommu = iommu; 244 245 246 /* Like PSYCHO and SCHIZO we have a 2GB aligned area 247 * for memory space. 248 */ 249 pci_memspace_mask = 0x7fffffffUL; 250 251 pci_fire_pbm_init(p, dp, portid); 252 return; 253 254fatal_memory_error: 255 prom_printf("PCI_FIRE: Fatal memory allocation error.\n"); 256 prom_halt(); 257} 258