1/* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * arch/sh64/kernel/time.c 7 * 8 * Copyright (C) 2000, 2001 Paolo Alberelli 9 * Copyright (C) 2003, 2004 Paul Mundt 10 * Copyright (C) 2003 Richard Curnow 11 * 12 * Original TMU/RTC code taken from sh version. 13 * Copyright (C) 1999 Tetsuya Okada & Niibe Yutaka 14 * Some code taken from i386 version. 15 * Copyright (C) 1991, 1992, 1995 Linus Torvalds 16 */ 17 18#include <linux/errno.h> 19#include <linux/rwsem.h> 20#include <linux/sched.h> 21#include <linux/kernel.h> 22#include <linux/param.h> 23#include <linux/string.h> 24#include <linux/mm.h> 25#include <linux/interrupt.h> 26#include <linux/time.h> 27#include <linux/delay.h> 28#include <linux/init.h> 29#include <linux/profile.h> 30#include <linux/smp.h> 31#include <linux/module.h> 32#include <linux/bcd.h> 33 34#include <asm/registers.h> /* required by inline __asm__ stmt. */ 35 36#include <asm/processor.h> 37#include <asm/uaccess.h> 38#include <asm/io.h> 39#include <asm/irq.h> 40#include <asm/delay.h> 41 42#include <linux/timex.h> 43#include <linux/irq.h> 44#include <asm/hardware.h> 45 46#define TMU_TOCR_INIT 0x00 47#define TMU0_TCR_INIT 0x0020 48#define TMU_TSTR_INIT 1 49#define TMU_TSTR_OFF 0 50 51/* RCR1 Bits */ 52#define RCR1_CF 0x80 /* Carry Flag */ 53#define RCR1_CIE 0x10 /* Carry Interrupt Enable */ 54#define RCR1_AIE 0x08 /* Alarm Interrupt Enable */ 55#define RCR1_AF 0x01 /* Alarm Flag */ 56 57/* RCR2 Bits */ 58#define RCR2_PEF 0x80 /* PEriodic interrupt Flag */ 59#define RCR2_PESMASK 0x70 /* Periodic interrupt Set */ 60#define RCR2_RTCEN 0x08 /* ENable RTC */ 61#define RCR2_ADJ 0x04 /* ADJustment (30-second) */ 62#define RCR2_RESET 0x02 /* Reset bit */ 63#define RCR2_START 0x01 /* Start bit */ 64 65/* Clock, Power and Reset Controller */ 66#define CPRC_BLOCK_OFF 0x01010000 67#define CPRC_BASE PHYS_PERIPHERAL_BLOCK + CPRC_BLOCK_OFF 68 69#define FRQCR (cprc_base+0x0) 70#define WTCSR (cprc_base+0x0018) 71#define STBCR (cprc_base+0x0030) 72 73/* Time Management Unit */ 74#define TMU_BLOCK_OFF 0x01020000 75#define TMU_BASE PHYS_PERIPHERAL_BLOCK + TMU_BLOCK_OFF 76#define TMU0_BASE tmu_base + 0x8 + (0xc * 0x0) 77#define TMU1_BASE tmu_base + 0x8 + (0xc * 0x1) 78#define TMU2_BASE tmu_base + 0x8 + (0xc * 0x2) 79 80#define TMU_TOCR tmu_base+0x0 /* Byte access */ 81#define TMU_TSTR tmu_base+0x4 /* Byte access */ 82 83#define TMU0_TCOR TMU0_BASE+0x0 /* Long access */ 84#define TMU0_TCNT TMU0_BASE+0x4 /* Long access */ 85#define TMU0_TCR TMU0_BASE+0x8 /* Word access */ 86 87/* Real Time Clock */ 88#define RTC_BLOCK_OFF 0x01040000 89#define RTC_BASE PHYS_PERIPHERAL_BLOCK + RTC_BLOCK_OFF 90 91#define R64CNT rtc_base+0x00 92#define RSECCNT rtc_base+0x04 93#define RMINCNT rtc_base+0x08 94#define RHRCNT rtc_base+0x0c 95#define RWKCNT rtc_base+0x10 96#define RDAYCNT rtc_base+0x14 97#define RMONCNT rtc_base+0x18 98#define RYRCNT rtc_base+0x1c /* 16bit */ 99#define RSECAR rtc_base+0x20 100#define RMINAR rtc_base+0x24 101#define RHRAR rtc_base+0x28 102#define RWKAR rtc_base+0x2c 103#define RDAYAR rtc_base+0x30 104#define RMONAR rtc_base+0x34 105#define RCR1 rtc_base+0x38 106#define RCR2 rtc_base+0x3c 107 108#define TICK_SIZE (tick_nsec / 1000) 109 110static unsigned long tmu_base, rtc_base; 111unsigned long cprc_base; 112 113/* Variables to allow interpolation of time of day to resolution better than a 114 * jiffy. */ 115 116/* This is effectively protected by xtime_lock */ 117static unsigned long ctc_last_interrupt; 118static unsigned long long usecs_per_jiffy = 1000000/HZ; /* Approximation */ 119 120#define CTC_JIFFY_SCALE_SHIFT 40 121 122/* 2**CTC_JIFFY_SCALE_SHIFT / ctc_ticks_per_jiffy */ 123static unsigned long long scaled_recip_ctc_ticks_per_jiffy; 124 125 126static unsigned long usecs_since_tick(void) 127{ 128 unsigned long long current_ctc; 129 long ctc_ticks_since_interrupt; 130 unsigned long long ull_ctc_ticks_since_interrupt; 131 unsigned long result; 132 133 unsigned long long mul1_out; 134 unsigned long long mul1_out_high; 135 unsigned long long mul2_out_low, mul2_out_high; 136 137 /* Read CTC register */ 138 asm ("getcon cr62, %0" : "=r" (current_ctc)); 139 /* Note, the CTC counts down on each CPU clock, not up. 140 Note(2), use long type to get correct wraparound arithmetic when 141 the counter crosses zero. */ 142 ctc_ticks_since_interrupt = (long) ctc_last_interrupt - (long) current_ctc; 143 ull_ctc_ticks_since_interrupt = (unsigned long long) ctc_ticks_since_interrupt; 144 145 /* Inline assembly to do 32x32x32->64 multiplier */ 146 asm volatile ("mulu.l %1, %2, %0" : 147 "=r" (mul1_out) : 148 "r" (ull_ctc_ticks_since_interrupt), "r" (usecs_per_jiffy)); 149 150 mul1_out_high = mul1_out >> 32; 151 152 asm volatile ("mulu.l %1, %2, %0" : 153 "=r" (mul2_out_low) : 154 "r" (mul1_out), "r" (scaled_recip_ctc_ticks_per_jiffy)); 155 156 asm volatile ("mulu.l %1, %2, %0" : 157 "=r" (mul2_out_high) : 158 "r" (mul1_out_high), "r" (scaled_recip_ctc_ticks_per_jiffy)); 159 160 result = (unsigned long) (((mul2_out_high << 32) + mul2_out_low) >> CTC_JIFFY_SCALE_SHIFT); 161 162 return result; 163} 164 165void do_gettimeofday(struct timeval *tv) 166{ 167 unsigned long flags; 168 unsigned long seq; 169 unsigned long usec, sec; 170 171 do { 172 seq = read_seqbegin_irqsave(&xtime_lock, flags); 173 usec = usecs_since_tick(); 174 sec = xtime.tv_sec; 175 usec += xtime.tv_nsec / 1000; 176 } while (read_seqretry_irqrestore(&xtime_lock, seq, flags)); 177 178 while (usec >= 1000000) { 179 usec -= 1000000; 180 sec++; 181 } 182 183 tv->tv_sec = sec; 184 tv->tv_usec = usec; 185} 186 187int do_settimeofday(struct timespec *tv) 188{ 189 time_t wtm_sec, sec = tv->tv_sec; 190 long wtm_nsec, nsec = tv->tv_nsec; 191 192 if ((unsigned long)tv->tv_nsec >= NSEC_PER_SEC) 193 return -EINVAL; 194 195 write_seqlock_irq(&xtime_lock); 196 /* 197 * This is revolting. We need to set "xtime" correctly. However, the 198 * value in this location is the value at the most recent update of 199 * wall time. Discover what correction gettimeofday() would have 200 * made, and then undo it! 201 */ 202 nsec -= 1000 * usecs_since_tick(); 203 204 wtm_sec = wall_to_monotonic.tv_sec + (xtime.tv_sec - sec); 205 wtm_nsec = wall_to_monotonic.tv_nsec + (xtime.tv_nsec - nsec); 206 207 set_normalized_timespec(&xtime, sec, nsec); 208 set_normalized_timespec(&wall_to_monotonic, wtm_sec, wtm_nsec); 209 210 ntp_clear(); 211 write_sequnlock_irq(&xtime_lock); 212 clock_was_set(); 213 214 return 0; 215} 216EXPORT_SYMBOL(do_settimeofday); 217 218static int set_rtc_time(unsigned long nowtime) 219{ 220 int retval = 0; 221 int real_seconds, real_minutes, cmos_minutes; 222 223 ctrl_outb(RCR2_RESET, RCR2); /* Reset pre-scaler & stop RTC */ 224 225 cmos_minutes = ctrl_inb(RMINCNT); 226 BCD_TO_BIN(cmos_minutes); 227 228 /* 229 * since we're only adjusting minutes and seconds, 230 * don't interfere with hour overflow. This avoids 231 * messing with unknown time zones but requires your 232 * RTC not to be off by more than 15 minutes 233 */ 234 real_seconds = nowtime % 60; 235 real_minutes = nowtime / 60; 236 if (((abs(real_minutes - cmos_minutes) + 15)/30) & 1) 237 real_minutes += 30; /* correct for half hour time zone */ 238 real_minutes %= 60; 239 240 if (abs(real_minutes - cmos_minutes) < 30) { 241 BIN_TO_BCD(real_seconds); 242 BIN_TO_BCD(real_minutes); 243 ctrl_outb(real_seconds, RSECCNT); 244 ctrl_outb(real_minutes, RMINCNT); 245 } else { 246 printk(KERN_WARNING 247 "set_rtc_time: can't update from %d to %d\n", 248 cmos_minutes, real_minutes); 249 retval = -1; 250 } 251 252 ctrl_outb(RCR2_RTCEN|RCR2_START, RCR2); /* Start RTC */ 253 254 return retval; 255} 256 257/* last time the RTC clock got updated */ 258static long last_rtc_update = 0; 259 260/* 261 * timer_interrupt() needs to keep up the real-time clock, 262 * as well as call the "do_timer()" routine every clocktick 263 */ 264static inline void do_timer_interrupt(void) 265{ 266 unsigned long long current_ctc; 267 asm ("getcon cr62, %0" : "=r" (current_ctc)); 268 ctc_last_interrupt = (unsigned long) current_ctc; 269 270 do_timer(1); 271#ifndef CONFIG_SMP 272 update_process_times(user_mode(get_irq_regs())); 273#endif 274 if (current->pid) 275 profile_tick(CPU_PROFILING); 276 277#ifdef CONFIG_HEARTBEAT 278 { 279 extern void heartbeat(void); 280 281 heartbeat(); 282 } 283#endif 284 285 /* 286 * If we have an externally synchronized Linux clock, then update 287 * RTC clock accordingly every ~11 minutes. Set_rtc_mmss() has to be 288 * called as close as possible to 500 ms before the new second starts. 289 */ 290 if (ntp_synced() && 291 xtime.tv_sec > last_rtc_update + 660 && 292 (xtime.tv_nsec / 1000) >= 500000 - ((unsigned) TICK_SIZE) / 2 && 293 (xtime.tv_nsec / 1000) <= 500000 + ((unsigned) TICK_SIZE) / 2) { 294 if (set_rtc_time(xtime.tv_sec) == 0) 295 last_rtc_update = xtime.tv_sec; 296 else 297 last_rtc_update = xtime.tv_sec - 600; /* do it again in 60 s */ 298 } 299} 300 301/* 302 * This is the same as the above, except we _also_ save the current 303 * Time Stamp Counter value at the time of the timer interrupt, so that 304 * we later on can estimate the time of day more exactly. 305 */ 306static irqreturn_t timer_interrupt(int irq, void *dev_id) 307{ 308 unsigned long timer_status; 309 310 /* Clear UNF bit */ 311 timer_status = ctrl_inw(TMU0_TCR); 312 timer_status &= ~0x100; 313 ctrl_outw(timer_status, TMU0_TCR); 314 315 /* 316 * Here we are in the timer irq handler. We just have irqs locally 317 * disabled but we don't know if the timer_bh is running on the other 318 * CPU. We need to avoid to SMP race with it. NOTE: we don' t need 319 * the irq version of write_lock because as just said we have irq 320 * locally disabled. -arca 321 */ 322 write_lock(&xtime_lock); 323 do_timer_interrupt(); 324 write_unlock(&xtime_lock); 325 326 return IRQ_HANDLED; 327} 328 329static unsigned long get_rtc_time(void) 330{ 331 unsigned int sec, min, hr, wk, day, mon, yr, yr100; 332 333 again: 334 do { 335 ctrl_outb(0, RCR1); /* Clear CF-bit */ 336 sec = ctrl_inb(RSECCNT); 337 min = ctrl_inb(RMINCNT); 338 hr = ctrl_inb(RHRCNT); 339 wk = ctrl_inb(RWKCNT); 340 day = ctrl_inb(RDAYCNT); 341 mon = ctrl_inb(RMONCNT); 342 yr = ctrl_inw(RYRCNT); 343 yr100 = (yr >> 8); 344 yr &= 0xff; 345 } while ((ctrl_inb(RCR1) & RCR1_CF) != 0); 346 347 BCD_TO_BIN(yr100); 348 BCD_TO_BIN(yr); 349 BCD_TO_BIN(mon); 350 BCD_TO_BIN(day); 351 BCD_TO_BIN(hr); 352 BCD_TO_BIN(min); 353 BCD_TO_BIN(sec); 354 355 if (yr > 99 || mon < 1 || mon > 12 || day > 31 || day < 1 || 356 hr > 23 || min > 59 || sec > 59) { 357 printk(KERN_ERR 358 "SH RTC: invalid value, resetting to 1 Jan 2000\n"); 359 ctrl_outb(RCR2_RESET, RCR2); /* Reset & Stop */ 360 ctrl_outb(0, RSECCNT); 361 ctrl_outb(0, RMINCNT); 362 ctrl_outb(0, RHRCNT); 363 ctrl_outb(6, RWKCNT); 364 ctrl_outb(1, RDAYCNT); 365 ctrl_outb(1, RMONCNT); 366 ctrl_outw(0x2000, RYRCNT); 367 ctrl_outb(RCR2_RTCEN|RCR2_START, RCR2); /* Start */ 368 goto again; 369 } 370 371 return mktime(yr100 * 100 + yr, mon, day, hr, min, sec); 372} 373 374static __init unsigned int get_cpu_hz(void) 375{ 376 unsigned int count; 377 unsigned long __dummy; 378 unsigned long ctc_val_init, ctc_val; 379 380 /* 381 ** Regardless the toolchain, force the compiler to use the 382 ** arbitrary register r3 as a clock tick counter. 383 ** NOTE: r3 must be in accordance with sh64_rtc_interrupt() 384 */ 385 register unsigned long long __rtc_irq_flag __asm__ ("r3"); 386 387 local_irq_enable(); 388 do {} while (ctrl_inb(R64CNT) != 0); 389 ctrl_outb(RCR1_CIE, RCR1); /* Enable carry interrupt */ 390 391 /* 392 * r3 is arbitrary. CDC does not support "=z". 393 */ 394 ctc_val_init = 0xffffffff; 395 ctc_val = ctc_val_init; 396 397 asm volatile("gettr tr0, %1\n\t" 398 "putcon %0, " __CTC "\n\t" 399 "and %2, r63, %2\n\t" 400 "pta $+4, tr0\n\t" 401 "beq/l %2, r63, tr0\n\t" 402 "ptabs %1, tr0\n\t" 403 "getcon " __CTC ", %0\n\t" 404 : "=r"(ctc_val), "=r" (__dummy), "=r" (__rtc_irq_flag) 405 : "0" (0)); 406 local_irq_disable(); 407 /* 408 * SH-3: 409 * CPU clock = 4 stages * loop 410 * tst rm,rm if id ex 411 * bt/s 1b if id ex 412 * add #1,rd if id ex 413 * (if) pipe line stole 414 * tst rm,rm if id ex 415 * .... 416 * 417 * 418 * SH-4: 419 * CPU clock = 6 stages * loop 420 * I don't know why. 421 * .... 422 * 423 * SH-5: 424 * Use CTC register to count. This approach returns the right value 425 * even if the I-cache is disabled (e.g. whilst debugging.) 426 * 427 */ 428 429 count = ctc_val_init - ctc_val; /* CTC counts down */ 430 431#if defined(CONFIG_SH_SIMULATOR) 432 /* 433 * Let's pretend we are a 5MHz SH-5 to avoid a too 434 * little timer interval. Also to keep delay 435 * calibration within a reasonable time. 436 */ 437 return 5000000; 438#else 439 /* 440 * This really is count by the number of clock cycles 441 * by the ratio between a complete R64CNT 442 * wrap-around (128) and CUI interrupt being raised (64). 443 */ 444 return count*2; 445#endif 446} 447 448static irqreturn_t sh64_rtc_interrupt(int irq, void *dev_id) 449{ 450 struct pt_regs *regs = get_irq_regs(); 451 452 ctrl_outb(0, RCR1); /* Disable Carry Interrupts */ 453 regs->regs[3] = 1; /* Using r3 */ 454 455 return IRQ_HANDLED; 456} 457 458static struct irqaction irq0 = { timer_interrupt, IRQF_DISABLED, CPU_MASK_NONE, "timer", NULL, NULL}; 459static struct irqaction irq1 = { sh64_rtc_interrupt, IRQF_DISABLED, CPU_MASK_NONE, "rtc", NULL, NULL}; 460 461void __init time_init(void) 462{ 463 unsigned int cpu_clock, master_clock, bus_clock, module_clock; 464 unsigned long interval; 465 unsigned long frqcr, ifc, pfc; 466 static int ifc_table[] = { 2, 4, 6, 8, 10, 12, 16, 24 }; 467#define bfc_table ifc_table /* Same */ 468#define pfc_table ifc_table /* Same */ 469 470 tmu_base = onchip_remap(TMU_BASE, 1024, "TMU"); 471 if (!tmu_base) { 472 panic("Unable to remap TMU\n"); 473 } 474 475 rtc_base = onchip_remap(RTC_BASE, 1024, "RTC"); 476 if (!rtc_base) { 477 panic("Unable to remap RTC\n"); 478 } 479 480 cprc_base = onchip_remap(CPRC_BASE, 1024, "CPRC"); 481 if (!cprc_base) { 482 panic("Unable to remap CPRC\n"); 483 } 484 485 xtime.tv_sec = get_rtc_time(); 486 xtime.tv_nsec = 0; 487 488 setup_irq(TIMER_IRQ, &irq0); 489 setup_irq(RTC_IRQ, &irq1); 490 491 /* Check how fast it is.. */ 492 cpu_clock = get_cpu_hz(); 493 494 /* Note careful order of operations to maintain reasonable precision and avoid overflow. */ 495 scaled_recip_ctc_ticks_per_jiffy = ((1ULL << CTC_JIFFY_SCALE_SHIFT) / (unsigned long long)(cpu_clock / HZ)); 496 497 disable_irq(RTC_IRQ); 498 499 printk("CPU clock: %d.%02dMHz\n", 500 (cpu_clock / 1000000), (cpu_clock % 1000000)/10000); 501 { 502 unsigned short bfc; 503 frqcr = ctrl_inl(FRQCR); 504 ifc = ifc_table[(frqcr>> 6) & 0x0007]; 505 bfc = bfc_table[(frqcr>> 3) & 0x0007]; 506 pfc = pfc_table[(frqcr>> 12) & 0x0007]; 507 master_clock = cpu_clock * ifc; 508 bus_clock = master_clock/bfc; 509 } 510 511 printk("Bus clock: %d.%02dMHz\n", 512 (bus_clock/1000000), (bus_clock % 1000000)/10000); 513 module_clock = master_clock/pfc; 514 printk("Module clock: %d.%02dMHz\n", 515 (module_clock/1000000), (module_clock % 1000000)/10000); 516 interval = (module_clock/(HZ*4)); 517 518 printk("Interval = %ld\n", interval); 519 520 current_cpu_data.cpu_clock = cpu_clock; 521 current_cpu_data.master_clock = master_clock; 522 current_cpu_data.bus_clock = bus_clock; 523 current_cpu_data.module_clock = module_clock; 524 525 /* Start TMU0 */ 526 ctrl_outb(TMU_TSTR_OFF, TMU_TSTR); 527 ctrl_outb(TMU_TOCR_INIT, TMU_TOCR); 528 ctrl_outw(TMU0_TCR_INIT, TMU0_TCR); 529 ctrl_outl(interval, TMU0_TCOR); 530 ctrl_outl(interval, TMU0_TCNT); 531 ctrl_outb(TMU_TSTR_INIT, TMU_TSTR); 532} 533 534void enter_deep_standby(void) 535{ 536 /* Disable watchdog timer */ 537 ctrl_outl(0xa5000000, WTCSR); 538 /* Configure deep standby on sleep */ 539 ctrl_outl(0x03, STBCR); 540 541#ifdef CONFIG_SH_ALPHANUMERIC 542 { 543 extern void mach_alphanum(int position, unsigned char value); 544 extern void mach_alphanum_brightness(int setting); 545 char halted[] = "Halted. "; 546 int i; 547 mach_alphanum_brightness(6); /* dimmest setting above off */ 548 for (i=0; i<8; i++) { 549 mach_alphanum(i, halted[i]); 550 } 551 asm __volatile__ ("synco"); 552 } 553#endif 554 555 asm __volatile__ ("sleep"); 556 asm __volatile__ ("synci"); 557 asm __volatile__ ("nop"); 558 asm __volatile__ ("nop"); 559 asm __volatile__ ("nop"); 560 asm __volatile__ ("nop"); 561 panic("Unexpected wakeup!\n"); 562} 563