1/* 2 * arch/sh/mm/tlb-sh4.c 3 * 4 * SH-4 specific TLB operations 5 * 6 * Copyright (C) 1999 Niibe Yutaka 7 * Copyright (C) 2002 Paul Mundt 8 * 9 * Released under the terms of the GNU GPL v2.0. 10 */ 11#include <linux/signal.h> 12#include <linux/sched.h> 13#include <linux/kernel.h> 14#include <linux/errno.h> 15#include <linux/string.h> 16#include <linux/types.h> 17#include <linux/ptrace.h> 18#include <linux/mman.h> 19#include <linux/mm.h> 20#include <linux/smp.h> 21#include <linux/smp_lock.h> 22#include <linux/interrupt.h> 23 24#include <asm/system.h> 25#include <asm/io.h> 26#include <asm/uaccess.h> 27#include <asm/pgalloc.h> 28#include <asm/mmu_context.h> 29#include <asm/cacheflush.h> 30 31void update_mmu_cache(struct vm_area_struct * vma, 32 unsigned long address, pte_t pte) 33{ 34 unsigned long flags; 35 unsigned long pteval; 36 unsigned long vpn; 37 struct page *page; 38 unsigned long pfn; 39 40 /* Ptrace may call this routine. */ 41 if (vma && current->active_mm != vma->vm_mm) 42 return; 43 44 pfn = pte_pfn(pte); 45 if (pfn_valid(pfn)) { 46 page = pfn_to_page(pfn); 47 if (!test_bit(PG_mapped, &page->flags)) { 48 unsigned long phys = pte_val(pte) & PTE_PHYS_MASK; 49 __flush_wback_region((void *)P1SEGADDR(phys), PAGE_SIZE); 50 __set_bit(PG_mapped, &page->flags); 51 } 52 } 53 54 local_irq_save(flags); 55 56 /* Set PTEH register */ 57 vpn = (address & MMU_VPN_MASK) | get_asid(); 58 ctrl_outl(vpn, MMU_PTEH); 59 60 pteval = pte_val(pte); 61 62 /* Set PTEA register */ 63 if (cpu_data->flags & CPU_HAS_PTEA) 64 /* TODO: make this look less hacky */ 65 ctrl_outl(((pteval >> 28) & 0xe) | (pteval & 0x1), MMU_PTEA); 66 67 /* Set PTEL register */ 68 pteval &= _PAGE_FLAGS_HARDWARE_MASK; /* drop software flags */ 69#ifdef CONFIG_SH_WRITETHROUGH 70 pteval |= _PAGE_WT; 71#endif 72 /* conveniently, we want all the software flags to be 0 anyway */ 73 ctrl_outl(pteval, MMU_PTEL); 74 75 /* Load the TLB */ 76 asm volatile("ldtlb": /* no output */ : /* no input */ : "memory"); 77 local_irq_restore(flags); 78} 79 80void local_flush_tlb_one(unsigned long asid, unsigned long page) 81{ 82 unsigned long addr, data; 83 84 /* 85 * NOTE: PTEH.ASID should be set to this MM 86 * _AND_ we need to write ASID to the array. 87 * 88 * It would be simple if we didn't need to set PTEH.ASID... 89 */ 90 addr = MMU_UTLB_ADDRESS_ARRAY | MMU_PAGE_ASSOC_BIT; 91 data = page | asid; /* VALID bit is off */ 92 jump_to_P2(); 93 ctrl_outl(data, addr); 94 back_to_P1(); 95} 96