1/* 2 * linux/arch/sh/boards/se/770x/setup.c 3 * 4 * Copyright (C) 2000 Kazumoto Kojima 5 * 6 * Hitachi SolutionEngine Support. 7 * 8 */ 9#include <linux/init.h> 10#include <linux/platform_device.h> 11#include <asm/machvec.h> 12#include <asm/se.h> 13#include <asm/io.h> 14#include <asm/smc37c93x.h> 15 16void init_se_IRQ(void); 17 18/* 19 * Configure the Super I/O chip 20 */ 21static void __init smsc_config(int index, int data) 22{ 23 outb_p(index, INDEX_PORT); 24 outb_p(data, DATA_PORT); 25} 26 27static void __init smsc_setup(char **cmdline_p) 28{ 29 outb_p(CONFIG_ENTER, CONFIG_PORT); 30 outb_p(CONFIG_ENTER, CONFIG_PORT); 31 32 /* FDC */ 33 smsc_config(CURRENT_LDN_INDEX, LDN_FDC); 34 smsc_config(ACTIVATE_INDEX, 0x01); 35 smsc_config(IRQ_SELECT_INDEX, 6); /* IRQ6 */ 36 37 /* AUXIO (GPIO): to use IDE1 */ 38 smsc_config(CURRENT_LDN_INDEX, LDN_AUXIO); 39 smsc_config(GPIO46_INDEX, 0x00); /* nIOROP */ 40 smsc_config(GPIO47_INDEX, 0x00); /* nIOWOP */ 41 42 /* COM1 */ 43 smsc_config(CURRENT_LDN_INDEX, LDN_COM1); 44 smsc_config(ACTIVATE_INDEX, 0x01); 45 smsc_config(IO_BASE_HI_INDEX, 0x03); 46 smsc_config(IO_BASE_LO_INDEX, 0xf8); 47 smsc_config(IRQ_SELECT_INDEX, 4); /* IRQ4 */ 48 49 /* COM2 */ 50 smsc_config(CURRENT_LDN_INDEX, LDN_COM2); 51 smsc_config(ACTIVATE_INDEX, 0x01); 52 smsc_config(IO_BASE_HI_INDEX, 0x02); 53 smsc_config(IO_BASE_LO_INDEX, 0xf8); 54 smsc_config(IRQ_SELECT_INDEX, 3); /* IRQ3 */ 55 56 /* RTC */ 57 smsc_config(CURRENT_LDN_INDEX, LDN_RTC); 58 smsc_config(ACTIVATE_INDEX, 0x01); 59 smsc_config(IRQ_SELECT_INDEX, 8); /* IRQ8 */ 60 61 outb_p(CONFIG_EXIT, CONFIG_PORT); 62} 63 64 65static struct resource cf_ide_resources[] = { 66 [0] = { 67 .start = PA_MRSHPC_IO + 0x1f0, 68 .end = PA_MRSHPC_IO + 0x1f0 + 8, 69 .flags = IORESOURCE_MEM, 70 }, 71 [1] = { 72 .start = PA_MRSHPC_IO + 0x1f0 + 0x206, 73 .end = PA_MRSHPC_IO + 0x1f0 +8 + 0x206 + 8, 74 .flags = IORESOURCE_MEM, 75 }, 76 [2] = { 77 .start = IRQ_CFCARD, 78 .flags = IORESOURCE_IRQ, 79 }, 80}; 81 82static struct platform_device cf_ide_device = { 83 .name = "pata_platform", 84 .id = -1, 85 .num_resources = ARRAY_SIZE(cf_ide_resources), 86 .resource = cf_ide_resources, 87}; 88 89static unsigned char heartbeat_bit_pos[] = { 8, 9, 10, 11, 12, 13, 14, 15 }; 90 91static struct resource heartbeat_resources[] = { 92 [0] = { 93 .start = PA_LED, 94 .end = PA_LED + ARRAY_SIZE(heartbeat_bit_pos) - 1, 95 .flags = IORESOURCE_MEM, 96 }, 97}; 98 99static struct platform_device heartbeat_device = { 100 .name = "heartbeat", 101 .id = -1, 102 .dev = { 103 .platform_data = heartbeat_bit_pos, 104 }, 105 .num_resources = ARRAY_SIZE(heartbeat_resources), 106 .resource = heartbeat_resources, 107}; 108 109static struct platform_device *se_devices[] __initdata = { 110 &heartbeat_device, 111 &cf_ide_device, 112}; 113 114static int __init se_devices_setup(void) 115{ 116 return platform_add_devices(se_devices, ARRAY_SIZE(se_devices)); 117} 118device_initcall(se_devices_setup); 119 120/* 121 * The Machine Vector 122 */ 123struct sh_machine_vector mv_se __initmv = { 124 .mv_name = "SolutionEngine", 125 .mv_setup = smsc_setup, 126#if defined(CONFIG_CPU_SH4) 127 .mv_nr_irqs = 48, 128#elif defined(CONFIG_CPU_SUBTYPE_SH7708) 129 .mv_nr_irqs = 32, 130#elif defined(CONFIG_CPU_SUBTYPE_SH7709) 131 .mv_nr_irqs = 61, 132#elif defined(CONFIG_CPU_SUBTYPE_SH7705) 133 .mv_nr_irqs = 86, 134#elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712) 135 .mv_nr_irqs = 104, 136#endif 137 138 .mv_inb = se_inb, 139 .mv_inw = se_inw, 140 .mv_inl = se_inl, 141 .mv_outb = se_outb, 142 .mv_outw = se_outw, 143 .mv_outl = se_outl, 144 145 .mv_inb_p = se_inb_p, 146 .mv_inw_p = se_inw, 147 .mv_inl_p = se_inl, 148 .mv_outb_p = se_outb_p, 149 .mv_outw_p = se_outw, 150 .mv_outl_p = se_outl, 151 152 .mv_insb = se_insb, 153 .mv_insw = se_insw, 154 .mv_insl = se_insl, 155 .mv_outsb = se_outsb, 156 .mv_outsw = se_outsw, 157 .mv_outsl = se_outsl, 158 159 .mv_init_irq = init_se_IRQ, 160}; 161ALIAS_MV(se) 162