1/* ppc.h -- Header file for PowerPC opcode table 2 Copyright 1994 Free Software Foundation, Inc. 3 Written by Ian Lance Taylor, Cygnus Support 4 5This file is part of GDB, GAS, and the GNU binutils. 6 7GDB, GAS, and the GNU binutils are free software; you can redistribute 8them and/or modify them under the terms of the GNU General Public 9License as published by the Free Software Foundation; either version 101, or (at your option) any later version. 11 12GDB, GAS, and the GNU binutils are distributed in the hope that they 13will be useful, but WITHOUT ANY WARRANTY; without even the implied 14warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See 15the GNU General Public License for more details. 16 17You should have received a copy of the GNU General Public License 18along with this file; see the file COPYING. If not, write to the Free 19Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ 20 21#ifndef PPC_H 22#define PPC_H 23 24/* The opcode table is an array of struct powerpc_opcode. */ 25 26struct powerpc_opcode 27{ 28 /* The opcode name. */ 29 const char *name; 30 31 /* The opcode itself. Those bits which will be filled in with 32 operands are zeroes. */ 33 unsigned long opcode; 34 35 /* The opcode mask. This is used by the disassembler. This is a 36 mask containing ones indicating those bits which must match the 37 opcode field, and zeroes indicating those bits which need not 38 match (and are presumably filled in by operands). */ 39 unsigned long mask; 40 41 /* One bit flags for the opcode. These are used to indicate which 42 specific processors support the instructions. The defined values 43 are listed below. */ 44 unsigned long flags; 45 46 /* An array of operand codes. Each code is an index into the 47 operand table. They appear in the order which the operands must 48 appear in assembly code, and are terminated by a zero. */ 49 unsigned char operands[8]; 50}; 51 52/* The table itself is sorted by major opcode number, and is otherwise 53 in the order in which the disassembler should consider 54 instructions. */ 55extern const struct powerpc_opcode powerpc_opcodes[]; 56extern const int powerpc_num_opcodes; 57 58/* Values defined for the flags field of a struct powerpc_opcode. */ 59 60/* Opcode is defined for the PowerPC architecture. */ 61#define PPC_OPCODE_PPC (01) 62 63/* Opcode is defined for the POWER (RS/6000) architecture. */ 64#define PPC_OPCODE_POWER (02) 65 66/* Opcode is defined for the POWER2 (Rios 2) architecture. */ 67#define PPC_OPCODE_POWER2 (04) 68 69/* Opcode is only defined on 32 bit architectures. */ 70#define PPC_OPCODE_32 (010) 71 72/* Opcode is only defined on 64 bit architectures. */ 73#define PPC_OPCODE_64 (020) 74 75/* Opcode is supported by the Motorola PowerPC 601 processor. The 601 76 is assumed to support all PowerPC (PPC_OPCODE_PPC) instructions, 77 but it also supports many additional POWER instructions. */ 78#define PPC_OPCODE_601 (040) 79 80/* A macro to extract the major opcode from an instruction. */ 81#define PPC_OP(i) (((i) >> 26) & 0x3f) 82 83/* The operands table is an array of struct powerpc_operand. */ 84 85struct powerpc_operand 86{ 87 /* The number of bits in the operand. */ 88 int bits; 89 90 /* How far the operand is left shifted in the instruction. */ 91 int shift; 92 93 /* Insertion function. This is used by the assembler. To insert an 94 operand value into an instruction, check this field. 95 96 If it is NULL, execute 97 i |= (op & ((1 << o->bits) - 1)) << o->shift; 98 (i is the instruction which we are filling in, o is a pointer to 99 this structure, and op is the opcode value; this assumes twos 100 complement arithmetic). 101 102 If this field is not NULL, then simply call it with the 103 instruction and the operand value. It will return the new value 104 of the instruction. If the ERRMSG argument is not NULL, then if 105 the operand value is illegal, *ERRMSG will be set to a warning 106 string (the operand will be inserted in any case). If the 107 operand value is legal, *ERRMSG will be unchanged (most operands 108 can accept any value). */ 109 unsigned long (*insert) PARAMS ((unsigned long instruction, long op, 110 const char **errmsg)); 111 112 /* Extraction function. This is used by the disassembler. To 113 extract this operand type from an instruction, check this field. 114 115 If it is NULL, compute 116 op = ((i) >> o->shift) & ((1 << o->bits) - 1); 117 if ((o->flags & PPC_OPERAND_SIGNED) != 0 118 && (op & (1 << (o->bits - 1))) != 0) 119 op -= 1 << o->bits; 120 (i is the instruction, o is a pointer to this structure, and op 121 is the result; this assumes twos complement arithmetic). 122 123 If this field is not NULL, then simply call it with the 124 instruction value. It will return the value of the operand. If 125 the INVALID argument is not NULL, *INVALID will be set to 126 non-zero if this operand type can not actually be extracted from 127 this operand (i.e., the instruction does not match). If the 128 operand is valid, *INVALID will not be changed. */ 129 long (*extract) PARAMS ((unsigned long instruction, int *invalid)); 130 131 /* One bit syntax flags. */ 132 unsigned long flags; 133}; 134 135/* Elements in the table are retrieved by indexing with values from 136 the operands field of the powerpc_opcodes table. */ 137 138extern const struct powerpc_operand powerpc_operands[]; 139 140/* Values defined for the flags field of a struct powerpc_operand. */ 141 142/* This operand takes signed values. */ 143#define PPC_OPERAND_SIGNED (01) 144 145/* This operand takes signed values, but also accepts a full positive 146 range of values when running in 32 bit mode. That is, if bits is 147 16, it takes any value from -0x8000 to 0xffff. In 64 bit mode, 148 this flag is ignored. */ 149#define PPC_OPERAND_SIGNOPT (02) 150 151/* This operand does not actually exist in the assembler input. This 152 is used to support extended mnemonics such as mr, for which two 153 operands fields are identical. The assembler should call the 154 insert function with any op value. The disassembler should call 155 the extract function, ignore the return value, and check the value 156 placed in the valid argument. */ 157#define PPC_OPERAND_FAKE (04) 158 159/* The next operand should be wrapped in parentheses rather than 160 separated from this one by a comma. This is used for the load and 161 store instructions which want their operands to look like 162 reg,displacement(reg) 163 */ 164#define PPC_OPERAND_PARENS (010) 165 166/* This operand may use the symbolic names for the CR fields, which 167 are 168 lt 0 gt 1 eq 2 so 3 un 3 169 cr0 0 cr1 1 cr2 2 cr3 3 170 cr4 4 cr5 5 cr6 6 cr7 7 171 These may be combined arithmetically, as in cr2*4+gt. These are 172 only supported on the PowerPC, not the POWER. */ 173#define PPC_OPERAND_CR (020) 174 175/* This operand names a register. The disassembler uses this to print 176 register names with a leading 'r'. */ 177#define PPC_OPERAND_GPR (040) 178 179/* This operand names a floating point register. The disassembler 180 prints these with a leading 'f'. */ 181#define PPC_OPERAND_FPR (0100) 182 183/* This operand is a relative branch displacement. The disassembler 184 prints these symbolically if possible. */ 185#define PPC_OPERAND_RELATIVE (0200) 186 187/* This operand is an absolute branch address. The disassembler 188 prints these symbolically if possible. */ 189#define PPC_OPERAND_ABSOLUTE (0400) 190 191/* This operand is optional, and is zero if omitted. This is used for 192 the optional BF and L fields in the comparison instructions. The 193 assembler must count the number of operands remaining on the line, 194 and the number of operands remaining for the opcode, and decide 195 whether this operand is present or not. The disassembler should 196 print this operand out only if it is not zero. */ 197#define PPC_OPERAND_OPTIONAL (01000) 198 199/* This flag is only used with PPC_OPERAND_OPTIONAL. If this operand 200 is omitted, then for the next operand use this operand value plus 201 1, ignoring the next operand field for the opcode. This wretched 202 hack is needed because the Power rotate instructions can take 203 either 4 or 5 operands. The disassembler should print this operand 204 out regardless of the PPC_OPERAND_OPTIONAL field. */ 205#define PPC_OPERAND_NEXT (02000) 206 207/* This operand should be regarded as a negative number for the 208 purposes of overflow checking (i.e., the normal most negative 209 number is disallowed and one more than the normal most positive 210 number is allowed). This flag will only be set for a signed 211 operand. */ 212#define PPC_OPERAND_NEGATIVE (04000) 213 214/* The POWER and PowerPC assemblers use a few macros. We keep them 215 with the operands table for simplicity. The macro table is an 216 array of struct powerpc_macro. */ 217 218struct powerpc_macro 219{ 220 /* The macro name. */ 221 const char *name; 222 223 /* The number of operands the macro takes. */ 224 unsigned int operands; 225 226 /* One bit flags for the opcode. These are used to indicate which 227 specific processors support the instructions. The values are the 228 same as those for the struct powerpc_opcode flags field. */ 229 unsigned long flags; 230 231 /* A format string to turn the macro into a normal instruction. 232 Each %N in the string is replaced with operand number N (zero 233 based). */ 234 const char *format; 235}; 236 237extern const struct powerpc_macro powerpc_macros[]; 238extern const int powerpc_num_macros; 239 240#endif /* PPC_H */ 241