1/* 2 * Copyright (c) 2005 Cisco Systems. All rights reserved. 3 * Roland Dreier <rolandd@cisco.com> 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License as published by the 7 * Free Software Foundation; either version 2 of the License, or (at your 8 * option) any later version. 9 */ 10 11#include <linux/kernel.h> 12#include <linux/delay.h> 13#include <linux/pci.h> 14#include <linux/init.h> 15 16#include <asm/reg.h> 17#include <asm/io.h> 18#include <asm/ibm44x.h> 19 20#include "ppc440spe_pcie.h" 21 22static int 23pcie_read_config(struct pci_bus *bus, unsigned int devfn, int offset, 24 int len, u32 *val) 25{ 26 struct pci_controller *hose = bus->sysdata; 27 28 if (PCI_SLOT(devfn) != 1) 29 return PCIBIOS_DEVICE_NOT_FOUND; 30 31 offset += devfn << 12; 32 33 /* 34 * Note: the caller has already checked that offset is 35 * suitably aligned and that len is 1, 2 or 4. 36 */ 37 switch (len) { 38 case 1: 39 *val = in_8(hose->cfg_data + offset); 40 break; 41 case 2: 42 *val = in_le16(hose->cfg_data + offset); 43 break; 44 default: 45 *val = in_le32(hose->cfg_data + offset); 46 break; 47 } 48 49 if (0) printk("%s: read %x(%d) @ %x\n", __func__, *val, len, offset); 50 51 return PCIBIOS_SUCCESSFUL; 52} 53 54static int 55pcie_write_config(struct pci_bus *bus, unsigned int devfn, int offset, 56 int len, u32 val) 57{ 58 struct pci_controller *hose = bus->sysdata; 59 60 if (PCI_SLOT(devfn) != 1) 61 return PCIBIOS_DEVICE_NOT_FOUND; 62 63 offset += devfn << 12; 64 65 switch (len) { 66 case 1: 67 out_8(hose->cfg_data + offset, val); 68 break; 69 case 2: 70 out_le16(hose->cfg_data + offset, val); 71 break; 72 default: 73 out_le32(hose->cfg_data + offset, val); 74 break; 75 } 76 return PCIBIOS_SUCCESSFUL; 77} 78 79static struct pci_ops pcie_pci_ops = 80{ 81 .read = pcie_read_config, 82 .write = pcie_write_config 83}; 84 85enum { 86 PTYPE_ENDPOINT = 0x0, 87 PTYPE_LEGACY_ENDPOINT = 0x1, 88 PTYPE_ROOT_PORT = 0x4, 89 90 LNKW_X1 = 0x1, 91 LNKW_X4 = 0x4, 92 LNKW_X8 = 0x8 93}; 94 95static void check_error(void) 96{ 97 u32 valPE0, valPE1, valPE2; 98 99 /* SDR0_PEGPLLLCT1 reset */ 100 if (!(valPE0 = SDR_READ(PESDR0_PLLLCT1) & 0x01000000)) { 101 printk(KERN_INFO "PCIE: SDR0_PEGPLLLCT1 reset error 0x%8x\n", valPE0); 102 } 103 104 valPE0 = SDR_READ(PESDR0_RCSSET); 105 valPE1 = SDR_READ(PESDR1_RCSSET); 106 valPE2 = SDR_READ(PESDR2_RCSSET); 107 108 /* SDR0_PExRCSSET rstgu */ 109 if ( !(valPE0 & 0x01000000) || 110 !(valPE1 & 0x01000000) || 111 !(valPE2 & 0x01000000)) { 112 printk(KERN_INFO "PCIE: SDR0_PExRCSSET rstgu error\n"); 113 } 114 115 /* SDR0_PExRCSSET rstdl */ 116 if ( !(valPE0 & 0x00010000) || 117 !(valPE1 & 0x00010000) || 118 !(valPE2 & 0x00010000)) { 119 printk(KERN_INFO "PCIE: SDR0_PExRCSSET rstdl error\n"); 120 } 121 122 /* SDR0_PExRCSSET rstpyn */ 123 if ( (valPE0 & 0x00001000) || 124 (valPE1 & 0x00001000) || 125 (valPE2 & 0x00001000)) { 126 printk(KERN_INFO "PCIE: SDR0_PExRCSSET rstpyn error\n"); 127 } 128 129 /* SDR0_PExRCSSET hldplb */ 130 if ( (valPE0 & 0x10000000) || 131 (valPE1 & 0x10000000) || 132 (valPE2 & 0x10000000)) { 133 printk(KERN_INFO "PCIE: SDR0_PExRCSSET hldplb error\n"); 134 } 135 136 /* SDR0_PExRCSSET rdy */ 137 if ( (valPE0 & 0x00100000) || 138 (valPE1 & 0x00100000) || 139 (valPE2 & 0x00100000)) { 140 printk(KERN_INFO "PCIE: SDR0_PExRCSSET rdy error\n"); 141 } 142 143 /* SDR0_PExRCSSET shutdown */ 144 if ( (valPE0 & 0x00000100) || 145 (valPE1 & 0x00000100) || 146 (valPE2 & 0x00000100)) { 147 printk(KERN_INFO "PCIE: SDR0_PExRCSSET shutdown error\n"); 148 } 149} 150 151/* 152 * Initialize PCI Express core as described in User Manual section 27.12.1 153 */ 154int ppc440spe_init_pcie(void) 155{ 156 /* Set PLL clock receiver to LVPECL */ 157 SDR_WRITE(PESDR0_PLLLCT1, SDR_READ(PESDR0_PLLLCT1) | 1 << 28); 158 159 check_error(); 160 161 printk(KERN_INFO "PCIE initialization OK\n"); 162 163 if (!(SDR_READ(PESDR0_PLLLCT2) & 0x10000)) 164 printk(KERN_INFO "PESDR_PLLCT2 resistance calibration failed (0x%08x)\n", 165 SDR_READ(PESDR0_PLLLCT2)); 166 167 /* De-assert reset of PCIe PLL, wait for lock */ 168 SDR_WRITE(PESDR0_PLLLCT1, SDR_READ(PESDR0_PLLLCT1) & ~(1 << 24)); 169 udelay(3); 170 171 return 0; 172} 173 174int ppc440spe_init_pcie_rootport(int port) 175{ 176 static int core_init; 177 void __iomem *utl_base; 178 u32 val = 0; 179 int i; 180 181 if (!core_init) { 182 ++core_init; 183 i = ppc440spe_init_pcie(); 184 if (i) 185 return i; 186 } 187 188 /* 189 * Initialize various parts of the PCI Express core for our port: 190 * 191 * - Set as a root port and enable max width 192 * (PXIE0 -> X8, PCIE1 and PCIE2 -> X4). 193 * - Set up UTL configuration. 194 * - Increase SERDES drive strength to levels suggested by AMCC. 195 * - De-assert RSTPYN, RSTDL and RSTGU. 196 */ 197 switch (port) { 198 case 0: 199 SDR_WRITE(PESDR0_DLPSET, PTYPE_ROOT_PORT << 20 | LNKW_X8 << 12); 200 201 SDR_WRITE(PESDR0_UTLSET1, 0x21222222); 202 SDR_WRITE(PESDR0_UTLSET2, 0x11000000); 203 204 SDR_WRITE(PESDR0_HSSL0SET1, 0x35000000); 205 SDR_WRITE(PESDR0_HSSL1SET1, 0x35000000); 206 SDR_WRITE(PESDR0_HSSL2SET1, 0x35000000); 207 SDR_WRITE(PESDR0_HSSL3SET1, 0x35000000); 208 SDR_WRITE(PESDR0_HSSL4SET1, 0x35000000); 209 SDR_WRITE(PESDR0_HSSL5SET1, 0x35000000); 210 SDR_WRITE(PESDR0_HSSL6SET1, 0x35000000); 211 SDR_WRITE(PESDR0_HSSL7SET1, 0x35000000); 212 213 SDR_WRITE(PESDR0_RCSSET, 214 (SDR_READ(PESDR0_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12); 215 break; 216 217 case 1: 218 SDR_WRITE(PESDR1_DLPSET, PTYPE_ROOT_PORT << 20 | LNKW_X4 << 12); 219 220 SDR_WRITE(PESDR1_UTLSET1, 0x21222222); 221 SDR_WRITE(PESDR1_UTLSET2, 0x11000000); 222 223 SDR_WRITE(PESDR1_HSSL0SET1, 0x35000000); 224 SDR_WRITE(PESDR1_HSSL1SET1, 0x35000000); 225 SDR_WRITE(PESDR1_HSSL2SET1, 0x35000000); 226 SDR_WRITE(PESDR1_HSSL3SET1, 0x35000000); 227 228 SDR_WRITE(PESDR1_RCSSET, 229 (SDR_READ(PESDR1_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12); 230 break; 231 232 case 2: 233 SDR_WRITE(PESDR2_DLPSET, PTYPE_ROOT_PORT << 20 | LNKW_X4 << 12); 234 235 SDR_WRITE(PESDR2_UTLSET1, 0x21222222); 236 SDR_WRITE(PESDR2_UTLSET2, 0x11000000); 237 238 SDR_WRITE(PESDR2_HSSL0SET1, 0x35000000); 239 SDR_WRITE(PESDR2_HSSL1SET1, 0x35000000); 240 SDR_WRITE(PESDR2_HSSL2SET1, 0x35000000); 241 SDR_WRITE(PESDR2_HSSL3SET1, 0x35000000); 242 243 SDR_WRITE(PESDR2_RCSSET, 244 (SDR_READ(PESDR2_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12); 245 break; 246 } 247 248 mdelay(1000); 249 250 switch (port) { 251 case 0: val = SDR_READ(PESDR0_RCSSTS); break; 252 case 1: val = SDR_READ(PESDR1_RCSSTS); break; 253 case 2: val = SDR_READ(PESDR2_RCSSTS); break; 254 } 255 256 if (!(val & (1 << 20))) 257 printk(KERN_INFO "PCIE%d: PGRST inactive\n", port); 258 else 259 printk(KERN_WARNING "PGRST for PCIE%d failed %08x\n", port, val); 260 261 switch (port) { 262 case 0: printk(KERN_INFO "PCIE0: LOOP %08x\n", SDR_READ(PESDR0_LOOP)); break; 263 case 1: printk(KERN_INFO "PCIE1: LOOP %08x\n", SDR_READ(PESDR1_LOOP)); break; 264 case 2: printk(KERN_INFO "PCIE2: LOOP %08x\n", SDR_READ(PESDR2_LOOP)); break; 265 } 266 267 /* 268 * Map UTL registers at 0xc_1000_0n00 269 */ 270 switch (port) { 271 case 0: 272 mtdcr(DCRN_PEGPL_REGBAH(PCIE0), 0x0000000c); 273 mtdcr(DCRN_PEGPL_REGBAL(PCIE0), 0x10000000); 274 mtdcr(DCRN_PEGPL_REGMSK(PCIE0), 0x00007001); 275 mtdcr(DCRN_PEGPL_SPECIAL(PCIE0), 0x68782800); 276 break; 277 278 case 1: 279 mtdcr(DCRN_PEGPL_REGBAH(PCIE1), 0x0000000c); 280 mtdcr(DCRN_PEGPL_REGBAL(PCIE1), 0x10001000); 281 mtdcr(DCRN_PEGPL_REGMSK(PCIE1), 0x00007001); 282 mtdcr(DCRN_PEGPL_SPECIAL(PCIE1), 0x68782800); 283 break; 284 285 case 2: 286 mtdcr(DCRN_PEGPL_REGBAH(PCIE2), 0x0000000c); 287 mtdcr(DCRN_PEGPL_REGBAL(PCIE2), 0x10002000); 288 mtdcr(DCRN_PEGPL_REGMSK(PCIE2), 0x00007001); 289 mtdcr(DCRN_PEGPL_SPECIAL(PCIE2), 0x68782800); 290 } 291 292 utl_base = ioremap64(0xc10000000ull + 0x1000 * port, 0x100); 293 294 /* 295 * Set buffer allocations and then assert VRB and TXE. 296 */ 297 out_be32(utl_base + PEUTL_OUTTR, 0x08000000); 298 out_be32(utl_base + PEUTL_INTR, 0x02000000); 299 out_be32(utl_base + PEUTL_OPDBSZ, 0x10000000); 300 out_be32(utl_base + PEUTL_PBBSZ, 0x53000000); 301 out_be32(utl_base + PEUTL_IPHBSZ, 0x08000000); 302 out_be32(utl_base + PEUTL_IPDBSZ, 0x10000000); 303 out_be32(utl_base + PEUTL_RCIRQEN, 0x00f00000); 304 out_be32(utl_base + PEUTL_PCTL, 0x80800066); 305 306 iounmap(utl_base); 307 308 /* 309 * We map PCI Express configuration access into the 512MB regions 310 * PCIE0: 0xc_4000_0000 311 * PCIE1: 0xc_8000_0000 312 * PCIE2: 0xc_c000_0000 313 */ 314 switch (port) { 315 case 0: 316 mtdcr(DCRN_PEGPL_CFGBAH(PCIE0), 0x0000000c); 317 mtdcr(DCRN_PEGPL_CFGBAL(PCIE0), 0x40000000); 318 mtdcr(DCRN_PEGPL_CFGMSK(PCIE0), 0xe0000001); /* 512MB region, valid */ 319 break; 320 321 case 1: 322 mtdcr(DCRN_PEGPL_CFGBAH(PCIE1), 0x0000000c); 323 mtdcr(DCRN_PEGPL_CFGBAL(PCIE1), 0x80000000); 324 mtdcr(DCRN_PEGPL_CFGMSK(PCIE1), 0xe0000001); /* 512MB region, valid */ 325 break; 326 327 case 2: 328 mtdcr(DCRN_PEGPL_CFGBAH(PCIE2), 0x0000000c); 329 mtdcr(DCRN_PEGPL_CFGBAL(PCIE2), 0xc0000000); 330 mtdcr(DCRN_PEGPL_CFGMSK(PCIE2), 0xe0000001); /* 512MB region, valid */ 331 break; 332 } 333 334 /* 335 * Check for VC0 active and assert RDY. 336 */ 337 switch (port) { 338 case 0: 339 if (!(SDR_READ(PESDR0_RCSSTS) & (1 << 16))) 340 printk(KERN_WARNING "PCIE0: VC0 not active\n"); 341 SDR_WRITE(PESDR0_RCSSET, SDR_READ(PESDR0_RCSSET) | 1 << 20); 342 break; 343 case 1: 344 if (!(SDR_READ(PESDR1_RCSSTS) & (1 << 16))) 345 printk(KERN_WARNING "PCIE0: VC0 not active\n"); 346 SDR_WRITE(PESDR1_RCSSET, SDR_READ(PESDR1_RCSSET) | 1 << 20); 347 break; 348 case 2: 349 if (!(SDR_READ(PESDR2_RCSSTS) & (1 << 16))) 350 printk(KERN_WARNING "PCIE0: VC0 not active\n"); 351 SDR_WRITE(PESDR2_RCSSET, SDR_READ(PESDR2_RCSSET) | 1 << 20); 352 break; 353 } 354 355 356 mdelay(100); 357 358 return 0; 359} 360 361void ppc440spe_setup_pcie(struct pci_controller *hose, int port) 362{ 363 void __iomem *mbase; 364 365 /* 366 * Map 16MB, which is enough for 4 bits of bus # 367 */ 368 hose->cfg_data = ioremap64(0xc40000000ull + port * 0x40000000, 369 1 << 24); 370 hose->ops = &pcie_pci_ops; 371 372 /* 373 * Set bus numbers on our root port 374 */ 375 mbase = ioremap64(0xc50000000ull + port * 0x40000000, 4096); 376 out_8(mbase + PCI_PRIMARY_BUS, 0); 377 out_8(mbase + PCI_SECONDARY_BUS, 0); 378 379 /* 380 * Set up outbound translation to hose->mem_space from PLB 381 * addresses at an offset of 0xd_0000_0000. We set the low 382 * bits of the mask to 11 to turn off splitting into 8 383 * subregions and to enable the outbound translation. 384 */ 385 out_le32(mbase + PECFG_POM0LAH, 0); 386 out_le32(mbase + PECFG_POM0LAL, hose->mem_space.start); 387 388 switch (port) { 389 case 0: 390 mtdcr(DCRN_PEGPL_OMR1BAH(PCIE0), 0x0000000d); 391 mtdcr(DCRN_PEGPL_OMR1BAL(PCIE0), hose->mem_space.start); 392 mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE0), 0x7fffffff); 393 mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE0), 394 ~(hose->mem_space.end - hose->mem_space.start) | 3); 395 break; 396 case 1: 397 mtdcr(DCRN_PEGPL_OMR1BAH(PCIE1), 0x0000000d); 398 mtdcr(DCRN_PEGPL_OMR1BAL(PCIE1), hose->mem_space.start); 399 mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE1), 0x7fffffff); 400 mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE1), 401 ~(hose->mem_space.end - hose->mem_space.start) | 3); 402 403 break; 404 case 2: 405 mtdcr(DCRN_PEGPL_OMR1BAH(PCIE2), 0x0000000d); 406 mtdcr(DCRN_PEGPL_OMR1BAL(PCIE2), hose->mem_space.start); 407 mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE2), 0x7fffffff); 408 mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE2), 409 ~(hose->mem_space.end - hose->mem_space.start) | 3); 410 break; 411 } 412 413 /* Set up 16GB inbound memory window at 0 */ 414 out_le32(mbase + PCI_BASE_ADDRESS_0, 0); 415 out_le32(mbase + PCI_BASE_ADDRESS_1, 0); 416 out_le32(mbase + PECFG_BAR0HMPA, 0x7fffffc); 417 out_le32(mbase + PECFG_BAR0LMPA, 0); 418 out_le32(mbase + PECFG_PIM0LAL, 0); 419 out_le32(mbase + PECFG_PIM0LAH, 0); 420 out_le32(mbase + PECFG_PIMEN, 0x1); 421 422 /* Enable I/O, Mem, and Busmaster cycles */ 423 out_le16(mbase + PCI_COMMAND, 424 in_le16(mbase + PCI_COMMAND) | 425 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); 426 427 iounmap(mbase); 428} 429