1/*
2 * A collection of structures, addresses, and values associated with
3 * the Motorola MPC8260ADS/MPC8266ADS-PCI boards.
4 * Copied from the RPX-Classic and SBS8260 stuff.
5 *
6 * Copyright (c) 2001 Dan Malek (dan@mvista.com)
7 */
8#ifdef __KERNEL__
9#ifndef __MACH_ADS8260_DEFS
10#define __MACH_ADS8260_DEFS
11
12
13#include <asm/ppcboot.h>
14
15#if defined(CONFIG_ADS8272)
16#define BOARD_CHIP_NAME "8272"
17#endif
18
19/* Memory map is configured by the PROM startup.
20 * We just map a few things we need.  The CSR is actually 4 byte-wide
21 * registers that can be accessed as 8-, 16-, or 32-bit values.
22 */
23#define CPM_MAP_ADDR		((uint)0xf0000000)
24#define BCSR_ADDR		((uint)0xf4500000)
25#define BCSR_SIZE		((uint)(32 * 1024))
26
27#define BOOTROM_RESTART_ADDR	((uint)0xff000104)
28
29/* For our show_cpuinfo hooks. */
30#define CPUINFO_VENDOR		"Motorola"
31#define CPUINFO_MACHINE		"PQ2 ADS PowerPC"
32
33/* The ADS8260 has 16, 32-bit wide control/status registers, accessed
34 * only on word boundaries.
35 * Not all are used (yet), or are interesting to us (yet).
36 */
37
38/* Things of interest in the CSR.
39*/
40#define BCSR0_LED0		((uint)0x02000000)	/* 0 == on */
41#define BCSR0_LED1		((uint)0x01000000)	/* 0 == on */
42#define BCSR1_FETHIEN		((uint)0x08000000)	/* 0 == enable */
43#define BCSR1_FETH_RST		((uint)0x04000000)	/* 0 == reset */
44#define BCSR1_RS232_EN1		((uint)0x02000000)	/* 0 == enable */
45#define BCSR1_RS232_EN2		((uint)0x01000000)	/* 0 == enable */
46#define BCSR3_FETHIEN2		((uint)0x10000000)	/* 0 == enable */
47#define BCSR3_FETH2_RST 	((uint)0x80000000)	/* 0 == reset */
48
49#define PHY_INTERRUPT	SIU_INT_IRQ7
50
51#ifdef CONFIG_PCI
52/* PCI interrupt controller */
53#define PCI_INT_STAT_REG	0xF8200000
54#define PCI_INT_MASK_REG	0xF8200004
55#define PIRQA			(NR_CPM_INTS + 0)
56#define PIRQB			(NR_CPM_INTS + 1)
57#define PIRQC			(NR_CPM_INTS + 2)
58#define PIRQD			(NR_CPM_INTS + 3)
59
60/*
61 * PCI memory map definitions for MPC8266ADS-PCI.
62 *
63 * processor view
64 *	local address		PCI address		target
65 *	0x80000000-0x9FFFFFFF	0x80000000-0x9FFFFFFF	PCI mem with prefetch
66 *	0xA0000000-0xBFFFFFFF	0xA0000000-0xBFFFFFFF	PCI mem w/o prefetch
67 *	0xF4000000-0xF7FFFFFF	0x00000000-0x03FFFFFF	PCI IO
68 *
69 * PCI master view
70 *	local address		PCI address		target
71 *	0x00000000-0x1FFFFFFF	0x00000000-0x1FFFFFFF	MPC8266 local memory
72 */
73
74/* All the other PCI memory map definitions reside at syslib/m82xx_pci.h
75   Here we should redefine what is unique for this board */
76#define M82xx_PCI_SLAVE_MEM_LOCAL	0x00000000	/* Local base */
77#define M82xx_PCI_SLAVE_MEM_BUS		0x00000000	/* PCI base */
78#define M82xx_PCI_SLAVE_MEM_SIZE	0x10000000	/* 256 Mb */
79
80#define M82xx_PCI_SLAVE_SEC_WND_SIZE	~(0x40000000 - 1U)	/* 2 x 512Mb  */
81#define M82xx_PCI_SLAVE_SEC_WND_BASE	0x80000000		/* PCI Memory base */
82
83#if defined(CONFIG_ADS8272)
84#define PCI_INT_TO_SIU 	SIU_INT_IRQ2
85#elif defined(CONFIG_PQ2FADS)
86#define PCI_INT_TO_SIU 	SIU_INT_IRQ6
87#else
88#warning PCI Bridge will be without interrupts support
89#endif
90
91#endif /* CONFIG_PCI */
92
93#endif /* __MACH_ADS8260_DEFS */
94#endif /* __KERNEL__ */
95