1/******************************************************************* 2* 3* Author: Xilinx, Inc. 4* 5* 6* This program is free software; you can redistribute it and/or modify it 7* under the terms of the GNU General Public License as published by the 8* Free Software Foundation; either version 2 of the License, or (at your 9* option) any later version. 10* 11* 12* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A 13* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS 14* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, 15* XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE 16* FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING 17* ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. 18* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO 19* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY 20* WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM 21* CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND 22* FITNESS FOR A PARTICULAR PURPOSE. 23* 24* 25* Xilinx hardware products are not intended for use in life support 26* appliances, devices, or systems. Use in such applications is 27* expressly prohibited. 28* 29* 30* (c) Copyright 2002-2004 Xilinx Inc. 31* All rights reserved. 32* 33* 34* You should have received a copy of the GNU General Public License along 35* with this program; if not, write to the Free Software Foundation, Inc., 36* 675 Mass Ave, Cambridge, MA 02139, USA. 37* 38* Description: Driver parameters 39* 40*******************************************************************/ 41 42#define XPAR_XPCI_NUM_INSTANCES 1 43#define XPAR_XPCI_CLOCK_HZ 33333333 44#define XPAR_OPB_PCI_REF_0_DEVICE_ID 0 45#define XPAR_OPB_PCI_REF_0_BASEADDR 0x20000000 46#define XPAR_OPB_PCI_REF_0_HIGHADDR 0x3FFFFFFF 47#define XPAR_OPB_PCI_REF_0_CONFIG_ADDR 0x3C000000 48#define XPAR_OPB_PCI_REF_0_CONFIG_DATA 0x3C000004 49#define XPAR_OPB_PCI_REF_0_LCONFIG_ADDR 0x3E000000 50#define XPAR_OPB_PCI_REF_0_MEM_BASEADDR 0x20000000 51#define XPAR_OPB_PCI_REF_0_MEM_HIGHADDR 0x37FFFFFF 52#define XPAR_OPB_PCI_REF_0_IO_BASEADDR 0x38000000 53#define XPAR_OPB_PCI_REF_0_IO_HIGHADDR 0x3BFFFFFF 54 55/******************************************************************/ 56 57#define XPAR_XEMAC_NUM_INSTANCES 1 58#define XPAR_OPB_ETHERNET_0_BASEADDR 0x60000000 59#define XPAR_OPB_ETHERNET_0_HIGHADDR 0x60003FFF 60#define XPAR_OPB_ETHERNET_0_DEVICE_ID 0 61#define XPAR_OPB_ETHERNET_0_ERR_COUNT_EXIST 1 62#define XPAR_OPB_ETHERNET_0_DMA_PRESENT 1 63#define XPAR_OPB_ETHERNET_0_MII_EXIST 1 64 65/******************************************************************/ 66 67#define XPAR_MY_OPB_GPIO_0_DEVICE_ID_0 0 68#define XPAR_MY_OPB_GPIO_0_BASEADDR_0 0x90000000 69#define XPAR_MY_OPB_GPIO_0_HIGHADDR_0 (0x90000000+0x7) 70#define XPAR_MY_OPB_GPIO_0_DEVICE_ID_1 1 71#define XPAR_MY_OPB_GPIO_0_BASEADDR_1 (0x90000000+0x8) 72#define XPAR_MY_OPB_GPIO_0_HIGHADDR_1 (0x90000000+0x1F) 73#define XPAR_XGPIO_NUM_INSTANCES 2 74 75/******************************************************************/ 76 77#define XPAR_XIIC_NUM_INSTANCES 1 78#define XPAR_OPB_IIC_0_BASEADDR 0xA8000000 79#define XPAR_OPB_IIC_0_HIGHADDR 0xA80001FF 80#define XPAR_OPB_IIC_0_DEVICE_ID 0 81#define XPAR_OPB_IIC_0_TEN_BIT_ADR 0 82 83/******************************************************************/ 84 85#define XPAR_XUARTNS550_NUM_INSTANCES 2 86#define XPAR_XUARTNS550_CLOCK_HZ 100000000 87#define XPAR_OPB_UART16550_0_BASEADDR 0xA0000000 88#define XPAR_OPB_UART16550_0_HIGHADDR 0xA0001FFF 89#define XPAR_OPB_UART16550_0_DEVICE_ID 0 90#define XPAR_OPB_UART16550_1_BASEADDR 0xA0010000 91#define XPAR_OPB_UART16550_1_HIGHADDR 0xA0011FFF 92#define XPAR_OPB_UART16550_1_DEVICE_ID 1 93 94/******************************************************************/ 95 96#define XPAR_XSPI_NUM_INSTANCES 1 97#define XPAR_OPB_SPI_0_BASEADDR 0xA4000000 98#define XPAR_OPB_SPI_0_HIGHADDR 0xA400007F 99#define XPAR_OPB_SPI_0_DEVICE_ID 0 100#define XPAR_OPB_SPI_0_FIFO_EXIST 1 101#define XPAR_OPB_SPI_0_SPI_SLAVE_ONLY 0 102#define XPAR_OPB_SPI_0_NUM_SS_BITS 1 103 104/******************************************************************/ 105 106#define XPAR_XPS2_NUM_INSTANCES 2 107#define XPAR_OPB_PS2_DUAL_REF_0_DEVICE_ID_0 0 108#define XPAR_OPB_PS2_DUAL_REF_0_BASEADDR_0 0xA9000000 109#define XPAR_OPB_PS2_DUAL_REF_0_HIGHADDR_0 (0xA9000000+0x3F) 110#define XPAR_OPB_PS2_DUAL_REF_0_DEVICE_ID_1 1 111#define XPAR_OPB_PS2_DUAL_REF_0_BASEADDR_1 (0xA9000000+0x1000) 112#define XPAR_OPB_PS2_DUAL_REF_0_HIGHADDR_1 (0xA9000000+0x103F) 113 114/******************************************************************/ 115 116#define XPAR_XTOUCHSCREEN_NUM_INSTANCES 1 117#define XPAR_OPB_TSD_REF_0_BASEADDR 0xAA000000 118#define XPAR_OPB_TSD_REF_0_HIGHADDR 0xAA000007 119#define XPAR_OPB_TSD_REF_0_DEVICE_ID 0 120 121/******************************************************************/ 122 123#define XPAR_OPB_AC97_CONTROLLER_REF_0_BASEADDR 0xA6000000 124#define XPAR_OPB_AC97_CONTROLLER_REF_0_HIGHADDR 0xA60000FF 125#define XPAR_OPB_PAR_PORT_REF_0_BASEADDR 0x90010000 126#define XPAR_OPB_PAR_PORT_REF_0_HIGHADDR 0x900100FF 127#define XPAR_PLB_DDR_0_BASEADDR 0x00000000 128#define XPAR_PLB_DDR_0_HIGHADDR 0x0FFFFFFF 129 130/******************************************************************/ 131 132#define XPAR_XINTC_HAS_IPR 1 133#define XPAR_INTC_MAX_NUM_INTR_INPUTS 18 134#define XPAR_XINTC_USE_DCR 0 135#define XPAR_XINTC_NUM_INSTANCES 1 136#define XPAR_DCR_INTC_0_BASEADDR 0xD0000FC0 137#define XPAR_DCR_INTC_0_HIGHADDR 0xD0000FDF 138#define XPAR_DCR_INTC_0_DEVICE_ID 0 139#define XPAR_DCR_INTC_0_KIND_OF_INTR 0x00038000 140 141/******************************************************************/ 142 143#define XPAR_DCR_INTC_0_MISC_LOGIC_0_PHY_MII_INT_INTR 0 144#define XPAR_DCR_INTC_0_OPB_ETHERNET_0_IP2INTC_IRPT_INTR 1 145#define XPAR_DCR_INTC_0_MISC_LOGIC_0_IIC_TEMP_CRIT_INTR 2 146#define XPAR_DCR_INTC_0_MISC_LOGIC_0_IIC_IRQ_INTR 3 147#define XPAR_DCR_INTC_0_OPB_IIC_0_IP2INTC_IRPT_INTR 4 148#define XPAR_DCR_INTC_0_OPB_SYSACE_0_SYSACE_IRQ_INTR 5 149#define XPAR_DCR_INTC_0_OPB_UART16550_0_IP2INTC_IRPT_INTR 6 150#define XPAR_DCR_INTC_0_OPB_UART16550_1_IP2INTC_IRPT_INTR 7 151#define XPAR_DCR_INTC_0_OPB_PS2_DUAL_REF_0_SYS_INTR1_INTR 8 152#define XPAR_DCR_INTC_0_OPB_PS2_DUAL_REF_0_SYS_INTR2_INTR 9 153#define XPAR_DCR_INTC_0_OPB_SPI_0_IP2INTC_IRPT_INTR 10 154#define XPAR_DCR_INTC_0_OPB_TSD_REF_0_INTR_INTR 11 155#define XPAR_DCR_INTC_0_OPB_AC97_CONTROLLER_REF_0_PLAYBACK_INTERRUPT_INTR 12 156#define XPAR_DCR_INTC_0_OPB_AC97_CONTROLLER_REF_0_RECORD_INTERRUPT_INTR 13 157#define XPAR_DCR_INTC_0_OPB_PCI_REF_0_INTR_OUT_INTR 14 158#define XPAR_DCR_INTC_0_PLB2OPB_BRIDGE_0_BUS_ERROR_DET_INTR 15 159#define XPAR_DCR_INTC_0_PLB_V34_0_BUS_ERROR_DET_INTR 16 160#define XPAR_DCR_INTC_0_OPB2PLB_BRIDGE_0_BUS_ERROR_DET_INTR 17 161 162/******************************************************************/ 163 164#define XPAR_XTFT_NUM_INSTANCES 1 165#define XPAR_PLB_TFT_CNTLR_REF_0_DCR_BASEADDR 0xD0000200 166#define XPAR_PLB_TFT_CNTLR_REF_0_DCR_HIGHADDR 0xD0000207 167#define XPAR_PLB_TFT_CNTLR_REF_0_DEVICE_ID 0 168 169/******************************************************************/ 170 171#define XPAR_XSYSACE_MEM_WIDTH 8 172#define XPAR_XSYSACE_NUM_INSTANCES 1 173#define XPAR_OPB_SYSACE_0_BASEADDR 0xCF000000 174#define XPAR_OPB_SYSACE_0_HIGHADDR 0xCF0001FF 175#define XPAR_OPB_SYSACE_0_DEVICE_ID 0 176#define XPAR_OPB_SYSACE_0_MEM_WIDTH 8 177 178/******************************************************************/ 179 180#define XPAR_CPU_PPC405_CORE_CLOCK_FREQ_HZ 300000000 181 182/******************************************************************/ 183 184/******************************************************************/ 185 186/* Linux Redefines */ 187 188/******************************************************************/ 189 190#define XPAR_UARTNS550_0_BASEADDR (XPAR_OPB_UART16550_0_BASEADDR+0x1000) 191#define XPAR_UARTNS550_0_HIGHADDR XPAR_OPB_UART16550_0_HIGHADDR 192#define XPAR_UARTNS550_0_CLOCK_FREQ_HZ XPAR_XUARTNS550_CLOCK_HZ 193#define XPAR_UARTNS550_0_DEVICE_ID XPAR_OPB_UART16550_0_DEVICE_ID 194#define XPAR_UARTNS550_1_BASEADDR (XPAR_OPB_UART16550_1_BASEADDR+0x1000) 195#define XPAR_UARTNS550_1_HIGHADDR XPAR_OPB_UART16550_1_HIGHADDR 196#define XPAR_UARTNS550_1_CLOCK_FREQ_HZ XPAR_XUARTNS550_CLOCK_HZ 197#define XPAR_UARTNS550_1_DEVICE_ID XPAR_OPB_UART16550_1_DEVICE_ID 198 199/******************************************************************/ 200 201#define XPAR_GPIO_0_BASEADDR XPAR_MY_OPB_GPIO_0_BASEADDR_0 202#define XPAR_GPIO_0_HIGHADDR XPAR_MY_OPB_GPIO_0_HIGHADDR_0 203#define XPAR_GPIO_0_DEVICE_ID XPAR_MY_OPB_GPIO_0_DEVICE_ID_0 204#define XPAR_GPIO_1_BASEADDR XPAR_MY_OPB_GPIO_0_BASEADDR_1 205#define XPAR_GPIO_1_HIGHADDR XPAR_MY_OPB_GPIO_0_HIGHADDR_1 206#define XPAR_GPIO_1_DEVICE_ID XPAR_MY_OPB_GPIO_0_DEVICE_ID_1 207 208/******************************************************************/ 209 210#define XPAR_IIC_0_BASEADDR XPAR_OPB_IIC_0_BASEADDR 211#define XPAR_IIC_0_HIGHADDR XPAR_OPB_IIC_0_HIGHADDR 212#define XPAR_IIC_0_TEN_BIT_ADR XPAR_OPB_IIC_0_TEN_BIT_ADR 213#define XPAR_IIC_0_DEVICE_ID XPAR_OPB_IIC_0_DEVICE_ID 214 215/******************************************************************/ 216 217#define XPAR_SYSACE_0_BASEADDR XPAR_OPB_SYSACE_0_BASEADDR 218#define XPAR_SYSACE_0_HIGHADDR XPAR_OPB_SYSACE_0_HIGHADDR 219#define XPAR_SYSACE_0_DEVICE_ID XPAR_OPB_SYSACE_0_DEVICE_ID 220 221/******************************************************************/ 222 223#define XPAR_INTC_0_BASEADDR XPAR_DCR_INTC_0_BASEADDR 224#define XPAR_INTC_0_HIGHADDR XPAR_DCR_INTC_0_HIGHADDR 225#define XPAR_INTC_0_KIND_OF_INTR XPAR_DCR_INTC_0_KIND_OF_INTR 226#define XPAR_INTC_0_DEVICE_ID XPAR_DCR_INTC_0_DEVICE_ID 227 228/******************************************************************/ 229 230#define XPAR_INTC_0_EMAC_0_VEC_ID XPAR_DCR_INTC_0_OPB_ETHERNET_0_IP2INTC_IRPT_INTR 231#define XPAR_INTC_0_IIC_0_VEC_ID XPAR_DCR_INTC_0_OPB_IIC_0_IP2INTC_IRPT_INTR 232#define XPAR_INTC_0_SYSACE_0_VEC_ID XPAR_DCR_INTC_0_OPB_SYSACE_0_SYSACE_IRQ_INTR 233#define XPAR_INTC_0_UARTNS550_0_VEC_ID XPAR_DCR_INTC_0_OPB_UART16550_0_IP2INTC_IRPT_INTR 234#define XPAR_INTC_0_UARTNS550_1_VEC_ID XPAR_DCR_INTC_0_OPB_UART16550_1_IP2INTC_IRPT_INTR 235#define XPAR_INTC_0_PS2_0_VEC_ID XPAR_DCR_INTC_0_OPB_PS2_DUAL_REF_0_SYS_INTR1_INTR 236#define XPAR_INTC_0_PS2_1_VEC_ID XPAR_DCR_INTC_0_OPB_PS2_DUAL_REF_0_SYS_INTR2_INTR 237#define XPAR_INTC_0_SPI_0_VEC_ID XPAR_DCR_INTC_0_OPB_SPI_0_IP2INTC_IRPT_INTR 238#define XPAR_INTC_0_TOUCHSCREEN_0_VEC_ID XPAR_DCR_INTC_0_OPB_TSD_REF_0_INTR_INTR 239#define XPAR_INTC_0_PCI_0_VEC_ID_A XPAR_DCR_INTC_0_OPB_PCI_REF_0_INTR_OUT_INTR 240#define XPAR_INTC_0_PCI_0_VEC_ID_B XPAR_DCR_INTC_0_OPB_PCI_REF_0_INTR_OUT_INTR 241#define XPAR_INTC_0_PCI_0_VEC_ID_C XPAR_DCR_INTC_0_OPB_PCI_REF_0_INTR_OUT_INTR 242#define XPAR_INTC_0_PCI_0_VEC_ID_D XPAR_DCR_INTC_0_OPB_PCI_REF_0_INTR_OUT_INTR 243 244/******************************************************************/ 245 246#define XPAR_EMAC_0_BASEADDR XPAR_OPB_ETHERNET_0_BASEADDR 247#define XPAR_EMAC_0_HIGHADDR XPAR_OPB_ETHERNET_0_HIGHADDR 248#define XPAR_EMAC_0_DMA_PRESENT XPAR_OPB_ETHERNET_0_DMA_PRESENT 249#define XPAR_EMAC_0_MII_EXIST XPAR_OPB_ETHERNET_0_MII_EXIST 250#define XPAR_EMAC_0_ERR_COUNT_EXIST XPAR_OPB_ETHERNET_0_ERR_COUNT_EXIST 251#define XPAR_EMAC_0_DEVICE_ID XPAR_OPB_ETHERNET_0_DEVICE_ID 252 253/******************************************************************/ 254 255#define XPAR_SPI_0_BASEADDR XPAR_OPB_SPI_0_BASEADDR 256#define XPAR_SPI_0_HIGHADDR XPAR_OPB_SPI_0_HIGHADDR 257#define XPAR_SPI_0_DEVICE_ID XPAR_OPB_SPI_0_DEVICE_ID 258 259/******************************************************************/ 260 261#define XPAR_TOUCHSCREEN_0_BASEADDR XPAR_OPB_TSD_REF_0_BASEADDR 262#define XPAR_TOUCHSCREEN_0_HIGHADDR XPAR_OPB_TSD_REF_0_HIGHADDR 263#define XPAR_TOUCHSCREEN_0_DEVICE_ID XPAR_OPB_TSD_REF_0_DEVICE_ID 264 265/******************************************************************/ 266 267#define XPAR_TFT_0_BASEADDR XPAR_PLB_TFT_CNTLR_REF_0_DCR_BASEADDR 268 269/******************************************************************/ 270 271#define XPAR_PCI_0_BASEADDR XPAR_OPB_PCI_REF_0_BASEADDR 272#define XPAR_PCI_0_HIGHADDR XPAR_OPB_PCI_REF_0_HIGHADDR 273#define XPAR_PCI_0_CONFIG_ADDR XPAR_OPB_PCI_REF_0_CONFIG_ADDR 274#define XPAR_PCI_0_CONFIG_DATA XPAR_OPB_PCI_REF_0_CONFIG_DATA 275#define XPAR_PCI_0_LCONFIG_ADDR XPAR_OPB_PCI_REF_0_LCONFIG_ADDR 276#define XPAR_PCI_0_MEM_BASEADDR XPAR_OPB_PCI_REF_0_MEM_BASEADDR 277#define XPAR_PCI_0_MEM_HIGHADDR XPAR_OPB_PCI_REF_0_MEM_HIGHADDR 278#define XPAR_PCI_0_IO_BASEADDR XPAR_OPB_PCI_REF_0_IO_BASEADDR 279#define XPAR_PCI_0_IO_HIGHADDR XPAR_OPB_PCI_REF_0_IO_HIGHADDR 280#define XPAR_PCI_0_CLOCK_FREQ_HZ XPAR_XPCI_CLOCK_HZ 281#define XPAR_PCI_0_DEVICE_ID XPAR_OPB_PCI_REF_0_DEVICE_ID 282 283/******************************************************************/ 284 285#define XPAR_PS2_0_BASEADDR XPAR_OPB_PS2_DUAL_REF_0_BASEADDR_0 286#define XPAR_PS2_0_HIGHADDR XPAR_OPB_PS2_DUAL_REF_0_HIGHADDR_0 287#define XPAR_PS2_0_DEVICE_ID XPAR_OPB_PS2_DUAL_REF_0_DEVICE_ID_0 288#define XPAR_PS2_1_BASEADDR XPAR_OPB_PS2_DUAL_REF_0_BASEADDR_1 289#define XPAR_PS2_1_HIGHADDR XPAR_OPB_PS2_DUAL_REF_0_HIGHADDR_1 290#define XPAR_PS2_1_DEVICE_ID XPAR_OPB_PS2_DUAL_REF_0_DEVICE_ID_1 291 292/******************************************************************/ 293 294#define XPAR_PLB_CLOCK_FREQ_HZ 100000000 295#define XPAR_CORE_CLOCK_FREQ_HZ XPAR_CPU_PPC405_CORE_CLOCK_FREQ_HZ 296#define XPAR_DDR_0_SIZE 0x08000000 297 298/******************************************************************/ 299 300#define XPAR_PERSISTENT_0_IIC_0_BASEADDR 0x00000400 301#define XPAR_PERSISTENT_0_IIC_0_HIGHADDR 0x000007FF 302#define XPAR_PERSISTENT_0_IIC_0_EEPROMADDR 0xA0 303 304/******************************************************************/ 305 306#define XPAR_POWER_0_POWERDOWN_BASEADDR 0x90000004 307#define XPAR_POWER_0_POWERDOWN_HIGHADDR 0x90000007 308#define XPAR_POWER_0_POWERDOWN_VALUE 0xFF 309 310/******************************************************************/ 311