1/*
2 *  Copyright (C) 1995  Linus Torvalds
3 *  Adapted from 'alpha' version by Gary Thomas
4 *  Modified by Cort Dougan (cort@cs.nmt.edu)
5 */
6
7/*
8 * bootup setup stuff..
9 */
10
11#include <linux/errno.h>
12#include <linux/sched.h>
13#include <linux/kernel.h>
14#include <linux/mm.h>
15#include <linux/stddef.h>
16#include <linux/unistd.h>
17#include <linux/ptrace.h>
18#include <linux/slab.h>
19#include <linux/user.h>
20#include <linux/a.out.h>
21#include <linux/tty.h>
22#include <linux/major.h>
23#include <linux/interrupt.h>
24#include <linux/reboot.h>
25#include <linux/init.h>
26#include <linux/pci.h>
27#include <linux/utsrelease.h>
28#include <linux/adb.h>
29#include <linux/module.h>
30#include <linux/delay.h>
31#include <linux/console.h>
32#include <linux/seq_file.h>
33#include <linux/root_dev.h>
34#include <linux/initrd.h>
35#include <linux/module.h>
36#include <linux/timer.h>
37
38#include <asm/io.h>
39#include <asm/pgtable.h>
40#include <asm/prom.h>
41#include <asm/gg2.h>
42#include <asm/pci-bridge.h>
43#include <asm/dma.h>
44#include <asm/machdep.h>
45#include <asm/irq.h>
46#include <asm/hydra.h>
47#include <asm/sections.h>
48#include <asm/time.h>
49#include <asm/i8259.h>
50#include <asm/mpic.h>
51#include <asm/rtas.h>
52#include <asm/xmon.h>
53
54#include "chrp.h"
55
56void rtas_indicator_progress(char *, unsigned short);
57
58int _chrp_type;
59EXPORT_SYMBOL(_chrp_type);
60
61static struct mpic *chrp_mpic;
62
63/* Used for doing CHRP event-scans */
64DEFINE_PER_CPU(struct timer_list, heartbeat_timer);
65unsigned long event_scan_interval;
66
67extern irqreturn_t xmon_irq(int, void *);
68
69extern unsigned long loops_per_jiffy;
70
71/* To be replaced by RTAS when available */
72static unsigned int __iomem *briq_SPOR;
73
74#ifdef CONFIG_SMP
75extern struct smp_ops_t chrp_smp_ops;
76#endif
77
78static const char *gg2_memtypes[4] = {
79	"FPM", "SDRAM", "EDO", "BEDO"
80};
81static const char *gg2_cachesizes[4] = {
82	"256 KB", "512 KB", "1 MB", "Reserved"
83};
84static const char *gg2_cachetypes[4] = {
85	"Asynchronous", "Reserved", "Flow-Through Synchronous",
86	"Pipelined Synchronous"
87};
88static const char *gg2_cachemodes[4] = {
89	"Disabled", "Write-Through", "Copy-Back", "Transparent Mode"
90};
91
92static const char *chrp_names[] = {
93	"Unknown",
94	"","","",
95	"Motorola",
96	"IBM or Longtrail",
97	"Genesi Pegasos",
98	"Total Impact Briq"
99};
100
101void chrp_show_cpuinfo(struct seq_file *m)
102{
103	int i, sdramen;
104	unsigned int t;
105	struct device_node *root;
106	const char *model = "";
107
108	root = of_find_node_by_path("/");
109	if (root)
110		model = of_get_property(root, "model", NULL);
111	seq_printf(m, "machine\t\t: CHRP %s\n", model);
112
113	/* longtrail (goldengate) stuff */
114	if (!strncmp(model, "IBM,LongTrail", 13)) {
115		/* VLSI VAS96011/12 `Golden Gate 2' */
116		/* Memory banks */
117		sdramen = (in_le32(gg2_pci_config_base + GG2_PCI_DRAM_CTRL)
118			   >>31) & 1;
119		for (i = 0; i < (sdramen ? 4 : 6); i++) {
120			t = in_le32(gg2_pci_config_base+
121						 GG2_PCI_DRAM_BANK0+
122						 i*4);
123			if (!(t & 1))
124				continue;
125			switch ((t>>8) & 0x1f) {
126			case 0x1f:
127				model = "4 MB";
128				break;
129			case 0x1e:
130				model = "8 MB";
131				break;
132			case 0x1c:
133				model = "16 MB";
134				break;
135			case 0x18:
136				model = "32 MB";
137				break;
138			case 0x10:
139				model = "64 MB";
140				break;
141			case 0x00:
142				model = "128 MB";
143				break;
144			default:
145				model = "Reserved";
146				break;
147			}
148			seq_printf(m, "memory bank %d\t: %s %s\n", i, model,
149				   gg2_memtypes[sdramen ? 1 : ((t>>1) & 3)]);
150		}
151		/* L2 cache */
152		t = in_le32(gg2_pci_config_base+GG2_PCI_CC_CTRL);
153		seq_printf(m, "board l2\t: %s %s (%s)\n",
154			   gg2_cachesizes[(t>>7) & 3],
155			   gg2_cachetypes[(t>>2) & 3],
156			   gg2_cachemodes[t & 3]);
157	}
158	of_node_put(root);
159}
160
161/*
162 *  Fixes for the National Semiconductor PC78308VUL SuperI/O
163 *
164 *  Some versions of Open Firmware incorrectly initialize the IRQ settings
165 *  for keyboard and mouse
166 */
167static inline void __init sio_write(u8 val, u8 index)
168{
169	outb(index, 0x15c);
170	outb(val, 0x15d);
171}
172
173static inline u8 __init sio_read(u8 index)
174{
175	outb(index, 0x15c);
176	return inb(0x15d);
177}
178
179static void __init sio_fixup_irq(const char *name, u8 device, u8 level,
180				     u8 type)
181{
182	u8 level0, type0, active;
183
184	/* select logical device */
185	sio_write(device, 0x07);
186	active = sio_read(0x30);
187	level0 = sio_read(0x70);
188	type0 = sio_read(0x71);
189	if (level0 != level || type0 != type || !active) {
190		printk(KERN_WARNING "sio: %s irq level %d, type %d, %sactive: "
191		       "remapping to level %d, type %d, active\n",
192		       name, level0, type0, !active ? "in" : "", level, type);
193		sio_write(0x01, 0x30);
194		sio_write(level, 0x70);
195		sio_write(type, 0x71);
196	}
197}
198
199static void __init sio_init(void)
200{
201	struct device_node *root;
202
203	if ((root = of_find_node_by_path("/")) &&
204	    !strncmp(of_get_property(root, "model", NULL),
205			"IBM,LongTrail", 13)) {
206		/* logical device 0 (KBC/Keyboard) */
207		sio_fixup_irq("keyboard", 0, 1, 2);
208		/* select logical device 1 (KBC/Mouse) */
209		sio_fixup_irq("mouse", 1, 12, 2);
210	}
211	of_node_put(root);
212}
213
214
215static void __init pegasos_set_l2cr(void)
216{
217	struct device_node *np;
218
219	/* On Pegasos, enable the l2 cache if needed, as the OF forgets it */
220	if (_chrp_type != _CHRP_Pegasos)
221		return;
222
223	/* Enable L2 cache if needed */
224	np = of_find_node_by_type(NULL, "cpu");
225	if (np != NULL) {
226		const unsigned int *l2cr = of_get_property(np, "l2cr", NULL);
227		if (l2cr == NULL) {
228			printk ("Pegasos l2cr : no cpu l2cr property found\n");
229			goto out;
230		}
231		if (!((*l2cr) & 0x80000000)) {
232			printk ("Pegasos l2cr : L2 cache was not active, "
233				"activating\n");
234			_set_L2CR(0);
235			_set_L2CR((*l2cr) | 0x80000000);
236		}
237	}
238out:
239	of_node_put(np);
240}
241
242static void briq_restart(char *cmd)
243{
244	local_irq_disable();
245	if (briq_SPOR)
246		out_be32(briq_SPOR, 0);
247	for(;;);
248}
249
250void __init chrp_setup_arch(void)
251{
252	struct device_node *root = of_find_node_by_path("/");
253	const char *machine = NULL;
254
255	/* init to some ~sane value until calibrate_delay() runs */
256	loops_per_jiffy = 50000000/HZ;
257
258	if (root)
259		machine = of_get_property(root, "model", NULL);
260	if (machine && strncmp(machine, "Pegasos", 7) == 0) {
261		_chrp_type = _CHRP_Pegasos;
262	} else if (machine && strncmp(machine, "IBM", 3) == 0) {
263		_chrp_type = _CHRP_IBM;
264	} else if (machine && strncmp(machine, "MOT", 3) == 0) {
265		_chrp_type = _CHRP_Motorola;
266	} else if (machine && strncmp(machine, "TotalImpact,BRIQ-1", 18) == 0) {
267		_chrp_type = _CHRP_briq;
268		/* Map the SPOR register on briq and change the restart hook */
269		briq_SPOR = ioremap(0xff0000e8, 4);
270		ppc_md.restart = briq_restart;
271	} else {
272		/* Let's assume it is an IBM chrp if all else fails */
273		_chrp_type = _CHRP_IBM;
274	}
275	of_node_put(root);
276	printk("chrp type = %x [%s]\n", _chrp_type, chrp_names[_chrp_type]);
277
278	rtas_initialize();
279	if (rtas_token("display-character") >= 0)
280		ppc_md.progress = rtas_progress;
281
282	/* use RTAS time-of-day routines if available */
283	if (rtas_token("get-time-of-day") != RTAS_UNKNOWN_SERVICE) {
284		ppc_md.get_boot_time	= rtas_get_boot_time;
285		ppc_md.get_rtc_time	= rtas_get_rtc_time;
286		ppc_md.set_rtc_time	= rtas_set_rtc_time;
287	}
288
289#ifdef CONFIG_BLK_DEV_INITRD
290	/* this is fine for chrp */
291	initrd_below_start_ok = 1;
292
293	if (initrd_start)
294		ROOT_DEV = Root_RAM0;
295	else
296#endif
297		ROOT_DEV = Root_SDA2; /* sda2 (sda1 is for the kernel) */
298
299	/* On pegasos, enable the L2 cache if not already done by OF */
300	pegasos_set_l2cr();
301
302	/* Lookup PCI host bridges */
303	chrp_find_bridges();
304
305	/*
306	 *  Temporary fixes for PCI devices.
307	 *  -- Geert
308	 */
309	hydra_init();		/* Mac I/O */
310
311	/*
312	 *  Fix the Super I/O configuration
313	 */
314	sio_init();
315
316	pci_create_OF_bus_map();
317
318	/*
319	 * Print the banner, then scroll down so boot progress
320	 * can be printed.  -- Cort
321	 */
322	if (ppc_md.progress) ppc_md.progress("Linux/PPC "UTS_RELEASE"\n", 0x0);
323}
324
325void
326chrp_event_scan(unsigned long unused)
327{
328	unsigned char log[1024];
329	int ret = 0;
330
331	rtas_call(rtas_token("event-scan"), 4, 1, &ret, 0xffffffff, 0,
332		  __pa(log), 1024);
333	mod_timer(&__get_cpu_var(heartbeat_timer),
334		  jiffies + event_scan_interval);
335}
336
337static void chrp_8259_cascade(unsigned int irq, struct irq_desc *desc)
338{
339	unsigned int cascade_irq = i8259_irq();
340	if (cascade_irq != NO_IRQ)
341		generic_handle_irq(cascade_irq);
342	desc->chip->eoi(irq);
343}
344
345/*
346 * Finds the open-pic node and sets up the mpic driver.
347 */
348static void __init chrp_find_openpic(void)
349{
350	struct device_node *np, *root;
351	int len, i, j;
352	int isu_size, idu_size;
353	const unsigned int *iranges, *opprop = NULL;
354	int oplen = 0;
355	unsigned long opaddr;
356	int na = 1;
357
358	np = of_find_node_by_type(NULL, "open-pic");
359	if (np == NULL)
360		return;
361	root = of_find_node_by_path("/");
362	if (root) {
363		opprop = of_get_property(root, "platform-open-pic", &oplen);
364		na = of_n_addr_cells(root);
365	}
366	if (opprop && oplen >= na * sizeof(unsigned int)) {
367		opaddr = opprop[na-1];	/* assume 32-bit */
368		oplen /= na * sizeof(unsigned int);
369	} else {
370		struct resource r;
371		if (of_address_to_resource(np, 0, &r)) {
372			goto bail;
373		}
374		opaddr = r.start;
375		oplen = 0;
376	}
377
378	printk(KERN_INFO "OpenPIC at %lx\n", opaddr);
379
380	iranges = of_get_property(np, "interrupt-ranges", &len);
381	if (iranges == NULL)
382		len = 0;	/* non-distributed mpic */
383	else
384		len /= 2 * sizeof(unsigned int);
385
386	/*
387	 * The first pair of cells in interrupt-ranges refers to the
388	 * IDU; subsequent pairs refer to the ISUs.
389	 */
390	if (oplen < len) {
391		printk(KERN_ERR "Insufficient addresses for distributed"
392		       " OpenPIC (%d < %d)\n", oplen, len);
393		len = oplen;
394	}
395
396	isu_size = 0;
397	idu_size = 0;
398	if (len > 0 && iranges[1] != 0) {
399		printk(KERN_INFO "OpenPIC irqs %d..%d in IDU\n",
400		       iranges[0], iranges[0] + iranges[1] - 1);
401		idu_size = iranges[1];
402	}
403	if (len > 1)
404		isu_size = iranges[3];
405
406	chrp_mpic = mpic_alloc(np, opaddr, MPIC_PRIMARY,
407			       isu_size, 0, " MPIC    ");
408	if (chrp_mpic == NULL) {
409		printk(KERN_ERR "Failed to allocate MPIC structure\n");
410		goto bail;
411	}
412	j = na - 1;
413	for (i = 1; i < len; ++i) {
414		iranges += 2;
415		j += na;
416		printk(KERN_INFO "OpenPIC irqs %d..%d in ISU at %x\n",
417		       iranges[0], iranges[0] + iranges[1] - 1,
418		       opprop[j]);
419		mpic_assign_isu(chrp_mpic, i - 1, opprop[j]);
420	}
421
422	mpic_init(chrp_mpic);
423	ppc_md.get_irq = mpic_get_irq;
424 bail:
425	of_node_put(root);
426	of_node_put(np);
427}
428
429#if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(CONFIG_XMON)
430static struct irqaction xmon_irqaction = {
431	.handler = xmon_irq,
432	.mask = CPU_MASK_NONE,
433	.name = "XMON break",
434};
435#endif
436
437static void __init chrp_find_8259(void)
438{
439	struct device_node *np, *pic = NULL;
440	unsigned long chrp_int_ack = 0;
441	unsigned int cascade_irq;
442
443	/* Look for cascade */
444	for_each_node_by_type(np, "interrupt-controller")
445		if (of_device_is_compatible(np, "chrp,iic")) {
446			pic = np;
447			break;
448		}
449	/* Ok, 8259 wasn't found. We need to handle the case where
450	 * we have a pegasos that claims to be chrp but doesn't have
451	 * a proper interrupt tree
452	 */
453	if (pic == NULL && chrp_mpic != NULL) {
454		printk(KERN_ERR "i8259: Not found in device-tree"
455		       " assuming no legacy interrupts\n");
456		return;
457	}
458
459	/* Look for intack. In a perfect world, we would look for it on
460	 * the ISA bus that holds the 8259 but heh... Works that way. If
461	 * we ever see a problem, we can try to re-use the pSeries code here.
462	 * Also, Pegasos-type platforms don't have a proper node to start
463	 * from anyway
464	 */
465	for_each_node_by_name(np, "pci") {
466		const unsigned int *addrp = of_get_property(np,
467				"8259-interrupt-acknowledge", NULL);
468
469		if (addrp == NULL)
470			continue;
471		chrp_int_ack = addrp[of_n_addr_cells(np)-1];
472		break;
473	}
474	of_node_put(np);
475	if (np == NULL)
476		printk(KERN_WARNING "Cannot find PCI interrupt acknowledge"
477		       " address, polling\n");
478
479	i8259_init(pic, chrp_int_ack);
480	if (ppc_md.get_irq == NULL) {
481		ppc_md.get_irq = i8259_irq;
482		irq_set_default_host(i8259_get_host());
483	}
484	if (chrp_mpic != NULL) {
485		cascade_irq = irq_of_parse_and_map(pic, 0);
486		if (cascade_irq == NO_IRQ)
487			printk(KERN_ERR "i8259: failed to map cascade irq\n");
488		else
489			set_irq_chained_handler(cascade_irq,
490						chrp_8259_cascade);
491	}
492}
493
494void __init chrp_init_IRQ(void)
495{
496#if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(CONFIG_XMON)
497	struct device_node *kbd;
498#endif
499	chrp_find_openpic();
500	chrp_find_8259();
501
502#ifdef CONFIG_SMP
503	/* Pegasos has no MPIC, those ops would make it crash. It might be an
504	 * option to move setting them to after we probe the PIC though
505	 */
506	if (chrp_mpic != NULL)
507		smp_ops = &chrp_smp_ops;
508#endif /* CONFIG_SMP */
509
510	if (_chrp_type == _CHRP_Pegasos)
511		ppc_md.get_irq        = i8259_irq;
512
513#if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(CONFIG_XMON)
514	/* see if there is a keyboard in the device tree
515	   with a parent of type "adb" */
516	for_each_node_by_name(kbd, "keyboard")
517		if (kbd->parent && kbd->parent->type
518		    && strcmp(kbd->parent->type, "adb") == 0)
519			break;
520	of_node_put(kbd);
521	if (kbd)
522		setup_irq(HYDRA_INT_ADB_NMI, &xmon_irqaction);
523#endif
524}
525
526void __init
527chrp_init2(void)
528{
529	struct device_node *device;
530	const unsigned int *p = NULL;
531
532#ifdef CONFIG_NVRAM
533	chrp_nvram_init();
534#endif
535
536	request_region(0x20,0x20,"pic1");
537	request_region(0xa0,0x20,"pic2");
538	request_region(0x00,0x20,"dma1");
539	request_region(0x40,0x20,"timer");
540	request_region(0x80,0x10,"dma page reg");
541	request_region(0xc0,0x20,"dma2");
542
543	/* Get the event scan rate for the rtas so we know how
544	 * often it expects a heartbeat. -- Cort
545	 */
546	device = of_find_node_by_name(NULL, "rtas");
547	if (device)
548		p = of_get_property(device, "rtas-event-scan-rate", NULL);
549	if (p && *p) {
550		/*
551		 * Arrange to call chrp_event_scan at least *p times
552		 * per minute.  We use 59 rather than 60 here so that
553		 * the rate will be slightly higher than the minimum.
554		 * This all assumes we don't do hotplug CPU on any
555		 * machine that needs the event scans done.
556		 */
557		unsigned long interval, offset;
558		int cpu, ncpus;
559		struct timer_list *timer;
560
561		interval = HZ * 59 / *p;
562		offset = HZ;
563		ncpus = num_online_cpus();
564		event_scan_interval = ncpus * interval;
565		for (cpu = 0; cpu < ncpus; ++cpu) {
566			timer = &per_cpu(heartbeat_timer, cpu);
567			setup_timer(timer, chrp_event_scan, 0);
568			timer->expires = jiffies + offset;
569			add_timer_on(timer, cpu);
570			offset += interval;
571		}
572		printk("RTAS Event Scan Rate: %u (%lu jiffies)\n",
573		       *p, interval);
574	}
575	of_node_put(device);
576
577	if (ppc_md.progress)
578		ppc_md.progress("  Have fun!    ", 0x7777);
579}
580
581static int __init chrp_probe(void)
582{
583 	char *dtype = of_get_flat_dt_prop(of_get_flat_dt_root(),
584 					  "device_type", NULL);
585 	if (dtype == NULL)
586 		return 0;
587 	if (strcmp(dtype, "chrp"))
588		return 0;
589
590	ISA_DMA_THRESHOLD = ~0L;
591	DMA_MODE_READ = 0x44;
592	DMA_MODE_WRITE = 0x48;
593
594	return 1;
595}
596
597define_machine(chrp) {
598	.name			= "CHRP",
599	.probe			= chrp_probe,
600	.setup_arch		= chrp_setup_arch,
601	.init			= chrp_init2,
602	.show_cpuinfo		= chrp_show_cpuinfo,
603	.init_IRQ		= chrp_init_IRQ,
604	.restart		= rtas_restart,
605	.power_off		= rtas_power_off,
606	.halt			= rtas_halt,
607	.time_init		= chrp_time_init,
608	.set_rtc_time		= chrp_set_rtc_time,
609	.get_rtc_time		= chrp_get_rtc_time,
610	.calibrate_decr		= generic_calibrate_decr,
611	.phys_mem_access_prot	= pci_phys_mem_access_prot,
612};
613