1/* 2 * IOMMU implementation for Cell Broadband Processor Architecture 3 * 4 * (C) Copyright IBM Corporation 2006 5 * 6 * Author: Jeremy Kerr <jk@ozlabs.org> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2, or (at your option) 11 * any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 21 */ 22 23#undef DEBUG 24 25#include <linux/kernel.h> 26#include <linux/init.h> 27#include <linux/interrupt.h> 28#include <linux/notifier.h> 29 30#include <asm/prom.h> 31#include <asm/iommu.h> 32#include <asm/machdep.h> 33#include <asm/pci-bridge.h> 34#include <asm/udbg.h> 35#include <asm/of_platform.h> 36#include <asm/lmb.h> 37 38#include "cbe_regs.h" 39#include "interrupt.h" 40 41/* Define CELL_IOMMU_REAL_UNMAP to actually unmap non-used pages 42 * instead of leaving them mapped to some dummy page. This can be 43 * enabled once the appropriate workarounds for spider bugs have 44 * been enabled 45 */ 46#define CELL_IOMMU_REAL_UNMAP 47 48/* Define CELL_IOMMU_STRICT_PROTECTION to enforce protection of 49 * IO PTEs based on the transfer direction. That can be enabled 50 * once spider-net has been fixed to pass the correct direction 51 * to the DMA mapping functions 52 */ 53#define CELL_IOMMU_STRICT_PROTECTION 54 55 56#define NR_IOMMUS 2 57 58/* IOC mmap registers */ 59#define IOC_Reg_Size 0x2000 60 61#define IOC_IOPT_CacheInvd 0x908 62#define IOC_IOPT_CacheInvd_NE_Mask 0xffe0000000000000ul 63#define IOC_IOPT_CacheInvd_IOPTE_Mask 0x000003fffffffff8ul 64#define IOC_IOPT_CacheInvd_Busy 0x0000000000000001ul 65 66#define IOC_IOST_Origin 0x918 67#define IOC_IOST_Origin_E 0x8000000000000000ul 68#define IOC_IOST_Origin_HW 0x0000000000000800ul 69#define IOC_IOST_Origin_HL 0x0000000000000400ul 70 71#define IOC_IO_ExcpStat 0x920 72#define IOC_IO_ExcpStat_V 0x8000000000000000ul 73#define IOC_IO_ExcpStat_SPF_Mask 0x6000000000000000ul 74#define IOC_IO_ExcpStat_SPF_S 0x6000000000000000ul 75#define IOC_IO_ExcpStat_SPF_P 0x4000000000000000ul 76#define IOC_IO_ExcpStat_ADDR_Mask 0x00000007fffff000ul 77#define IOC_IO_ExcpStat_RW_Mask 0x0000000000000800ul 78#define IOC_IO_ExcpStat_IOID_Mask 0x00000000000007fful 79 80#define IOC_IO_ExcpMask 0x928 81#define IOC_IO_ExcpMask_SFE 0x4000000000000000ul 82#define IOC_IO_ExcpMask_PFE 0x2000000000000000ul 83 84#define IOC_IOCmd_Offset 0x1000 85 86#define IOC_IOCmd_Cfg 0xc00 87#define IOC_IOCmd_Cfg_TE 0x0000800000000000ul 88 89 90/* Segment table entries */ 91#define IOSTE_V 0x8000000000000000ul /* valid */ 92#define IOSTE_H 0x4000000000000000ul /* cache hint */ 93#define IOSTE_PT_Base_RPN_Mask 0x3ffffffffffff000ul /* base RPN of IOPT */ 94#define IOSTE_NPPT_Mask 0x0000000000000fe0ul /* no. pages in IOPT */ 95#define IOSTE_PS_Mask 0x0000000000000007ul /* page size */ 96#define IOSTE_PS_4K 0x0000000000000001ul /* - 4kB */ 97#define IOSTE_PS_64K 0x0000000000000003ul /* - 64kB */ 98#define IOSTE_PS_1M 0x0000000000000005ul /* - 1MB */ 99#define IOSTE_PS_16M 0x0000000000000007ul /* - 16MB */ 100 101/* Page table entries */ 102#define IOPTE_PP_W 0x8000000000000000ul /* protection: write */ 103#define IOPTE_PP_R 0x4000000000000000ul /* protection: read */ 104#define IOPTE_M 0x2000000000000000ul /* coherency required */ 105#define IOPTE_SO_R 0x1000000000000000ul /* ordering: writes */ 106#define IOPTE_SO_RW 0x1800000000000000ul /* ordering: r & w */ 107#define IOPTE_RPN_Mask 0x07fffffffffff000ul /* RPN */ 108#define IOPTE_H 0x0000000000000800ul /* cache hint */ 109#define IOPTE_IOID_Mask 0x00000000000007fful /* ioid */ 110 111 112/* IOMMU sizing */ 113#define IO_SEGMENT_SHIFT 28 114#define IO_PAGENO_BITS (IO_SEGMENT_SHIFT - IOMMU_PAGE_SHIFT) 115 116/* The high bit needs to be set on every DMA address */ 117#define SPIDER_DMA_OFFSET 0x80000000ul 118 119struct iommu_window { 120 struct list_head list; 121 struct cbe_iommu *iommu; 122 unsigned long offset; 123 unsigned long size; 124 unsigned long pte_offset; 125 unsigned int ioid; 126 struct iommu_table table; 127}; 128 129#define NAMESIZE 8 130struct cbe_iommu { 131 int nid; 132 char name[NAMESIZE]; 133 void __iomem *xlate_regs; 134 void __iomem *cmd_regs; 135 unsigned long *stab; 136 unsigned long *ptab; 137 void *pad_page; 138 struct list_head windows; 139}; 140 141/* Static array of iommus, one per node 142 * each contains a list of windows, keyed from dma_window property 143 * - on bus setup, look for a matching window, or create one 144 * - on dev setup, assign iommu_table ptr 145 */ 146static struct cbe_iommu iommus[NR_IOMMUS]; 147static int cbe_nr_iommus; 148 149static void invalidate_tce_cache(struct cbe_iommu *iommu, unsigned long *pte, 150 long n_ptes) 151{ 152 unsigned long __iomem *reg; 153 unsigned long val; 154 long n; 155 156 reg = iommu->xlate_regs + IOC_IOPT_CacheInvd; 157 158 while (n_ptes > 0) { 159 /* we can invalidate up to 1 << 11 PTEs at once */ 160 n = min(n_ptes, 1l << 11); 161 val = (((n /*- 1*/) << 53) & IOC_IOPT_CacheInvd_NE_Mask) 162 | (__pa(pte) & IOC_IOPT_CacheInvd_IOPTE_Mask) 163 | IOC_IOPT_CacheInvd_Busy; 164 165 out_be64(reg, val); 166 while (in_be64(reg) & IOC_IOPT_CacheInvd_Busy) 167 ; 168 169 n_ptes -= n; 170 pte += n; 171 } 172} 173 174static void tce_build_cell(struct iommu_table *tbl, long index, long npages, 175 unsigned long uaddr, enum dma_data_direction direction) 176{ 177 int i; 178 unsigned long *io_pte, base_pte; 179 struct iommu_window *window = 180 container_of(tbl, struct iommu_window, table); 181 182 /* implementing proper protection causes problems with the spidernet 183 * driver - check mapping directions later, but allow read & write by 184 * default for now.*/ 185#ifdef CELL_IOMMU_STRICT_PROTECTION 186 /* to avoid referencing a global, we use a trick here to setup the 187 * protection bit. "prot" is setup to be 3 fields of 4 bits apprended 188 * together for each of the 3 supported direction values. It is then 189 * shifted left so that the fields matching the desired direction 190 * lands on the appropriate bits, and other bits are masked out. 191 */ 192 const unsigned long prot = 0xc48; 193 base_pte = 194 ((prot << (52 + 4 * direction)) & (IOPTE_PP_W | IOPTE_PP_R)) 195 | IOPTE_M | IOPTE_SO_RW | (window->ioid & IOPTE_IOID_Mask); 196#else 197 base_pte = IOPTE_PP_W | IOPTE_PP_R | IOPTE_M | IOPTE_SO_RW | 198 (window->ioid & IOPTE_IOID_Mask); 199#endif 200 201 io_pte = (unsigned long *)tbl->it_base + (index - window->pte_offset); 202 203 for (i = 0; i < npages; i++, uaddr += IOMMU_PAGE_SIZE) 204 io_pte[i] = base_pte | (__pa(uaddr) & IOPTE_RPN_Mask); 205 206 mb(); 207 208 invalidate_tce_cache(window->iommu, io_pte, npages); 209 210 pr_debug("tce_build_cell(index=%lx,n=%lx,dir=%d,base_pte=%lx)\n", 211 index, npages, direction, base_pte); 212} 213 214static void tce_free_cell(struct iommu_table *tbl, long index, long npages) 215{ 216 217 int i; 218 unsigned long *io_pte, pte; 219 struct iommu_window *window = 220 container_of(tbl, struct iommu_window, table); 221 222 pr_debug("tce_free_cell(index=%lx,n=%lx)\n", index, npages); 223 224#ifdef CELL_IOMMU_REAL_UNMAP 225 pte = 0; 226#else 227 /* spider bridge does PCI reads after freeing - insert a mapping 228 * to a scratch page instead of an invalid entry */ 229 pte = IOPTE_PP_R | IOPTE_M | IOPTE_SO_RW | __pa(window->iommu->pad_page) 230 | (window->ioid & IOPTE_IOID_Mask); 231#endif 232 233 io_pte = (unsigned long *)tbl->it_base + (index - window->pte_offset); 234 235 for (i = 0; i < npages; i++) 236 io_pte[i] = pte; 237 238 mb(); 239 240 invalidate_tce_cache(window->iommu, io_pte, npages); 241} 242 243static irqreturn_t ioc_interrupt(int irq, void *data) 244{ 245 unsigned long stat; 246 struct cbe_iommu *iommu = data; 247 248 stat = in_be64(iommu->xlate_regs + IOC_IO_ExcpStat); 249 250 /* Might want to rate limit it */ 251 printk(KERN_ERR "iommu: DMA exception 0x%016lx\n", stat); 252 printk(KERN_ERR " V=%d, SPF=[%c%c], RW=%s, IOID=0x%04x\n", 253 !!(stat & IOC_IO_ExcpStat_V), 254 (stat & IOC_IO_ExcpStat_SPF_S) ? 'S' : ' ', 255 (stat & IOC_IO_ExcpStat_SPF_P) ? 'P' : ' ', 256 (stat & IOC_IO_ExcpStat_RW_Mask) ? "Read" : "Write", 257 (unsigned int)(stat & IOC_IO_ExcpStat_IOID_Mask)); 258 printk(KERN_ERR " page=0x%016lx\n", 259 stat & IOC_IO_ExcpStat_ADDR_Mask); 260 261 /* clear interrupt */ 262 stat &= ~IOC_IO_ExcpStat_V; 263 out_be64(iommu->xlate_regs + IOC_IO_ExcpStat, stat); 264 265 return IRQ_HANDLED; 266} 267 268static int cell_iommu_find_ioc(int nid, unsigned long *base) 269{ 270 struct device_node *np; 271 struct resource r; 272 273 *base = 0; 274 275 /* First look for new style /be nodes */ 276 for_each_node_by_name(np, "ioc") { 277 if (of_node_to_nid(np) != nid) 278 continue; 279 if (of_address_to_resource(np, 0, &r)) { 280 printk(KERN_ERR "iommu: can't get address for %s\n", 281 np->full_name); 282 continue; 283 } 284 *base = r.start; 285 of_node_put(np); 286 return 0; 287 } 288 289 /* Ok, let's try the old way */ 290 for_each_node_by_type(np, "cpu") { 291 const unsigned int *nidp; 292 const unsigned long *tmp; 293 294 nidp = of_get_property(np, "node-id", NULL); 295 if (nidp && *nidp == nid) { 296 tmp = of_get_property(np, "ioc-translation", NULL); 297 if (tmp) { 298 *base = *tmp; 299 of_node_put(np); 300 return 0; 301 } 302 } 303 } 304 305 return -ENODEV; 306} 307 308static void cell_iommu_setup_hardware(struct cbe_iommu *iommu, unsigned long size) 309{ 310 struct page *page; 311 int ret, i; 312 unsigned long reg, segments, pages_per_segment, ptab_size, n_pte_pages; 313 unsigned long xlate_base; 314 unsigned int virq; 315 316 if (cell_iommu_find_ioc(iommu->nid, &xlate_base)) 317 panic("%s: missing IOC register mappings for node %d\n", 318 __FUNCTION__, iommu->nid); 319 320 iommu->xlate_regs = ioremap(xlate_base, IOC_Reg_Size); 321 iommu->cmd_regs = iommu->xlate_regs + IOC_IOCmd_Offset; 322 323 segments = size >> IO_SEGMENT_SHIFT; 324 pages_per_segment = 1ull << IO_PAGENO_BITS; 325 326 pr_debug("%s: iommu[%d]: segments: %lu, pages per segment: %lu\n", 327 __FUNCTION__, iommu->nid, segments, pages_per_segment); 328 329 /* set up the segment table */ 330 page = alloc_pages_node(iommu->nid, GFP_KERNEL, 0); 331 BUG_ON(!page); 332 iommu->stab = page_address(page); 333 clear_page(iommu->stab); 334 335 /* ... and the page tables. Since these are contiguous, we can treat 336 * the page tables as one array of ptes, like pSeries does. 337 */ 338 ptab_size = segments * pages_per_segment * sizeof(unsigned long); 339 pr_debug("%s: iommu[%d]: ptab_size: %lu, order: %d\n", __FUNCTION__, 340 iommu->nid, ptab_size, get_order(ptab_size)); 341 page = alloc_pages_node(iommu->nid, GFP_KERNEL, get_order(ptab_size)); 342 BUG_ON(!page); 343 344 iommu->ptab = page_address(page); 345 memset(iommu->ptab, 0, ptab_size); 346 347 /* allocate a bogus page for the end of each mapping */ 348 page = alloc_pages_node(iommu->nid, GFP_KERNEL, 0); 349 BUG_ON(!page); 350 iommu->pad_page = page_address(page); 351 clear_page(iommu->pad_page); 352 353 /* number of pages needed for a page table */ 354 n_pte_pages = (pages_per_segment * 355 sizeof(unsigned long)) >> IOMMU_PAGE_SHIFT; 356 357 pr_debug("%s: iommu[%d]: stab at %p, ptab at %p, n_pte_pages: %lu\n", 358 __FUNCTION__, iommu->nid, iommu->stab, iommu->ptab, 359 n_pte_pages); 360 361 /* initialise the STEs */ 362 reg = IOSTE_V | ((n_pte_pages - 1) << 5); 363 364 if (IOMMU_PAGE_SIZE == 0x1000) 365 reg |= IOSTE_PS_4K; 366 else if (IOMMU_PAGE_SIZE == 0x10000) 367 reg |= IOSTE_PS_64K; 368 else { 369 extern void __unknown_page_size_error(void); 370 __unknown_page_size_error(); 371 } 372 373 pr_debug("Setting up IOMMU stab:\n"); 374 for (i = 0; i * (1ul << IO_SEGMENT_SHIFT) < size; i++) { 375 iommu->stab[i] = reg | 376 (__pa(iommu->ptab) + n_pte_pages * IOMMU_PAGE_SIZE * i); 377 pr_debug("\t[%d] 0x%016lx\n", i, iommu->stab[i]); 378 } 379 380 /* ensure that the STEs have updated */ 381 mb(); 382 383 /* setup interrupts for the iommu. */ 384 reg = in_be64(iommu->xlate_regs + IOC_IO_ExcpStat); 385 out_be64(iommu->xlate_regs + IOC_IO_ExcpStat, 386 reg & ~IOC_IO_ExcpStat_V); 387 out_be64(iommu->xlate_regs + IOC_IO_ExcpMask, 388 IOC_IO_ExcpMask_PFE | IOC_IO_ExcpMask_SFE); 389 390 virq = irq_create_mapping(NULL, 391 IIC_IRQ_IOEX_ATI | (iommu->nid << IIC_IRQ_NODE_SHIFT)); 392 BUG_ON(virq == NO_IRQ); 393 394 ret = request_irq(virq, ioc_interrupt, IRQF_DISABLED, 395 iommu->name, iommu); 396 BUG_ON(ret); 397 398 /* set the IOC segment table origin register (and turn on the iommu) */ 399 reg = IOC_IOST_Origin_E | __pa(iommu->stab) | IOC_IOST_Origin_HW; 400 out_be64(iommu->xlate_regs + IOC_IOST_Origin, reg); 401 in_be64(iommu->xlate_regs + IOC_IOST_Origin); 402 403 /* turn on IO translation */ 404 reg = in_be64(iommu->cmd_regs + IOC_IOCmd_Cfg) | IOC_IOCmd_Cfg_TE; 405 out_be64(iommu->cmd_regs + IOC_IOCmd_Cfg, reg); 406} 407 408 409static struct iommu_window * __init 410cell_iommu_setup_window(struct cbe_iommu *iommu, struct device_node *np, 411 unsigned long offset, unsigned long size, 412 unsigned long pte_offset) 413{ 414 struct iommu_window *window; 415 const unsigned int *ioid; 416 417 ioid = of_get_property(np, "ioid", NULL); 418 if (ioid == NULL) 419 printk(KERN_WARNING "iommu: missing ioid for %s using 0\n", 420 np->full_name); 421 422 window = kmalloc_node(sizeof(*window), GFP_KERNEL, iommu->nid); 423 BUG_ON(window == NULL); 424 425 window->offset = offset; 426 window->size = size; 427 window->ioid = ioid ? *ioid : 0; 428 window->iommu = iommu; 429 window->pte_offset = pte_offset; 430 431 window->table.it_blocksize = 16; 432 window->table.it_base = (unsigned long)iommu->ptab; 433 window->table.it_index = iommu->nid; 434 window->table.it_offset = (offset >> IOMMU_PAGE_SHIFT) + 435 window->pte_offset; 436 window->table.it_size = size >> IOMMU_PAGE_SHIFT; 437 438 iommu_init_table(&window->table, iommu->nid); 439 440 pr_debug("\tioid %d\n", window->ioid); 441 pr_debug("\tblocksize %ld\n", window->table.it_blocksize); 442 pr_debug("\tbase 0x%016lx\n", window->table.it_base); 443 pr_debug("\toffset 0x%lx\n", window->table.it_offset); 444 pr_debug("\tsize %ld\n", window->table.it_size); 445 446 list_add(&window->list, &iommu->windows); 447 448 if (offset != 0) 449 return window; 450 451 __set_bit(0, window->table.it_map); 452 tce_build_cell(&window->table, window->table.it_offset, 1, 453 (unsigned long)iommu->pad_page, DMA_TO_DEVICE); 454 window->table.it_hint = window->table.it_blocksize; 455 456 return window; 457} 458 459static struct cbe_iommu *cell_iommu_for_node(int nid) 460{ 461 int i; 462 463 for (i = 0; i < cbe_nr_iommus; i++) 464 if (iommus[i].nid == nid) 465 return &iommus[i]; 466 return NULL; 467} 468 469static void cell_dma_dev_setup(struct device *dev) 470{ 471 struct iommu_window *window; 472 struct cbe_iommu *iommu; 473 struct dev_archdata *archdata = &dev->archdata; 474 475 /* If we run without iommu, no need to do anything */ 476 if (get_pci_dma_ops() == &dma_direct_ops) 477 return; 478 479 /* Current implementation uses the first window available in that 480 * node's iommu. We -might- do something smarter later though it may 481 * never be necessary 482 */ 483 iommu = cell_iommu_for_node(archdata->numa_node); 484 if (iommu == NULL || list_empty(&iommu->windows)) { 485 printk(KERN_ERR "iommu: missing iommu for %s (node %d)\n", 486 archdata->of_node ? archdata->of_node->full_name : "?", 487 archdata->numa_node); 488 return; 489 } 490 window = list_entry(iommu->windows.next, struct iommu_window, list); 491 492 archdata->dma_data = &window->table; 493} 494 495static void cell_pci_dma_dev_setup(struct pci_dev *dev) 496{ 497 cell_dma_dev_setup(&dev->dev); 498} 499 500static int cell_of_bus_notify(struct notifier_block *nb, unsigned long action, 501 void *data) 502{ 503 struct device *dev = data; 504 505 /* We are only intereted in device addition */ 506 if (action != BUS_NOTIFY_ADD_DEVICE) 507 return 0; 508 509 /* We use the PCI DMA ops */ 510 dev->archdata.dma_ops = get_pci_dma_ops(); 511 512 cell_dma_dev_setup(dev); 513 514 return 0; 515} 516 517static struct notifier_block cell_of_bus_notifier = { 518 .notifier_call = cell_of_bus_notify 519}; 520 521static int __init cell_iommu_get_window(struct device_node *np, 522 unsigned long *base, 523 unsigned long *size) 524{ 525 const void *dma_window; 526 unsigned long index; 527 528 /* Use ibm,dma-window if available, else, hard code ! */ 529 dma_window = of_get_property(np, "ibm,dma-window", NULL); 530 if (dma_window == NULL) { 531 *base = 0; 532 *size = 0x80000000u; 533 return -ENODEV; 534 } 535 536 of_parse_dma_window(np, dma_window, &index, base, size); 537 return 0; 538} 539 540static void __init cell_iommu_init_one(struct device_node *np, unsigned long offset) 541{ 542 struct cbe_iommu *iommu; 543 unsigned long base, size; 544 int nid, i; 545 546 /* Get node ID */ 547 nid = of_node_to_nid(np); 548 if (nid < 0) { 549 printk(KERN_ERR "iommu: failed to get node for %s\n", 550 np->full_name); 551 return; 552 } 553 pr_debug("iommu: setting up iommu for node %d (%s)\n", 554 nid, np->full_name); 555 556 557 if (cbe_nr_iommus >= NR_IOMMUS) { 558 printk(KERN_ERR "iommu: too many IOMMUs detected ! (%s)\n", 559 np->full_name); 560 return; 561 } 562 563 /* Init base fields */ 564 i = cbe_nr_iommus++; 565 iommu = &iommus[i]; 566 iommu->stab = NULL; 567 iommu->nid = nid; 568 snprintf(iommu->name, sizeof(iommu->name), "iommu%d", i); 569 INIT_LIST_HEAD(&iommu->windows); 570 571 /* Obtain a window for it */ 572 cell_iommu_get_window(np, &base, &size); 573 574 pr_debug("\ttranslating window 0x%lx...0x%lx\n", 575 base, base + size - 1); 576 577 /* Initialize the hardware */ 578 cell_iommu_setup_hardware(iommu, size); 579 580 /* Setup the iommu_table */ 581 cell_iommu_setup_window(iommu, np, base, size, 582 offset >> IOMMU_PAGE_SHIFT); 583} 584 585static void __init cell_disable_iommus(void) 586{ 587 int node; 588 unsigned long base, val; 589 void __iomem *xregs, *cregs; 590 591 /* Make sure IOC translation is disabled on all nodes */ 592 for_each_online_node(node) { 593 if (cell_iommu_find_ioc(node, &base)) 594 continue; 595 xregs = ioremap(base, IOC_Reg_Size); 596 if (xregs == NULL) 597 continue; 598 cregs = xregs + IOC_IOCmd_Offset; 599 600 pr_debug("iommu: cleaning up iommu on node %d\n", node); 601 602 out_be64(xregs + IOC_IOST_Origin, 0); 603 (void)in_be64(xregs + IOC_IOST_Origin); 604 val = in_be64(cregs + IOC_IOCmd_Cfg); 605 val &= ~IOC_IOCmd_Cfg_TE; 606 out_be64(cregs + IOC_IOCmd_Cfg, val); 607 (void)in_be64(cregs + IOC_IOCmd_Cfg); 608 609 iounmap(xregs); 610 } 611} 612 613static int __init cell_iommu_init_disabled(void) 614{ 615 struct device_node *np = NULL; 616 unsigned long base = 0, size; 617 618 /* When no iommu is present, we use direct DMA ops */ 619 set_pci_dma_ops(&dma_direct_ops); 620 621 /* First make sure all IOC translation is turned off */ 622 cell_disable_iommus(); 623 624 /* If we have no Axon, we set up the spider DMA magic offset */ 625 if (of_find_node_by_name(NULL, "axon") == NULL) 626 dma_direct_offset = SPIDER_DMA_OFFSET; 627 628 /* Now we need to check to see where the memory is mapped 629 * in PCI space. We assume that all busses use the same dma 630 * window which is always the case so far on Cell, thus we 631 * pick up the first pci-internal node we can find and check 632 * the DMA window from there. 633 */ 634 for_each_node_by_name(np, "axon") { 635 if (np->parent == NULL || np->parent->parent != NULL) 636 continue; 637 if (cell_iommu_get_window(np, &base, &size) == 0) 638 break; 639 } 640 if (np == NULL) { 641 for_each_node_by_name(np, "pci-internal") { 642 if (np->parent == NULL || np->parent->parent != NULL) 643 continue; 644 if (cell_iommu_get_window(np, &base, &size) == 0) 645 break; 646 } 647 } 648 of_node_put(np); 649 650 /* If we found a DMA window, we check if it's big enough to enclose 651 * all of physical memory. If not, we force enable IOMMU 652 */ 653 if (np && size < lmb_end_of_DRAM()) { 654 printk(KERN_WARNING "iommu: force-enabled, dma window" 655 " (%ldMB) smaller than total memory (%ldMB)\n", 656 size >> 20, lmb_end_of_DRAM() >> 20); 657 return -ENODEV; 658 } 659 660 dma_direct_offset += base; 661 662 printk("iommu: disabled, direct DMA offset is 0x%lx\n", 663 dma_direct_offset); 664 665 return 0; 666} 667 668static int __init cell_iommu_init(void) 669{ 670 struct device_node *np; 671 672 if (!machine_is(cell)) 673 return -ENODEV; 674 675 /* If IOMMU is disabled or we have little enough RAM to not need 676 * to enable it, we setup a direct mapping. 677 * 678 * Note: should we make sure we have the IOMMU actually disabled ? 679 */ 680 if (iommu_is_off || 681 (!iommu_force_on && lmb_end_of_DRAM() <= 0x80000000ull)) 682 if (cell_iommu_init_disabled() == 0) 683 goto bail; 684 685 /* Setup various ppc_md. callbacks */ 686 ppc_md.pci_dma_dev_setup = cell_pci_dma_dev_setup; 687 ppc_md.tce_build = tce_build_cell; 688 ppc_md.tce_free = tce_free_cell; 689 690 /* Create an iommu for each /axon node. */ 691 for_each_node_by_name(np, "axon") { 692 if (np->parent == NULL || np->parent->parent != NULL) 693 continue; 694 cell_iommu_init_one(np, 0); 695 } 696 697 /* Create an iommu for each toplevel /pci-internal node for 698 * old hardware/firmware 699 */ 700 for_each_node_by_name(np, "pci-internal") { 701 if (np->parent == NULL || np->parent->parent != NULL) 702 continue; 703 cell_iommu_init_one(np, SPIDER_DMA_OFFSET); 704 } 705 706 /* Setup default PCI iommu ops */ 707 set_pci_dma_ops(&dma_iommu_ops); 708 709 bail: 710 /* Register callbacks on OF platform device addition/removal 711 * to handle linking them to the right DMA operations 712 */ 713 bus_register_notifier(&of_platform_bus_type, &cell_of_bus_notifier); 714 715 return 0; 716} 717arch_initcall(cell_iommu_init); 718