1/*
2 *  Copyright (C) 1995  Linus Torvalds
3 *  Adapted from 'alpha' version by Gary Thomas
4 *  Modified by Cort Dougan (cort@cs.nmt.edu)
5 *  Modified for MBX using prep/chrp/pmac functions by Dan (dmalek@jlc.net)
6 *  Further modified for generic 8xx by Dan.
7 */
8
9/*
10 * bootup setup stuff..
11 */
12
13#include <linux/errno.h>
14#include <linux/sched.h>
15#include <linux/kernel.h>
16#include <linux/mm.h>
17#include <linux/stddef.h>
18#include <linux/unistd.h>
19#include <linux/ptrace.h>
20#include <linux/slab.h>
21#include <linux/user.h>
22#include <linux/a.out.h>
23#include <linux/tty.h>
24#include <linux/major.h>
25#include <linux/interrupt.h>
26#include <linux/reboot.h>
27#include <linux/init.h>
28#include <linux/initrd.h>
29#include <linux/ioport.h>
30#include <linux/bootmem.h>
31#include <linux/seq_file.h>
32#include <linux/root_dev.h>
33#include <linux/time.h>
34#include <linux/rtc.h>
35
36#include <asm/mmu.h>
37#include <asm/reg.h>
38#include <asm/residual.h>
39#include <asm/io.h>
40#include <asm/pgtable.h>
41#include <asm/mpc8xx.h>
42#include <asm/8xx_immap.h>
43#include <asm/machdep.h>
44#include <asm/bootinfo.h>
45#include <asm/time.h>
46#include <asm/prom.h>
47#include <asm/fs_pd.h>
48#include <mm/mmu_decl.h>
49
50#include "sysdev/mpc8xx_pic.h"
51
52void m8xx_calibrate_decr(void);
53extern void m8xx_wdt_handler_install(bd_t *bp);
54extern int cpm_pic_init(void);
55extern int cpm_get_irq(void);
56
57/* A place holder for time base interrupts, if they are ever enabled. */
58irqreturn_t timebase_interrupt(int irq, void * dev)
59{
60	printk ("timebase_interrupt()\n");
61
62	return IRQ_HANDLED;
63}
64
65static struct irqaction tbint_irqaction = {
66	.handler = timebase_interrupt,
67	.mask = CPU_MASK_NONE,
68	.name = "tbint",
69};
70
71/* per-board overridable init_internal_rtc() function. */
72void __init __attribute__ ((weak))
73init_internal_rtc(void)
74{
75	sit8xx_t *sys_tmr = (sit8xx_t *) immr_map(im_sit);
76
77	/* Disable the RTC one second and alarm interrupts. */
78	clrbits16(&sys_tmr->sit_rtcsc, (RTCSC_SIE | RTCSC_ALE));
79
80	/* Enable the RTC */
81	setbits16(&sys_tmr->sit_rtcsc, (RTCSC_RTF | RTCSC_RTE));
82	immr_unmap(sys_tmr);
83}
84
85static int __init get_freq(char *name, unsigned long *val)
86{
87        struct device_node *cpu;
88        const unsigned int *fp;
89        int found = 0;
90
91        /* The cpu node should have timebase and clock frequency properties */
92        cpu = of_find_node_by_type(NULL, "cpu");
93
94        if (cpu) {
95                fp = of_get_property(cpu, name, NULL);
96                if (fp) {
97                        found = 1;
98                        *val = *fp;
99                }
100
101                of_node_put(cpu);
102        }
103
104        return found;
105}
106
107/* The decrementer counts at the system (internal) clock frequency divided by
108 * sixteen, or external oscillator divided by four.  We force the processor
109 * to use system clock divided by sixteen.
110 */
111void __init mpc8xx_calibrate_decr(void)
112{
113	struct device_node *cpu;
114	cark8xx_t *clk_r1;
115	car8xx_t *clk_r2;
116	sitk8xx_t *sys_tmr1;
117	sit8xx_t *sys_tmr2;
118	int irq, virq;
119
120        clk_r1 = (cark8xx_t *) immr_map(im_clkrstk);
121
122	/* Unlock the SCCR. */
123	out_be32(&clk_r1->cark_sccrk, ~KAPWR_KEY);
124	out_be32(&clk_r1->cark_sccrk, KAPWR_KEY);
125	immr_unmap(clk_r1);
126
127	/* Force all 8xx processors to use divide by 16 processor clock. */
128        clk_r2 = (car8xx_t *) immr_map(im_clkrst);
129	setbits32(&clk_r2->car_sccr, 0x02000000);
130	immr_unmap(clk_r2);
131
132	/* Processor frequency is MHz.
133	 */
134        ppc_tb_freq = 50000000;
135        if (!get_freq("bus-frequency", &ppc_tb_freq)) {
136                printk(KERN_ERR "WARNING: Estimating decrementer frequency "
137                                "(not found)\n");
138        }
139        ppc_tb_freq /= 16;
140        ppc_proc_freq = 50000000;
141        if (!get_freq("clock-frequency", &ppc_proc_freq))
142                printk(KERN_ERR "WARNING: Estimating processor frequency"
143                                "(not found)\n");
144
145        printk("Decrementer Frequency = 0x%lx\n", ppc_tb_freq);
146
147	/* Perform some more timer/timebase initialization.  This used
148	 * to be done elsewhere, but other changes caused it to get
149	 * called more than once....that is a bad thing.
150	 *
151	 * First, unlock all of the registers we are going to modify.
152	 * To protect them from corruption during power down, registers
153	 * that are maintained by keep alive power are "locked".  To
154	 * modify these registers we have to write the key value to
155	 * the key location associated with the register.
156	 * Some boards power up with these unlocked, while others
157	 * are locked.  Writing anything (including the unlock code?)
158	 * to the unlocked registers will lock them again.  So, here
159	 * we guarantee the registers are locked, then we unlock them
160	 * for our use.
161	 */
162        sys_tmr1 = (sitk8xx_t *) immr_map(im_sitk);
163	out_be32(&sys_tmr1->sitk_tbscrk, ~KAPWR_KEY);
164	out_be32(&sys_tmr1->sitk_rtcsck, ~KAPWR_KEY);
165	out_be32(&sys_tmr1->sitk_tbk, ~KAPWR_KEY);
166	out_be32(&sys_tmr1->sitk_tbscrk, KAPWR_KEY);
167	out_be32(&sys_tmr1->sitk_rtcsck, KAPWR_KEY);
168	out_be32(&sys_tmr1->sitk_tbk, KAPWR_KEY);
169	immr_unmap(sys_tmr1);
170
171	init_internal_rtc();
172
173	/* Enabling the decrementer also enables the timebase interrupts
174	 * (or from the other point of view, to get decrementer interrupts
175	 * we have to enable the timebase).  The decrementer interrupt
176	 * is wired into the vector table, nothing to do here for that.
177	 */
178        cpu = of_find_node_by_type(NULL, "cpu");
179        virq= irq_of_parse_and_map(cpu, 0);
180	irq = irq_map[virq].hwirq;
181
182	sys_tmr2 = (sit8xx_t *) immr_map(im_sit);
183	out_be16(&sys_tmr2->sit_tbscr, ((1 << (7 - (irq/2))) << 8) |
184					(TBSCR_TBF | TBSCR_TBE));
185	immr_unmap(sys_tmr2);
186
187	if (setup_irq(virq, &tbint_irqaction))
188		panic("Could not allocate timer IRQ!");
189
190#ifdef CONFIG_8xx_WDT
191	/* Install watchdog timer handler early because it might be
192	 * already enabled by the bootloader
193	 */
194	m8xx_wdt_handler_install(binfo);
195#endif
196}
197
198/* The RTC on the MPC8xx is an internal register.
199 * We want to protect this during power down, so we need to unlock,
200 * modify, and re-lock.
201 */
202
203int mpc8xx_set_rtc_time(struct rtc_time *tm)
204{
205	sitk8xx_t *sys_tmr1;
206	sit8xx_t *sys_tmr2;
207	int time;
208
209        sys_tmr1 = (sitk8xx_t *) immr_map(im_sitk);
210	sys_tmr2 = (sit8xx_t *) immr_map(im_sit);
211	time = mktime(tm->tm_year+1900, tm->tm_mon+1, tm->tm_mday,
212                      tm->tm_hour, tm->tm_min, tm->tm_sec);
213
214	out_be32(&sys_tmr1->sitk_rtck, KAPWR_KEY);
215	out_be32(&sys_tmr2->sit_rtc, time);
216	out_be32(&sys_tmr1->sitk_rtck, ~KAPWR_KEY);
217
218	immr_unmap(sys_tmr2);
219	immr_unmap(sys_tmr1);
220	return 0;
221}
222
223void mpc8xx_get_rtc_time(struct rtc_time *tm)
224{
225	unsigned long data;
226	sit8xx_t *sys_tmr = (sit8xx_t *) immr_map(im_sit);
227
228	/* Get time from the RTC. */
229	data = in_be32(&sys_tmr->sit_rtc);
230	to_tm(data, tm);
231        tm->tm_year -= 1900;
232        tm->tm_mon -= 1;
233	immr_unmap(sys_tmr);
234	return;
235}
236
237void mpc8xx_restart(char *cmd)
238{
239	__volatile__ unsigned char dummy;
240	car8xx_t * clk_r = (car8xx_t *) immr_map(im_clkrst);
241
242
243	local_irq_disable();
244
245	setbits32(&clk_r->car_plprcr, 0x00000080);
246	/* Clear the ME bit in MSR to cause checkstop on machine check
247	*/
248	mtmsr(mfmsr() & ~0x1000);
249
250	dummy = in_8(&clk_r->res[0]);
251	printk("Restart failed\n");
252	while(1);
253}
254
255void mpc8xx_show_cpuinfo(struct seq_file *m)
256{
257	struct device_node *root;
258	uint memsize = total_memory;
259	const char *model = "";
260
261	seq_printf(m, "Vendor\t\t: Freescale Semiconductor\n");
262
263	root = of_find_node_by_path("/");
264	if (root)
265		model = of_get_property(root, "model", NULL);
266	seq_printf(m, "Machine\t\t: %s\n", model);
267	of_node_put(root);
268
269	seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024));
270}
271
272static void cpm_cascade(unsigned int irq, struct irq_desc *desc)
273{
274	int cascade_irq;
275
276	if ((cascade_irq = cpm_get_irq()) >= 0) {
277		struct irq_desc *cdesc = irq_desc + cascade_irq;
278
279		generic_handle_irq(cascade_irq);
280		cdesc->chip->eoi(cascade_irq);
281	}
282	desc->chip->eoi(irq);
283}
284
285/* Initialize the internal interrupt controller.  The number of
286 * interrupts supported can vary with the processor type, and the
287 * 82xx family can have up to 64.
288 * External interrupts can be either edge or level triggered, and
289 * need to be initialized by the appropriate driver.
290 */
291void __init m8xx_pic_init(void)
292{
293	int irq;
294
295	if (mpc8xx_pic_init()) {
296                printk(KERN_ERR "Failed interrupt 8xx controller  initialization\n");
297		return;
298	}
299
300	irq = cpm_pic_init();
301	if (irq != NO_IRQ)
302		set_irq_chained_handler(irq, cpm_cascade);
303}
304