1#include <linux/init.h>
2#include <linux/pm.h>
3#include <linux/io.h>
4#include <asm/time.h>
5#include <asm/cacheflush.h>
6#include <asm/mpc52xx.h>
7
8#include "mpc52xx_pic.h"
9
10
11/* these are defined in mpc52xx_sleep.S, and only used here */
12extern void mpc52xx_deep_sleep(void *sram, void *sdram_regs,
13		struct mpc52xx_cdm *, struct mpc52xx_intr *);
14extern void mpc52xx_ds_sram(void);
15extern const long mpc52xx_ds_sram_size;
16extern void mpc52xx_ds_cached(void);
17extern const long mpc52xx_ds_cached_size;
18
19static void __iomem *mbar;
20static void __iomem *sdram;
21static struct mpc52xx_cdm __iomem *cdm;
22static struct mpc52xx_intr __iomem *intr;
23static struct mpc52xx_gpio_wkup __iomem *gpiow;
24static void *sram;
25static int sram_size;
26
27struct mpc52xx_suspend mpc52xx_suspend;
28
29static int mpc52xx_pm_valid(suspend_state_t state)
30{
31	switch (state) {
32	case PM_SUSPEND_STANDBY:
33		return 1;
34	default:
35		return 0;
36	}
37}
38
39int mpc52xx_set_wakeup_gpio(u8 pin, u8 level)
40{
41	u16 tmp;
42
43	/* enable gpio */
44	out_8(&gpiow->wkup_gpioe, in_8(&gpiow->wkup_gpioe) | (1 << pin));
45	/* set as input */
46	out_8(&gpiow->wkup_ddr, in_8(&gpiow->wkup_ddr) & ~(1 << pin));
47	/* enable deep sleep interrupt */
48	out_8(&gpiow->wkup_inten, in_8(&gpiow->wkup_inten) | (1 << pin));
49	/* low/high level creates wakeup interrupt */
50	tmp = in_be16(&gpiow->wkup_itype);
51	tmp &= ~(0x3 << (pin * 2));
52	tmp |= (!level + 1) << (pin * 2);
53	out_be16(&gpiow->wkup_itype, tmp);
54	/* master enable */
55	out_8(&gpiow->wkup_maste, 1);
56
57	return 0;
58}
59
60int mpc52xx_pm_prepare(suspend_state_t state)
61{
62	if (state != PM_SUSPEND_STANDBY)
63		return -EINVAL;
64
65	/* map the whole register space */
66	mbar = mpc52xx_find_and_map("mpc5200");
67	if (!mbar) {
68		printk(KERN_ERR "%s:%i Error mapping registers\n", __func__, __LINE__);
69		return -ENOSYS;
70	}
71	/* these offsets are from mpc5200 users manual */
72	sdram	= mbar + 0x100;
73	cdm	= mbar + 0x200;
74	intr	= mbar + 0x500;
75	gpiow	= mbar + 0xc00;
76	sram	= mbar + 0x8000;	/* Those will be handled by the */
77	sram_size = 0x4000;		/* bestcomm driver soon */
78
79	/* call board suspend code, if applicable */
80	if (mpc52xx_suspend.board_suspend_prepare)
81		mpc52xx_suspend.board_suspend_prepare(mbar);
82	else {
83		printk(KERN_ALERT "%s: %i don't know how to wake up the board\n",
84				__func__, __LINE__);
85		goto out_unmap;
86	}
87
88	return 0;
89
90 out_unmap:
91	iounmap(mbar);
92	return -ENOSYS;
93}
94
95
96char saved_sram[0x4000];
97
98int mpc52xx_pm_enter(suspend_state_t state)
99{
100	u32 clk_enables;
101	u32 msr, hid0;
102	u32 intr_main_mask;
103	void __iomem * irq_0x500 = (void *)CONFIG_KERNEL_START + 0x500;
104	unsigned long irq_0x500_stop = (unsigned long)irq_0x500 + mpc52xx_ds_cached_size;
105	char saved_0x500[mpc52xx_ds_cached_size];
106
107	/* disable all interrupts in PIC */
108	intr_main_mask = in_be32(&intr->main_mask);
109	out_be32(&intr->main_mask, intr_main_mask | 0x1ffff);
110
111	/* don't let DEC expire any time soon */
112	mtspr(SPRN_DEC, 0x7fffffff);
113
114	/* save SRAM */
115	memcpy(saved_sram, sram, sram_size);
116
117	/* copy low level suspend code to sram */
118	memcpy(sram, mpc52xx_ds_sram, mpc52xx_ds_sram_size);
119
120	out_8(&cdm->ccs_sleep_enable, 1);
121	out_8(&cdm->osc_sleep_enable, 1);
122	out_8(&cdm->ccs_qreq_test, 1);
123
124	/* disable all but SDRAM and bestcomm (SRAM) clocks */
125	clk_enables = in_be32(&cdm->clk_enables);
126	out_be32(&cdm->clk_enables, clk_enables & 0x00088000);
127
128	/* disable power management */
129	msr = mfmsr();
130	mtmsr(msr & ~MSR_POW);
131
132	/* enable sleep mode, disable others */
133	hid0 = mfspr(SPRN_HID0);
134	mtspr(SPRN_HID0, (hid0 & ~(HID0_DOZE | HID0_NAP | HID0_DPM)) | HID0_SLEEP);
135
136	/* save original, copy our irq handler, flush from dcache and invalidate icache */
137	memcpy(saved_0x500, irq_0x500, mpc52xx_ds_cached_size);
138	memcpy(irq_0x500, mpc52xx_ds_cached, mpc52xx_ds_cached_size);
139	flush_icache_range((unsigned long)irq_0x500, irq_0x500_stop);
140
141	/* call low-level sleep code */
142	mpc52xx_deep_sleep(sram, sdram, cdm, intr);
143
144	/* restore original irq handler */
145	memcpy(irq_0x500, saved_0x500, mpc52xx_ds_cached_size);
146	flush_icache_range((unsigned long)irq_0x500, irq_0x500_stop);
147
148	/* restore old power mode */
149	mtmsr(msr & ~MSR_POW);
150	mtspr(SPRN_HID0, hid0);
151	mtmsr(msr);
152
153	out_be32(&cdm->clk_enables, clk_enables);
154	out_8(&cdm->ccs_sleep_enable, 0);
155	out_8(&cdm->osc_sleep_enable, 0);
156
157	/* restore SRAM */
158	memcpy(sram, saved_sram, sram_size);
159
160	/* restart jiffies */
161	wakeup_decrementer();
162
163	/* reenable interrupts in PIC */
164	out_be32(&intr->main_mask, intr_main_mask);
165
166	return 0;
167}
168
169int mpc52xx_pm_finish(suspend_state_t state)
170{
171	/* call board resume code */
172	if (mpc52xx_suspend.board_resume_finish)
173		mpc52xx_suspend.board_resume_finish(mbar);
174
175	iounmap(mbar);
176
177	return 0;
178}
179
180static struct pm_ops mpc52xx_pm_ops = {
181	.valid		= mpc52xx_pm_valid,
182	.prepare	= mpc52xx_pm_prepare,
183	.enter		= mpc52xx_pm_enter,
184	.finish		= mpc52xx_pm_finish,
185};
186
187int __init mpc52xx_pm_init(void)
188{
189	pm_set_ops(&mpc52xx_pm_ops);
190	return 0;
191}
192