1/* 2 * Header file for Freescale MPC52xx Interrupt controller 3 * 4 * Copyright (C) 2004-2005 Sylvain Munaut <tnt@246tNt.com> 5 * Copyright (C) 2003 MontaVista, Software, Inc. 6 * 7 * This file is licensed under the terms of the GNU General Public License 8 * version 2. This program is licensed "as is" without any warranty of any 9 * kind, whether express or implied. 10 */ 11 12#ifndef __POWERPC_SYSDEV_MPC52xx_PIC_H__ 13#define __POWERPC_SYSDEV_MPC52xx_PIC_H__ 14 15#include <asm/types.h> 16 17 18/* HW IRQ mapping */ 19#define MPC52xx_IRQ_L1_CRIT (0) 20#define MPC52xx_IRQ_L1_MAIN (1) 21#define MPC52xx_IRQ_L1_PERP (2) 22#define MPC52xx_IRQ_L1_SDMA (3) 23 24#define MPC52xx_IRQ_L1_OFFSET (6) 25#define MPC52xx_IRQ_L1_MASK (0x00c0) 26 27#define MPC52xx_IRQ_L2_OFFSET (0) 28#define MPC52xx_IRQ_L2_MASK (0x003f) 29 30#define MPC52xx_IRQ_HIGHTESTHWIRQ (0xd0) 31 32 33/* Interrupt controller Register set */ 34struct mpc52xx_intr { 35 u32 per_mask; /* INTR + 0x00 */ 36 u32 per_pri1; /* INTR + 0x04 */ 37 u32 per_pri2; /* INTR + 0x08 */ 38 u32 per_pri3; /* INTR + 0x0c */ 39 u32 ctrl; /* INTR + 0x10 */ 40 u32 main_mask; /* INTR + 0x14 */ 41 u32 main_pri1; /* INTR + 0x18 */ 42 u32 main_pri2; /* INTR + 0x1c */ 43 u32 reserved1; /* INTR + 0x20 */ 44 u32 enc_status; /* INTR + 0x24 */ 45 u32 crit_status; /* INTR + 0x28 */ 46 u32 main_status; /* INTR + 0x2c */ 47 u32 per_status; /* INTR + 0x30 */ 48 u32 reserved2; /* INTR + 0x34 */ 49 u32 per_error; /* INTR + 0x38 */ 50}; 51 52#endif /* __POWERPC_SYSDEV_MPC52xx_PIC_H__ */ 53