1/* 2 * 3 * Copyright (C) 2005 Embedded Alley Solutions, Inc 4 * Ported to 2.6. 5 * 6 * Per Hallsmark, per.hallsmark@mvista.com 7 * Copyright (C) 2000, 2001 MIPS Technologies, Inc. 8 * Copyright (C) 2001 Ralf Baechle 9 * 10 * Cleaned up and bug fixing: Pete Popov, ppopov@embeddedalley.com 11 * 12 * This program is free software; you can distribute it and/or modify it 13 * under the terms of the GNU General Public License (Version 2) as 14 * published by the Free Software Foundation. 15 * 16 * This program is distributed in the hope it will be useful, but WITHOUT 17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 19 * for more details. 20 * 21 * You should have received a copy of the GNU General Public License along 22 * with this program; if not, write to the Free Software Foundation, Inc., 23 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. 24 * 25 */ 26#include <linux/compiler.h> 27#include <linux/init.h> 28#include <linux/irq.h> 29#include <linux/sched.h> 30#include <linux/slab.h> 31#include <linux/interrupt.h> 32#include <linux/kernel_stat.h> 33#include <linux/random.h> 34#include <linux/module.h> 35 36#include <asm/io.h> 37#include <asm/gdb-stub.h> 38#include <int.h> 39#include <uart.h> 40 41/* default prio for interrupts */ 42/* first one is a no-no so therefore always prio 0 (disabled) */ 43static char gic_prio[PNX8550_INT_GIC_TOTINT] = { 44 0, 1, 1, 1, 1, 15, 1, 1, 1, 1, // 0 - 9 45 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, // 10 - 19 46 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, // 20 - 29 47 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, // 30 - 39 48 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, // 40 - 49 49 1, 1, 1, 1, 1, 1, 1, 1, 2, 1, // 50 - 59 50 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, // 60 - 69 51 1 // 70 52}; 53 54static void hw0_irqdispatch(int irq) 55{ 56 /* find out which interrupt */ 57 irq = PNX8550_GIC_VECTOR_0 >> 3; 58 59 if (irq == 0) { 60 printk("hw0_irqdispatch: irq 0, spurious interrupt?\n"); 61 return; 62 } 63 do_IRQ(PNX8550_INT_GIC_MIN + irq); 64} 65 66 67static void timer_irqdispatch(int irq) 68{ 69 irq = (0x01c0 & read_c0_config7()) >> 6; 70 71 if (unlikely(irq == 0)) { 72 printk("timer_irqdispatch: irq 0, spurious interrupt?\n"); 73 return; 74 } 75 76 if (irq & 0x1) 77 do_IRQ(PNX8550_INT_TIMER1); 78 if (irq & 0x2) 79 do_IRQ(PNX8550_INT_TIMER2); 80 if (irq & 0x4) 81 do_IRQ(PNX8550_INT_TIMER3); 82} 83 84asmlinkage void plat_irq_dispatch(void) 85{ 86 unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM; 87 88 if (pending & STATUSF_IP2) 89 hw0_irqdispatch(2); 90 else if (pending & STATUSF_IP7) { 91 if (read_c0_config7() & 0x01c0) 92 timer_irqdispatch(7); 93 } else 94 spurious_interrupt(); 95} 96 97static inline void modify_cp0_intmask(unsigned clr_mask, unsigned set_mask) 98{ 99 unsigned long status = read_c0_status(); 100 101 status &= ~((clr_mask & 0xFF) << 8); 102 status |= (set_mask & 0xFF) << 8; 103 104 write_c0_status(status); 105} 106 107static inline void mask_gic_int(unsigned int irq_nr) 108{ 109 /* interrupt disabled, bit 26(WE_ENABLE)=1 and bit 16(enable)=0 */ 110 PNX8550_GIC_REQ(irq_nr) = 1<<28; /* set priority to 0 */ 111} 112 113static inline void unmask_gic_int(unsigned int irq_nr) 114{ 115 /* set prio mask to lower four bits and enable interrupt */ 116 PNX8550_GIC_REQ(irq_nr) = (1<<26 | 1<<16) | (1<<28) | gic_prio[irq_nr]; 117} 118 119static inline void mask_irq(unsigned int irq_nr) 120{ 121 if ((PNX8550_INT_CP0_MIN <= irq_nr) && (irq_nr <= PNX8550_INT_CP0_MAX)) { 122 modify_cp0_intmask(1 << irq_nr, 0); 123 } else if ((PNX8550_INT_GIC_MIN <= irq_nr) && 124 (irq_nr <= PNX8550_INT_GIC_MAX)) { 125 mask_gic_int(irq_nr - PNX8550_INT_GIC_MIN); 126 } else if ((PNX8550_INT_TIMER_MIN <= irq_nr) && 127 (irq_nr <= PNX8550_INT_TIMER_MAX)) { 128 modify_cp0_intmask(1 << 7, 0); 129 } else { 130 printk("mask_irq: irq %d doesn't exist!\n", irq_nr); 131 } 132} 133 134static inline void unmask_irq(unsigned int irq_nr) 135{ 136 if ((PNX8550_INT_CP0_MIN <= irq_nr) && (irq_nr <= PNX8550_INT_CP0_MAX)) { 137 modify_cp0_intmask(0, 1 << irq_nr); 138 } else if ((PNX8550_INT_GIC_MIN <= irq_nr) && 139 (irq_nr <= PNX8550_INT_GIC_MAX)) { 140 unmask_gic_int(irq_nr - PNX8550_INT_GIC_MIN); 141 } else if ((PNX8550_INT_TIMER_MIN <= irq_nr) && 142 (irq_nr <= PNX8550_INT_TIMER_MAX)) { 143 modify_cp0_intmask(0, 1 << 7); 144 } else { 145 printk("mask_irq: irq %d doesn't exist!\n", irq_nr); 146 } 147} 148 149int pnx8550_set_gic_priority(int irq, int priority) 150{ 151 int gic_irq = irq-PNX8550_INT_GIC_MIN; 152 int prev_priority = PNX8550_GIC_REQ(gic_irq) & 0xf; 153 154 gic_prio[gic_irq] = priority; 155 PNX8550_GIC_REQ(gic_irq) |= (0x10000000 | gic_prio[gic_irq]); 156 157 return prev_priority; 158} 159 160static struct irq_chip level_irq_type = { 161 .name = "PNX Level IRQ", 162 .ack = mask_irq, 163 .mask = mask_irq, 164 .mask_ack = mask_irq, 165 .unmask = unmask_irq, 166}; 167 168static struct irqaction gic_action = { 169 .handler = no_action, 170 .flags = IRQF_DISABLED, 171 .name = "GIC", 172}; 173 174static struct irqaction timer_action = { 175 .handler = no_action, 176 .flags = IRQF_DISABLED, 177 .name = "Timer", 178}; 179 180void __init arch_init_irq(void) 181{ 182 int i; 183 int configPR; 184 185 for (i = 0; i < PNX8550_INT_CP0_TOTINT; i++) { 186 set_irq_chip_and_handler(i, &level_irq_type, handle_level_irq); 187 mask_irq(i); /* mask the irq just in case */ 188 } 189 190 /* init of GIC/IPC interrupts */ 191 /* should be done before cp0 since cp0 init enables the GIC int */ 192 for (i = PNX8550_INT_GIC_MIN; i <= PNX8550_INT_GIC_MAX; i++) { 193 int gic_int_line = i - PNX8550_INT_GIC_MIN; 194 if (gic_int_line == 0 ) 195 continue; // don't fiddle with int 0 196 /* 197 * enable change of TARGET, ENABLE and ACTIVE_LOW bits 198 * set TARGET 0 to route through hw0 interrupt 199 * set ACTIVE_LOW 0 active high (correct?) 200 * 201 * We really should setup an interrupt description table 202 * to do this nicely. 203 * Note, PCI INTA is active low on the bus, but inverted 204 * in the GIC, so to us it's active high. 205 */ 206 PNX8550_GIC_REQ(i - PNX8550_INT_GIC_MIN) = 0x1E000000; 207 208 /* mask/priority is still 0 so we will not get any 209 * interrupts until it is unmasked */ 210 211 set_irq_chip_and_handler(i, &level_irq_type, handle_level_irq); 212 } 213 214 /* Priority level 0 */ 215 PNX8550_GIC_PRIMASK_0 = PNX8550_GIC_PRIMASK_1 = 0; 216 217 /* Set int vector table address */ 218 PNX8550_GIC_VECTOR_0 = PNX8550_GIC_VECTOR_1 = 0; 219 220 set_irq_chip_and_handler(MIPS_CPU_GIC_IRQ, &level_irq_type, 221 handle_level_irq); 222 setup_irq(MIPS_CPU_GIC_IRQ, &gic_action); 223 224 /* init of Timer interrupts */ 225 for (i = PNX8550_INT_TIMER_MIN; i <= PNX8550_INT_TIMER_MAX; i++) 226 set_irq_chip_and_handler(i, &level_irq_type, handle_level_irq); 227 228 /* Stop Timer 1-3 */ 229 configPR = read_c0_config7(); 230 configPR |= 0x00000038; 231 write_c0_config7(configPR); 232 233 set_irq_chip_and_handler(MIPS_CPU_TIMER_IRQ, &level_irq_type, 234 handle_level_irq); 235 setup_irq(MIPS_CPU_TIMER_IRQ, &timer_action); 236} 237 238EXPORT_SYMBOL(pnx8550_set_gic_priority); 239