1/* 2 * Copyright (C) 2001,2002,2005 Broadcom Corporation 3 * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org) 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License 7 * as published by the Free Software Foundation; either version 2 8 * of the License, or (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 18 */ 19 20#include <linux/types.h> 21#include <linux/pci.h> 22#include <linux/kernel.h> 23#include <linux/init.h> 24#include <linux/mm.h> 25#include <linux/console.h> 26#include <linux/tty.h> 27 28#include <asm/sibyte/bcm1480_regs.h> 29#include <asm/sibyte/bcm1480_scd.h> 30#include <asm/sibyte/board.h> 31#include <asm/io.h> 32 33/* 34 * Macros for calculating offsets into config space given a device 35 * structure or dev/fun/reg 36 */ 37#define CFGOFFSET(bus,devfn,where) (((bus)<<16)+((devfn)<<8)+(where)) 38#define CFGADDR(bus,devfn,where) CFGOFFSET((bus)->number,(devfn),where) 39 40static void *cfg_space; 41 42#define PCI_BUS_ENABLED 1 43#define PCI_DEVICE_MODE 2 44 45static int bcm1480_bus_status = 0; 46 47#define PCI_BRIDGE_DEVICE 0 48 49/* 50 * Read/write 32-bit values in config space. 51 */ 52static inline u32 READCFG32(u32 addr) 53{ 54 return *(u32 *)(cfg_space + (addr&~3)); 55} 56 57static inline void WRITECFG32(u32 addr, u32 data) 58{ 59 *(u32 *)(cfg_space + (addr & ~3)) = data; 60} 61 62int pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) 63{ 64 return dev->irq; 65} 66 67/* Do platform specific device initialization at pci_enable_device() time */ 68int pcibios_plat_dev_init(struct pci_dev *dev) 69{ 70 return 0; 71} 72 73/* 74 * Some checks before doing config cycles: 75 * In PCI Device Mode, hide everything on bus 0 except the LDT host 76 * bridge. Otherwise, access is controlled by bridge MasterEn bits. 77 */ 78static int bcm1480_pci_can_access(struct pci_bus *bus, int devfn) 79{ 80 u32 devno; 81 82 if (!(bcm1480_bus_status & (PCI_BUS_ENABLED | PCI_DEVICE_MODE))) 83 return 0; 84 85 if (bus->number == 0) { 86 devno = PCI_SLOT(devfn); 87 if (bcm1480_bus_status & PCI_DEVICE_MODE) 88 return 0; 89 else 90 return 1; 91 } else 92 return 1; 93} 94 95/* 96 * Read/write access functions for various sizes of values 97 * in config space. Return all 1's for disallowed accesses 98 * for a kludgy but adequate simulation of master aborts. 99 */ 100 101static int bcm1480_pcibios_read(struct pci_bus *bus, unsigned int devfn, 102 int where, int size, u32 * val) 103{ 104 u32 data = 0; 105 106 if ((size == 2) && (where & 1)) 107 return PCIBIOS_BAD_REGISTER_NUMBER; 108 else if ((size == 4) && (where & 3)) 109 return PCIBIOS_BAD_REGISTER_NUMBER; 110 111 if (bcm1480_pci_can_access(bus, devfn)) 112 data = READCFG32(CFGADDR(bus, devfn, where)); 113 else 114 data = 0xFFFFFFFF; 115 116 if (size == 1) 117 *val = (data >> ((where & 3) << 3)) & 0xff; 118 else if (size == 2) 119 *val = (data >> ((where & 3) << 3)) & 0xffff; 120 else 121 *val = data; 122 123 return PCIBIOS_SUCCESSFUL; 124} 125 126static int bcm1480_pcibios_write(struct pci_bus *bus, unsigned int devfn, 127 int where, int size, u32 val) 128{ 129 u32 cfgaddr = CFGADDR(bus, devfn, where); 130 u32 data = 0; 131 132 if ((size == 2) && (where & 1)) 133 return PCIBIOS_BAD_REGISTER_NUMBER; 134 else if ((size == 4) && (where & 3)) 135 return PCIBIOS_BAD_REGISTER_NUMBER; 136 137 if (!bcm1480_pci_can_access(bus, devfn)) 138 return PCIBIOS_BAD_REGISTER_NUMBER; 139 140 data = READCFG32(cfgaddr); 141 142 if (size == 1) 143 data = (data & ~(0xff << ((where & 3) << 3))) | 144 (val << ((where & 3) << 3)); 145 else if (size == 2) 146 data = (data & ~(0xffff << ((where & 3) << 3))) | 147 (val << ((where & 3) << 3)); 148 else 149 data = val; 150 151 WRITECFG32(cfgaddr, data); 152 153 return PCIBIOS_SUCCESSFUL; 154} 155 156struct pci_ops bcm1480_pci_ops = { 157 bcm1480_pcibios_read, 158 bcm1480_pcibios_write, 159}; 160 161static struct resource bcm1480_mem_resource = { 162 .name = "BCM1480 PCI MEM", 163 .start = 0x30000000UL, 164 .end = 0x3fffffffUL, 165 .flags = IORESOURCE_MEM, 166}; 167 168static struct resource bcm1480_io_resource = { 169 .name = "BCM1480 PCI I/O", 170 .start = 0x2c000000UL, 171 .end = 0x2dffffffUL, 172 .flags = IORESOURCE_IO, 173}; 174 175struct pci_controller bcm1480_controller = { 176 .pci_ops = &bcm1480_pci_ops, 177 .mem_resource = &bcm1480_mem_resource, 178 .io_resource = &bcm1480_io_resource, 179}; 180 181 182static int __init bcm1480_pcibios_init(void) 183{ 184 uint32_t cmdreg; 185 uint64_t reg; 186 extern int pci_probe_only; 187 188 /* CFE will assign PCI resources */ 189 pci_probe_only = 1; 190 191 /* Avoid ISA compat ranges. */ 192 PCIBIOS_MIN_IO = 0x00008000UL; 193 PCIBIOS_MIN_MEM = 0x01000000UL; 194 195 /* Set I/O resource limits. - unlimited for now to accomodate HT */ 196 ioport_resource.end = 0xffffffffUL; 197 iomem_resource.end = 0xffffffffUL; 198 199 cfg_space = ioremap(A_BCM1480_PHYS_PCI_CFG_MATCH_BITS, 16*1024*1024); 200 201 /* 202 * See if the PCI bus has been configured by the firmware. 203 */ 204 reg = __raw_readq(IOADDR(A_SCD_SYSTEM_CFG)); 205 if (!(reg & M_BCM1480_SYS_PCI_HOST)) { 206 bcm1480_bus_status |= PCI_DEVICE_MODE; 207 } else { 208 cmdreg = READCFG32(CFGOFFSET(0, PCI_DEVFN(PCI_BRIDGE_DEVICE, 0), 209 PCI_COMMAND)); 210 if (!(cmdreg & PCI_COMMAND_MASTER)) { 211 printk 212 ("PCI: Skipping PCI probe. Bus is not initialized.\n"); 213 iounmap(cfg_space); 214 return 1; 215 } 216 bcm1480_bus_status |= PCI_BUS_ENABLED; 217 } 218 219 /* turn on ExpMemEn */ 220 cmdreg = READCFG32(CFGOFFSET(0, PCI_DEVFN(PCI_BRIDGE_DEVICE, 0), 0x40)); 221 WRITECFG32(CFGOFFSET(0, PCI_DEVFN(PCI_BRIDGE_DEVICE, 0), 0x40), 222 cmdreg | 0x10); 223 cmdreg = READCFG32(CFGOFFSET(0, PCI_DEVFN(PCI_BRIDGE_DEVICE, 0), 0x40)); 224 225 226 set_io_port_base((unsigned long) 227 ioremap(A_BCM1480_PHYS_PCI_IO_MATCH_BYTES, 65536)); 228 isa_slot_offset = (unsigned long) 229 ioremap(A_BCM1480_PHYS_PCI_MEM_MATCH_BYTES, 1024*1024); 230 231 register_pci_controller(&bcm1480_controller); 232 233#ifdef CONFIG_VGA_CONSOLE 234 take_over_console(&vga_con,0,MAX_NR_CONSOLES-1,1); 235#endif 236 return 0; 237} 238 239arch_initcall(bcm1480_pcibios_init); 240