1/*
2 * Copyright (C) 2000 RidgeRun, Inc.
3 * Author: RidgeRun, Inc.
4 *   glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
5 *
6 * Copyright 2001 MontaVista Software Inc.
7 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
8 * Copyright (C) 2000, 2001 Ralf Baechle (ralf@gnu.org)
9 *
10 * Copyright 2004 PMC-Sierra
11 * Author: Manish Lachwani (lachwani@pmc-sierra.com)
12 *
13 *  This program is free software; you can redistribute  it and/or modify it
14 *  under  the terms of  the GNU General  Public License as published by the
15 *  Free Software Foundation;  either version 2 of the  License, or (at your
16 *  option) any later version.
17 *
18 *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
19 *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
20 *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
21 *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
22 *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
24 *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
25 *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
26 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 *  You should have received a copy of the  GNU General Public License along
30 *  with this program; if not, write  to the Free Software Foundation, Inc.,
31 *  675 Mass Ave, Cambridge, MA 02139, USA.
32 *
33 *  Copyright (C) 2004 MontaVista Software Inc.
34 *  Author: Manish Lachwani, mlachwani@mvista.com
35 *
36 */
37#include <linux/errno.h>
38#include <linux/init.h>
39#include <linux/kernel_stat.h>
40#include <linux/module.h>
41#include <linux/signal.h>
42#include <linux/sched.h>
43#include <linux/types.h>
44#include <linux/interrupt.h>
45#include <linux/ioport.h>
46#include <linux/timex.h>
47#include <linux/slab.h>
48#include <linux/random.h>
49#include <asm/bitops.h>
50#include <asm/bootinfo.h>
51#include <asm/io.h>
52#include <asm/irq.h>
53#include <asm/mipsregs.h>
54#include <asm/system.h>
55
56static struct irqaction cascade_mv64340 = {
57	no_action, IRQF_DISABLED, CPU_MASK_NONE, "MV64340-Cascade", NULL, NULL
58};
59
60void __init arch_init_irq(void)
61{
62	/*
63	 * Clear all of the interrupts while we change the able around a bit.
64	 * int-handler is not on bootstrap
65	 */
66	clear_c0_status(ST0_IM | ST0_BEV);
67
68	rm7k_cpu_irq_init();
69
70	/* set up the cascading interrupts */
71	setup_irq(8, &cascade_mv64340);		/* unmask intControl IM8, IRQ 9 */
72	mv64340_irq_init(16);
73
74	set_c0_status(ST0_IM); /* IE in the status register */
75
76}
77
78asmlinkage void plat_irq_dispatch(void)
79{
80	unsigned int pending = read_c0_cause() & read_c0_status();
81
82	if (pending & STATUSF_IP0)
83		do_IRQ(0);
84	else if (pending & STATUSF_IP1)
85		do_IRQ(1);
86	else if (pending & STATUSF_IP2)
87		do_IRQ(2);
88	else if (pending & STATUSF_IP3)
89		do_IRQ(3);
90	else if (pending & STATUSF_IP4)
91		do_IRQ(4);
92	else if (pending & STATUSF_IP5)
93		do_IRQ(5);
94	else if (pending & STATUSF_IP6)
95		do_IRQ(6);
96	else if (pending & STATUSF_IP7)
97		do_IRQ(7);
98	else {
99		/*
100		 * Now look at the extended interrupts
101		 */
102		pending = (read_c0_cause() & (read_c0_intcontrol() << 8)) >> 16;
103
104		if (pending & STATUSF_IP8)
105			ll_mv64340_irq();
106		else
107			spurious_interrupt();
108	}
109}
110