1/* 2 * sc-rm7k.c: RM7000 cache management functions. 3 * 4 * Copyright (C) 1997, 2001, 2003, 2004 Ralf Baechle (ralf@linux-mips.org) 5 */ 6 7#undef DEBUG 8 9#include <linux/init.h> 10#include <linux/kernel.h> 11#include <linux/mm.h> 12#include <linux/bitops.h> 13 14#include <asm/addrspace.h> 15#include <asm/bcache.h> 16#include <asm/cacheops.h> 17#include <asm/mipsregs.h> 18#include <asm/processor.h> 19#include <asm/cacheflush.h> /* for run_uncached() */ 20 21/* Primary cache parameters. */ 22#define sc_lsize 32 23#define tc_pagesize (32*128) 24 25/* Secondary cache parameters. */ 26#define scache_size (256*1024) /* Fixed to 256KiB on RM7000 */ 27 28extern unsigned long icache_way_size, dcache_way_size; 29 30#include <asm/r4kcache.h> 31 32int rm7k_tcache_enabled; 33 34static void rm7k_sc_wback_inv(unsigned long addr, unsigned long size) 35{ 36 unsigned long end, a; 37 38 pr_debug("rm7k_sc_wback_inv[%08lx,%08lx]", addr, size); 39 40 /* Catch bad driver code */ 41 BUG_ON(size == 0); 42 43 blast_scache_range(addr, addr + size); 44 45 if (!rm7k_tcache_enabled) 46 return; 47 48 a = addr & ~(tc_pagesize - 1); 49 end = (addr + size - 1) & ~(tc_pagesize - 1); 50 while(1) { 51 invalidate_tcache_page(a); /* Page_Invalidate_T */ 52 if (a == end) 53 break; 54 a += tc_pagesize; 55 } 56} 57 58static void rm7k_sc_inv(unsigned long addr, unsigned long size) 59{ 60 unsigned long end, a; 61 62 pr_debug("rm7k_sc_inv[%08lx,%08lx]", addr, size); 63 64 /* Catch bad driver code */ 65 BUG_ON(size == 0); 66 67 blast_inv_scache_range(addr, addr + size); 68 69 if (!rm7k_tcache_enabled) 70 return; 71 72 a = addr & ~(tc_pagesize - 1); 73 end = (addr + size - 1) & ~(tc_pagesize - 1); 74 while(1) { 75 invalidate_tcache_page(a); /* Page_Invalidate_T */ 76 if (a == end) 77 break; 78 a += tc_pagesize; 79 } 80} 81 82/* 83 * This function is executed in uncached address space. 84 */ 85static __init void __rm7k_sc_enable(void) 86{ 87 int i; 88 89 set_c0_config(RM7K_CONF_SE); 90 91 write_c0_taglo(0); 92 write_c0_taghi(0); 93 94 for (i = 0; i < scache_size; i += sc_lsize) { 95 __asm__ __volatile__ ( 96 ".set noreorder\n\t" 97 ".set mips3\n\t" 98 "cache %1, (%0)\n\t" 99 ".set mips0\n\t" 100 ".set reorder" 101 : 102 : "r" (CKSEG0ADDR(i)), "i" (Index_Store_Tag_SD)); 103 } 104} 105 106static __init void rm7k_sc_enable(void) 107{ 108 if (read_c0_config() & RM7K_CONF_SE) 109 return; 110 111 printk(KERN_INFO "Enabling secondary cache...\n"); 112 run_uncached(__rm7k_sc_enable); 113} 114 115static void rm7k_sc_disable(void) 116{ 117 clear_c0_config(RM7K_CONF_SE); 118} 119 120struct bcache_ops rm7k_sc_ops = { 121 .bc_enable = rm7k_sc_enable, 122 .bc_disable = rm7k_sc_disable, 123 .bc_wback_inv = rm7k_sc_wback_inv, 124 .bc_inv = rm7k_sc_inv 125}; 126 127void __init rm7k_sc_init(void) 128{ 129 struct cpuinfo_mips *c = ¤t_cpu_data; 130 unsigned int config = read_c0_config(); 131 132 if ((config & RM7K_CONF_SC)) 133 return; 134 135 c->scache.linesz = sc_lsize; 136 c->scache.ways = 4; 137 c->scache.waybit= __ffs(scache_size / c->scache.ways); 138 c->scache.waysize = scache_size / c->scache.ways; 139 c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways); 140 printk(KERN_INFO "Secondary cache size %dK, linesize %d bytes.\n", 141 (scache_size >> 10), sc_lsize); 142 143 if (!(config & RM7K_CONF_SE)) 144 rm7k_sc_enable(); 145 146 /* 147 * While we're at it let's deal with the tertiary cache. 148 */ 149 if (!(config & RM7K_CONF_TC)) { 150 151 /* 152 * We can't enable the L3 cache yet. There may be board-specific 153 * magic necessary to turn it on, and blindly asking the CPU to 154 * start using it would may give cache errors. 155 * 156 * Also, board-specific knowledge may allow us to use the 157 * CACHE Flash_Invalidate_T instruction if the tag RAM supports 158 * it, and may specify the size of the L3 cache so we don't have 159 * to probe it. 160 */ 161 printk(KERN_INFO "Tertiary cache present, %s enabled\n", 162 (config & RM7K_CONF_TE) ? "already" : "not (yet)"); 163 164 if ((config & RM7K_CONF_TE)) 165 rm7k_tcache_enabled = 1; 166 } 167 168 bcops = &rm7k_sc_ops; 169} 170