1/* 2 * linux/arch/mips/kernel/proc.c 3 * 4 * Copyright (C) 1995, 1996, 2001 Ralf Baechle 5 * Copyright (C) 2001, 2004 MIPS Technologies, Inc. 6 * Copyright (C) 2004 Maciej W. Rozycki 7 */ 8#include <linux/delay.h> 9#include <linux/kernel.h> 10#include <linux/sched.h> 11#include <linux/seq_file.h> 12#include <asm/bootinfo.h> 13#include <asm/cpu.h> 14#include <asm/cpu-features.h> 15#include <asm/mipsregs.h> 16#include <asm/processor.h> 17#include <asm/watch.h> 18 19unsigned int vced_count, vcei_count; 20 21static const char *cpu_name[] = { 22 [CPU_UNKNOWN] = "unknown", 23 [CPU_R2000] = "R2000", 24 [CPU_R3000] = "R3000", 25 [CPU_R3000A] = "R3000A", 26 [CPU_R3041] = "R3041", 27 [CPU_R3051] = "R3051", 28 [CPU_R3052] = "R3052", 29 [CPU_R3081] = "R3081", 30 [CPU_R3081E] = "R3081E", 31 [CPU_R4000PC] = "R4000PC", 32 [CPU_R4000SC] = "R4000SC", 33 [CPU_R4000MC] = "R4000MC", 34 [CPU_R4200] = "R4200", 35 [CPU_R4400PC] = "R4400PC", 36 [CPU_R4400SC] = "R4400SC", 37 [CPU_R4400MC] = "R4400MC", 38 [CPU_R4600] = "R4600", 39 [CPU_R6000] = "R6000", 40 [CPU_R6000A] = "R6000A", 41 [CPU_R8000] = "R8000", 42 [CPU_R10000] = "R10000", 43 [CPU_R12000] = "R12000", 44 [CPU_R14000] = "R14000", 45 [CPU_R4300] = "R4300", 46 [CPU_R4650] = "R4650", 47 [CPU_R4700] = "R4700", 48 [CPU_R5000] = "R5000", 49 [CPU_R5000A] = "R5000A", 50 [CPU_R4640] = "R4640", 51 [CPU_NEVADA] = "Nevada", 52 [CPU_RM7000] = "RM7000", 53 [CPU_RM9000] = "RM9000", 54 [CPU_R5432] = "R5432", 55 [CPU_4KC] = "MIPS 4Kc", 56 [CPU_5KC] = "MIPS 5Kc", 57 [CPU_R4310] = "R4310", 58 [CPU_SB1] = "SiByte SB1", 59 [CPU_SB1A] = "SiByte SB1A", 60 [CPU_TX3912] = "TX3912", 61 [CPU_TX3922] = "TX3922", 62 [CPU_TX3927] = "TX3927", 63 [CPU_AU1000] = "Au1000", 64 [CPU_AU1500] = "Au1500", 65 [CPU_AU1100] = "Au1100", 66 [CPU_AU1550] = "Au1550", 67 [CPU_AU1200] = "Au1200", 68 [CPU_4KEC] = "MIPS 4KEc", 69 [CPU_4KSC] = "MIPS 4KSc", 70 [CPU_VR41XX] = "NEC Vr41xx", 71 [CPU_R5500] = "R5500", 72 [CPU_TX49XX] = "TX49xx", 73 [CPU_20KC] = "MIPS 20Kc", 74 [CPU_24K] = "MIPS 24K", 75 [CPU_25KF] = "MIPS 25Kf", 76 [CPU_34K] = "MIPS 34K", 77 [CPU_74K] = "MIPS 74K", 78 [CPU_VR4111] = "NEC VR4111", 79 [CPU_VR4121] = "NEC VR4121", 80 [CPU_VR4122] = "NEC VR4122", 81 [CPU_VR4131] = "NEC VR4131", 82 [CPU_VR4133] = "NEC VR4133", 83 [CPU_VR4181] = "NEC VR4181", 84 [CPU_VR4181A] = "NEC VR4181A", 85 [CPU_SR71000] = "Sandcraft SR71000", 86 [CPU_PR4450] = "Philips PR4450", 87 [CPU_BCM4710] = "Broadcom BCM4710", 88 [CPU_BCM3302] = "Broadcom BCM3302", 89}; 90 91 92static int show_cpuinfo(struct seq_file *m, void *v) 93{ 94 unsigned long n = (unsigned long) v - 1; 95 unsigned int version = cpu_data[n].processor_id; 96 unsigned int fp_vers = cpu_data[n].fpu_id; 97 char fmt [64]; 98 extern unsigned long unaligned_instructions; 99 100#ifdef CONFIG_SMP 101 if (!cpu_isset(n, cpu_online_map)) 102 return 0; 103#endif 104 105 /* 106 * For the first processor also print the system type 107 */ 108 if (n == 0) 109 seq_printf(m, "system type\t\t: %s\n", get_system_type()); 110 111 seq_printf(m, "processor\t\t: %ld\n", n); 112 sprintf(fmt, "cpu model\t\t: %%s V%%d.%%d%s\n", 113 cpu_data[n].options & MIPS_CPU_FPU ? " FPU V%d.%d" : ""); 114 seq_printf(m, fmt, cpu_name[cpu_data[n].cputype <= CPU_LAST ? 115 cpu_data[n].cputype : CPU_UNKNOWN], 116 (version >> 4) & 0x0f, version & 0x0f, 117 (fp_vers >> 4) & 0x0f, fp_vers & 0x0f); 118 seq_printf(m, "BogoMIPS\t\t: %lu.%02lu\n", 119 cpu_data[n].udelay_val / (500000/HZ), 120 (cpu_data[n].udelay_val / (5000/HZ)) % 100); 121 seq_printf(m, "wait instruction\t: %s\n", cpu_wait ? "yes" : "no"); 122 seq_printf(m, "microsecond timers\t: %s\n", 123 cpu_has_counter ? "yes" : "no"); 124 seq_printf(m, "tlb_entries\t\t: %d\n", cpu_data[n].tlbsize); 125 seq_printf(m, "extra interrupt vector\t: %s\n", 126 cpu_has_divec ? "yes" : "no"); 127 seq_printf(m, "hardware watchpoint\t: %s\n", 128 cpu_has_watch ? "yes" : "no"); 129 seq_printf(m, "ASEs implemented\t:%s%s%s%s%s%s\n", 130 cpu_has_mips16 ? " mips16" : "", 131 cpu_has_mdmx ? " mdmx" : "", 132 cpu_has_mips3d ? " mips3d" : "", 133 cpu_has_smartmips ? " smartmips" : "", 134 cpu_has_dsp ? " dsp" : "", 135 cpu_has_mipsmt ? " mt" : "" 136 ); 137 138 sprintf(fmt, "VCE%%c exceptions\t\t: %s\n", 139 cpu_has_vce ? "%u" : "not available"); 140 seq_printf(m, fmt, 'D', vced_count); 141 seq_printf(m, fmt, 'I', vcei_count); 142 seq_printf(m, "\n"); 143 144 seq_printf(m, "unaligned_instructions\t: %lu\n", unaligned_instructions); 145 146#ifdef CONFIG_BCM47XX 147 seq_printf(m, "dcache hits\t\t: %u\n", read_perf_cntr(0)); 148 seq_printf(m, "dcache misses\t\t: %u\n", read_perf_cntr(1)); 149 seq_printf(m, "icache hits\t\t: %u\n", read_perf_cntr(2)); 150 seq_printf(m, "icache misses\t\t: %u\n", read_perf_cntr(3)); 151 seq_printf(m, "instructions\t\t: %u\n", read_perf_cntr(4)); 152#endif 153 154 return 0; 155} 156 157static void *c_start(struct seq_file *m, loff_t *pos) 158{ 159 unsigned long i = *pos; 160 161 return i < NR_CPUS ? (void *) (i + 1) : NULL; 162} 163 164static void *c_next(struct seq_file *m, void *v, loff_t *pos) 165{ 166 ++*pos; 167 return c_start(m, pos); 168} 169 170static void c_stop(struct seq_file *m, void *v) 171{ 172} 173 174struct seq_operations cpuinfo_op = { 175 .start = c_start, 176 .next = c_next, 177 .stop = c_stop, 178 .show = show_cpuinfo, 179}; 180