1/* 2 * setup.c 3 * 4 * BRIEF MODULE DESCRIPTION 5 * Momentum Computer Ocelot (CP7000) - board dependent boot routines 6 * 7 * Copyright (C) 1996, 1997, 2001, 06 Ralf Baechle (ralf@linux-mips.org) 8 * Copyright (C) 2000 RidgeRun, Inc. 9 * Copyright (C) 2001 Red Hat, Inc. 10 * Copyright (C) 2002 Momentum Computer 11 * 12 * Author: RidgeRun, Inc. 13 * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com 14 * 15 * Copyright 2001 MontaVista Software Inc. 16 * Author: jsun@mvista.com or jsun@junsun.net 17 * 18 * This program is free software; you can redistribute it and/or modify it 19 * under the terms of the GNU General Public License as published by the 20 * Free Software Foundation; either version 2 of the License, or (at your 21 * option) any later version. 22 * 23 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 26 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 29 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 30 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * You should have received a copy of the GNU General Public License along 35 * with this program; if not, write to the Free Software Foundation, Inc., 36 * 675 Mass Ave, Cambridge, MA 02139, USA. 37 * 38 */ 39#include <linux/init.h> 40#include <linux/kernel.h> 41#include <linux/types.h> 42#include <linux/mm.h> 43#include <linux/swap.h> 44#include <linux/ioport.h> 45#include <linux/sched.h> 46#include <linux/interrupt.h> 47#include <linux/pci.h> 48#include <linux/timex.h> 49#include <linux/vmalloc.h> 50#include <linux/pm.h> 51 52#include <asm/time.h> 53#include <asm/bootinfo.h> 54#include <asm/page.h> 55#include <asm/io.h> 56#include <asm/irq.h> 57#include <asm/pci.h> 58#include <asm/processor.h> 59#include <asm/reboot.h> 60#include <asm/traps.h> 61#include <linux/bootmem.h> 62#include <linux/initrd.h> 63#include <asm/gt64120.h> 64#include "ocelot_pld.h" 65 66unsigned long gt64120_base = KSEG1ADDR(GT_DEF_BASE); 67 68/* These functions are used for rebooting or halting the machine*/ 69extern void momenco_ocelot_restart(char *command); 70extern void momenco_ocelot_halt(void); 71extern void momenco_ocelot_power_off(void); 72 73extern void momenco_ocelot_irq_setup(void); 74 75static char reset_reason; 76 77#define ENTRYLO(x) ((pte_val(pfn_pte((x) >> PAGE_SHIFT, PAGE_KERNEL_UNCACHED)) >> 6)|1) 78 79static void __init setup_l3cache(unsigned long size); 80 81/* setup code for a handoff from a version 1 PMON 2000 PROM */ 82static void PMON_v1_setup(void) 83{ 84 /* A wired TLB entry for the GT64120A and the serial port. The 85 GT64120A is going to be hit on every IRQ anyway - there's 86 absolutely no point in letting it be a random TLB entry, as 87 it'll just cause needless churning of the TLB. And we use 88 the other half for the serial port, which is just a PITA 89 otherwise :) 90 91 Device Physical Virtual 92 GT64120 Internal Regs 0x24000000 0xe0000000 93 UARTs (CS2) 0x2d000000 0xe0001000 94 */ 95 add_wired_entry(ENTRYLO(0x24000000), ENTRYLO(0x2D000000), 0xe0000000, PM_4K); 96 97 /* Also a temporary entry to let us talk to the Ocelot PLD and NVRAM 98 in the CS[012] region. We can't use ioremap() yet. The NVRAM 99 is a ST M48T37Y, which includes NVRAM, RTC, and Watchdog functions. 100 101 Ocelot PLD (CS0) 0x2c000000 0xe0020000 102 NVRAM 0x2c800000 0xe0030000 103 */ 104 105 add_temporary_entry(ENTRYLO(0x2C000000), ENTRYLO(0x2d000000), 0xe0020000, PM_64K); 106 107 /* Relocate the CS3/BootCS region */ 108 GT_WRITE(GT_CS3BOOTLD_OFS, 0x2f000000 >> 21); 109 110 /* Relocate CS[012] */ 111 GT_WRITE(GT_CS20LD_OFS, 0x2c000000 >> 21); 112 113 /* Relocate the GT64120A itself... */ 114 GT_WRITE(GT_ISD_OFS, 0x24000000 >> 21); 115 mb(); 116 gt64120_base = 0xe0000000; 117 118 /* ...and the PCI0 view of it. */ 119 GT_WRITE(GT_PCI0_CFGADDR_OFS, 0x80000020); 120 GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x24000000); 121 GT_WRITE(GT_PCI0_CFGADDR_OFS, 0x80000024); 122 GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x24000001); 123} 124 125/* setup code for a handoff from a version 2 PMON 2000 PROM */ 126void PMON_v2_setup() 127{ 128 /* A wired TLB entry for the GT64120A and the serial port. The 129 GT64120A is going to be hit on every IRQ anyway - there's 130 absolutely no point in letting it be a random TLB entry, as 131 it'll just cause needless churning of the TLB. And we use 132 the other half for the serial port, which is just a PITA 133 otherwise :) 134 135 Device Physical Virtual 136 GT64120 Internal Regs 0xf4000000 0xe0000000 137 UARTs (CS2) 0xfd000000 0xe0001000 138 */ 139 add_wired_entry(ENTRYLO(0xf4000000), ENTRYLO(0xfD000000), 0xe0000000, PM_4K); 140 141 /* Also a temporary entry to let us talk to the Ocelot PLD and NVRAM 142 in the CS[012] region. We can't use ioremap() yet. The NVRAM 143 is a ST M48T37Y, which includes NVRAM, RTC, and Watchdog functions. 144 145 Ocelot PLD (CS0) 0xfc000000 0xe0020000 146 NVRAM 0xfc800000 0xe0030000 147 */ 148 add_temporary_entry(ENTRYLO(0xfC000000), ENTRYLO(0xfd000000), 0xe0020000, PM_64K); 149 150 gt64120_base = 0xe0000000; 151} 152 153void __init plat_mem_setup(void) 154{ 155 void (*l3func)(unsigned long)=KSEG1ADDR(&setup_l3cache); 156 unsigned int tmpword; 157 158 _machine_restart = momenco_ocelot_restart; 159 _machine_halt = momenco_ocelot_halt; 160 pm_power_off = momenco_ocelot_power_off; 161 162 /* 163 * initrd_start = (unsigned long)ocelot_initrd_start; 164 * initrd_end = (unsigned long)ocelot_initrd_start + (ulong)ocelot_initrd_size; 165 * initrd_below_start_ok = 1; 166 */ 167 168 /* do handoff reconfiguration */ 169 if (gt64120_base == KSEG1ADDR(GT_DEF_BASE)) 170 PMON_v1_setup(); 171 else 172 PMON_v2_setup(); 173 174 /* Turn off the Bit-Error LED */ 175 OCELOT_PLD_WRITE(0x80, INTCLR); 176 177 /* Relocate all the PCI1 stuff, not that we use it */ 178 GT_WRITE(GT_PCI1IOLD_OFS, 0x30000000 >> 21); 179 GT_WRITE(GT_PCI1M0LD_OFS, 0x32000000 >> 21); 180 GT_WRITE(GT_PCI1M1LD_OFS, 0x34000000 >> 21); 181 182 /* Relocate PCI0 I/O and Mem0 */ 183 GT_WRITE(GT_PCI0IOLD_OFS, 0x20000000 >> 21); 184 GT_WRITE(GT_PCI0M0LD_OFS, 0x22000000 >> 21); 185 186 /* Relocate PCI0 Mem1 */ 187 GT_WRITE(GT_PCI0M1LD_OFS, 0x36000000 >> 21); 188 189 /* For the initial programming, we assume 512MB configuration */ 190 /* Relocate the CPU's view of the RAM... */ 191 GT_WRITE(GT_SCS10LD_OFS, 0); 192 GT_WRITE(GT_SCS10HD_OFS, 0x0fe00000 >> 21); 193 GT_WRITE(GT_SCS32LD_OFS, 0x10000000 >> 21); 194 GT_WRITE(GT_SCS32HD_OFS, 0x0fe00000 >> 21); 195 196 GT_WRITE(GT_SCS1LD_OFS, 0xff); 197 GT_WRITE(GT_SCS1HD_OFS, 0x00); 198 GT_WRITE(GT_SCS0LD_OFS, 0); 199 GT_WRITE(GT_SCS0HD_OFS, 0xff); 200 GT_WRITE(GT_SCS3LD_OFS, 0xff); 201 GT_WRITE(GT_SCS3HD_OFS, 0x00); 202 GT_WRITE(GT_SCS2LD_OFS, 0); 203 GT_WRITE(GT_SCS2HD_OFS, 0xff); 204 205 /* ...and the PCI0 view of it. */ 206 GT_WRITE(GT_PCI0_CFGADDR_OFS, 0x80000010); 207 GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x00000000); 208 GT_WRITE(GT_PCI0_CFGADDR_OFS, 0x80000014); 209 GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x10000000); 210 GT_WRITE(GT_PCI0_BS_SCS10_OFS, 0x0ffff000); 211 GT_WRITE(GT_PCI0_BS_SCS32_OFS, 0x0ffff000); 212 213 tmpword = OCELOT_PLD_READ(BOARDREV); 214 if (tmpword < 26) 215 printk("Momenco Ocelot: Board Assembly Rev. %c\n", 'A'+tmpword); 216 else 217 printk("Momenco Ocelot: Board Assembly Revision #0x%x\n", tmpword); 218 219 tmpword = OCELOT_PLD_READ(PLD1_ID); 220 printk("PLD 1 ID: %d.%d\n", tmpword>>4, tmpword&15); 221 tmpword = OCELOT_PLD_READ(PLD2_ID); 222 printk("PLD 2 ID: %d.%d\n", tmpword>>4, tmpword&15); 223 tmpword = OCELOT_PLD_READ(RESET_STATUS); 224 printk("Reset reason: 0x%x\n", tmpword); 225 reset_reason = tmpword; 226 OCELOT_PLD_WRITE(0xff, RESET_STATUS); 227 228 tmpword = OCELOT_PLD_READ(BOARD_STATUS); 229 printk("Board Status register: 0x%02x\n", tmpword); 230 printk(" - User jumper: %s\n", (tmpword & 0x80)?"installed":"absent"); 231 printk(" - Boot flash write jumper: %s\n", (tmpword&0x40)?"installed":"absent"); 232 printk(" - Tulip PHY %s connected\n", (tmpword&0x10)?"is":"not"); 233 printk(" - L3 Cache size: %d MiB\n", (1<<((tmpword&12) >> 2))&~1); 234 printk(" - SDRAM size: %d MiB\n", 1<<(6+(tmpword&3))); 235 236 if (tmpword&12) 237 l3func((1<<(((tmpword&12) >> 2)+20))); 238 239 switch(tmpword &3) { 240 case 3: 241 /* 512MiB */ 242 /* Decoders are allready set -- just add the 243 * appropriate region */ 244 add_memory_region( 0x40<<20, 0xC0<<20, BOOT_MEM_RAM); 245 add_memory_region(0x100<<20, 0x100<<20, BOOT_MEM_RAM); 246 break; 247 case 2: 248 /* 256MiB -- two banks of 128MiB */ 249 GT_WRITE(GT_SCS10HD_OFS, 0x07e00000 >> 21); 250 GT_WRITE(GT_SCS32LD_OFS, 0x08000000 >> 21); 251 GT_WRITE(GT_SCS32HD_OFS, 0x0fe00000 >> 21); 252 253 GT_WRITE(GT_SCS0HD_OFS, 0x7f); 254 GT_WRITE(GT_SCS2LD_OFS, 0x80); 255 GT_WRITE(GT_SCS2HD_OFS, 0xff); 256 257 /* reconfigure the PCI0 interface view of memory */ 258 GT_WRITE(GT_PCI0_CFGADDR_OFS, 0x80000014); 259 GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x08000000); 260 GT_WRITE(GT_PCI0_BS_SCS10_OFS, 0x0ffff000); 261 GT_WRITE(GT_PCI0_BS_SCS32_OFS, 0x0ffff000); 262 263 add_memory_region(0x40<<20, 0x40<<20, BOOT_MEM_RAM); 264 add_memory_region(0x80<<20, 0x80<<20, BOOT_MEM_RAM); 265 break; 266 case 1: 267 /* 128MiB -- 64MiB per bank */ 268 GT_WRITE(GT_SCS10HD_OFS, 0x03e00000 >> 21); 269 GT_WRITE(GT_SCS32LD_OFS, 0x04000000 >> 21); 270 GT_WRITE(GT_SCS32HD_OFS, 0x07e00000 >> 21); 271 272 GT_WRITE(GT_SCS0HD_OFS, 0x3f); 273 GT_WRITE(GT_SCS2LD_OFS, 0x40); 274 GT_WRITE(GT_SCS2HD_OFS, 0x7f); 275 276 /* reconfigure the PCI0 interface view of memory */ 277 GT_WRITE(GT_PCI0_CFGADDR_OFS, 0x80000014); 278 GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x04000000); 279 GT_WRITE(GT_PCI0_BS_SCS10_OFS, 0x03fff000); 280 GT_WRITE(GT_PCI0_BS_SCS32_OFS, 0x03fff000); 281 282 /* add the appropriate region */ 283 add_memory_region(0x40<<20, 0x40<<20, BOOT_MEM_RAM); 284 break; 285 case 0: 286 /* 64MiB */ 287 GT_WRITE(GT_SCS10HD_OFS, 0x01e00000 >> 21); 288 GT_WRITE(GT_SCS32LD_OFS, 0x02000000 >> 21); 289 GT_WRITE(GT_SCS32HD_OFS, 0x03e00000 >> 21); 290 291 GT_WRITE(GT_SCS0HD_OFS, 0x1f); 292 GT_WRITE(GT_SCS2LD_OFS, 0x20); 293 GT_WRITE(GT_SCS2HD_OFS, 0x3f); 294 295 /* reconfigure the PCI0 interface view of memory */ 296 GT_WRITE(GT_PCI0_CFGADDR_OFS, 0x80000014); 297 GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x04000000); 298 GT_WRITE(GT_PCI0_BS_SCS10_OFS, 0x01fff000); 299 GT_WRITE(GT_PCI0_BS_SCS32_OFS, 0x01fff000); 300 301 break; 302 } 303 304 /* Fix up the DiskOnChip mapping */ 305 GT_WRITE(GT_DEV_B3_OFS, 0xfef73); 306} 307 308extern int rm7k_tcache_enabled; 309/* 310 * This runs in KSEG1. See the verbiage in rm7k.c::probe_scache() 311 */ 312#define Page_Invalidate_T 0x16 313static void __init setup_l3cache(unsigned long size) 314{ 315 int register i; 316 unsigned long tmp; 317 318 printk("Enabling L3 cache..."); 319 320 /* Enable the L3 cache in the GT64120A's CPU Configuration register */ 321 tmp = GT_READ(GT_CPU_OFS); 322 GT_WRITE(GT_CPU_OFS, tmp | (1<<14)); 323 324 /* Enable the L3 cache in the CPU */ 325 set_c0_config(1<<12 /* CONF_TE */); 326 327 /* Clear the cache */ 328 write_c0_taglo(0); 329 write_c0_taghi(0); 330 331 for (i=0; i < size; i+= 4096) { 332 __asm__ __volatile__ ( 333 ".set noreorder\n\t" 334 ".set mips3\n\t" 335 "cache %1, (%0)\n\t" 336 ".set mips0\n\t" 337 ".set reorder" 338 : 339 : "r" (KSEG0ADDR(i)), 340 "i" (Page_Invalidate_T)); 341 } 342 343 /* Let the RM7000 MM code know that the tertiary cache is enabled */ 344 rm7k_tcache_enabled = 1; 345 346 printk("Done\n"); 347} 348 349 350/* This needs to be one of the first initcalls, because no I/O port access 351 can work before this */ 352 353static int io_base_ioremap(void) 354{ 355 void *io_remap_range = ioremap(GT_PCI_IO_BASE, GT_PCI_IO_SIZE); 356 357 if (!io_remap_range) { 358 panic("Could not ioremap I/O port range"); 359 } 360 set_io_port_base(io_remap_range - GT_PCI_IO_BASE); 361 362 return 0; 363} 364 365module_init(io_base_ioremap); 366