1/*
2 * Setup pointers to hardware dependent routines.
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License.  See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 1996, 1997, 2004, 05 by Ralf Baechle (ralf@linux-mips.org)
9 * Copyright (C) 2001, 2002, 2003 by Liam Davies (ldavies@agile.tv)
10 *
11 */
12#include <linux/interrupt.h>
13#include <linux/init.h>
14#include <linux/pm.h>
15
16#include <asm/bootinfo.h>
17#include <asm/time.h>
18#include <asm/io.h>
19#include <asm/reboot.h>
20#include <asm/gt64120.h>
21
22#include <cobalt.h>
23
24extern void cobalt_machine_restart(char *command);
25extern void cobalt_machine_halt(void);
26extern void cobalt_machine_power_off(void);
27
28const char *get_system_type(void)
29{
30	switch (cobalt_board_id) {
31		case COBALT_BRD_ID_QUBE1:
32			return "Cobalt Qube";
33		case COBALT_BRD_ID_RAQ1:
34			return "Cobalt RaQ";
35		case COBALT_BRD_ID_QUBE2:
36			return "Cobalt Qube2";
37		case COBALT_BRD_ID_RAQ2:
38			return "Cobalt RaQ2";
39	}
40	return "MIPS Cobalt";
41}
42
43void __init plat_timer_setup(struct irqaction *irq)
44{
45	/* Load timer value for HZ (TCLK is 50MHz) */
46	GT_WRITE(GT_TC0_OFS, 50*1000*1000 / HZ);
47
48	/* Enable timer */
49	GT_WRITE(GT_TC_CONTROL_OFS, GT_TC_CONTROL_ENTC0_MSK | GT_TC_CONTROL_SELTC0_MSK);
50
51	/* Register interrupt */
52	setup_irq(COBALT_GALILEO_IRQ, irq);
53
54	/* Enable interrupt */
55	GT_WRITE(GT_INTRMASK_OFS, GT_INTR_T0EXP_MSK | GT_READ(GT_INTRMASK_OFS));
56}
57
58/*
59 * Cobalt doesn't have PS/2 keyboard/mouse interfaces,
60 * keyboard conntroller is never used.
61 * Also PCI-ISA bridge DMA contoroller is never used.
62 */
63static struct resource cobalt_reserved_resources[] = {
64	{	/* dma1 */
65		.start	= 0x00,
66		.end	= 0x1f,
67		.name	= "reserved",
68		.flags	= IORESOURCE_BUSY | IORESOURCE_IO,
69	},
70	{	/* keyboard */
71		.start	= 0x60,
72		.end	= 0x6f,
73		.name	= "reserved",
74		.flags	= IORESOURCE_BUSY | IORESOURCE_IO,
75	},
76	{	/* dma page reg */
77		.start	= 0x80,
78		.end	= 0x8f,
79		.name	= "reserved",
80		.flags	= IORESOURCE_BUSY | IORESOURCE_IO,
81	},
82	{	/* dma2 */
83		.start	= 0xc0,
84		.end	= 0xdf,
85		.name	= "reserved",
86		.flags	= IORESOURCE_BUSY | IORESOURCE_IO,
87	},
88};
89
90void __init plat_mem_setup(void)
91{
92	int i;
93
94	_machine_restart = cobalt_machine_restart;
95	_machine_halt = cobalt_machine_halt;
96	pm_power_off = cobalt_machine_power_off;
97
98	set_io_port_base(CKSEG1ADDR(GT_DEF_PCI0_IO_BASE));
99
100	/* I/O port resource must include LCD/buttons */
101	ioport_resource.end = 0x0fffffff;
102
103	/* These resources have been reserved by VIA SuperI/O chip. */
104	for (i = 0; i < ARRAY_SIZE(cobalt_reserved_resources); i++)
105		request_resource(&ioport_resource, cobalt_reserved_resources + i);
106}
107
108/*
109 * Prom init. We read our one and only communication with the firmware.
110 * Grab the amount of installed memory.
111 * Better boot loaders (CoLo) pass a command line too :-)
112 */
113
114void __init prom_init(void)
115{
116	int narg, indx, posn, nchr;
117	unsigned long memsz;
118	char **argv;
119
120	mips_machgroup = MACH_GROUP_COBALT;
121
122	memsz = fw_arg0 & 0x7fff0000;
123	narg = fw_arg0 & 0x0000ffff;
124
125	if (narg) {
126		arcs_cmdline[0] = '\0';
127		argv = (char **) fw_arg1;
128		posn = 0;
129		for (indx = 1; indx < narg; ++indx) {
130			nchr = strlen(argv[indx]);
131			if (posn + 1 + nchr + 1 > sizeof(arcs_cmdline))
132				break;
133			if (posn)
134				arcs_cmdline[posn++] = ' ';
135			strcpy(arcs_cmdline + posn, argv[indx]);
136			posn += nchr;
137		}
138	}
139
140	add_memory_region(0x0, memsz, BOOT_MEM_RAM);
141}
142
143void __init prom_free_prom_memory(void)
144{
145	/* Nothing to do! */
146}
147