1/* 2 * bios32.c - PCI BIOS functions for m68k systems. 3 * 4 * Written by Wout Klaren. 5 * 6 * Based on the DEC Alpha bios32.c by Dave Rusling and David Mosberger. 7 */ 8 9#include <linux/init.h> 10#include <linux/kernel.h> 11 12# define DBG_DEVS(args) 13 14#ifdef CONFIG_PCI 15 16/* 17 * PCI support for Linux/m68k. Currently only the Hades is supported. 18 * 19 * The support for PCI bridges in the DEC Alpha version has 20 * been removed in this version. 21 */ 22 23#include <linux/pci.h> 24#include <linux/slab.h> 25#include <linux/mm.h> 26 27#include <asm/io.h> 28#include <asm/pci.h> 29#include <asm/uaccess.h> 30 31#define KB 1024 32#define MB (1024*KB) 33#define GB (1024*MB) 34 35#define MAJOR_REV 0 36#define MINOR_REV 5 37 38/* 39 * Align VAL to ALIGN, which must be a power of two. 40 */ 41 42#define ALIGN(val,align) (((val) + ((align) - 1)) & ~((align) - 1)) 43 44/* 45 * Offsets relative to the I/O and memory base addresses from where resources 46 * are allocated. 47 */ 48 49#define IO_ALLOC_OFFSET 0x00004000 50#define MEM_ALLOC_OFFSET 0x04000000 51 52/* 53 * Declarations of hardware specific initialisation functions. 54 */ 55 56extern struct pci_bus_info *init_hades_pci(void); 57 58/* 59 * Bus info structure of the PCI bus. A pointer to this structure is 60 * put in the sysdata member of the pci_bus structure. 61 */ 62 63static struct pci_bus_info *bus_info; 64 65static int pci_modify = 1; /* If set, layout the PCI bus ourself. */ 66static int skip_vga; /* If set do not modify base addresses 67 of vga cards.*/ 68static int disable_pci_burst; /* If set do not allow PCI bursts. */ 69 70static unsigned int io_base; 71static unsigned int mem_base; 72 73/* 74 * static void disable_dev(struct pci_dev *dev) 75 * 76 * Disable PCI device DEV so that it does not respond to I/O or memory 77 * accesses. 78 * 79 * Parameters: 80 * 81 * dev - device to disable. 82 */ 83 84static void __init disable_dev(struct pci_dev *dev) 85{ 86 unsigned short cmd; 87 88 if (((dev->class >> 8 == PCI_CLASS_NOT_DEFINED_VGA) || 89 (dev->class >> 8 == PCI_CLASS_DISPLAY_VGA) || 90 (dev->class >> 8 == PCI_CLASS_DISPLAY_XGA)) && skip_vga) 91 return; 92 93 pci_read_config_word(dev, PCI_COMMAND, &cmd); 94 95 cmd &= (~PCI_COMMAND_IO & ~PCI_COMMAND_MEMORY & ~PCI_COMMAND_MASTER); 96 pci_write_config_word(dev, PCI_COMMAND, cmd); 97} 98 99/* 100 * static void layout_dev(struct pci_dev *dev) 101 * 102 * Layout memory and I/O for a device. 103 * 104 * Parameters: 105 * 106 * device - device to layout memory and I/O for. 107 */ 108 109static void __init layout_dev(struct pci_dev *dev) 110{ 111 unsigned short cmd; 112 unsigned int base, mask, size, reg; 113 unsigned int alignto; 114 int i; 115 116 /* 117 * Skip video cards if requested. 118 */ 119 120 if (((dev->class >> 8 == PCI_CLASS_NOT_DEFINED_VGA) || 121 (dev->class >> 8 == PCI_CLASS_DISPLAY_VGA) || 122 (dev->class >> 8 == PCI_CLASS_DISPLAY_XGA)) && skip_vga) 123 return; 124 125 pci_read_config_word(dev, PCI_COMMAND, &cmd); 126 127 for (reg = PCI_BASE_ADDRESS_0, i = 0; reg <= PCI_BASE_ADDRESS_5; reg += 4, i++) 128 { 129 /* 130 * Figure out how much space and of what type this 131 * device wants. 132 */ 133 134 pci_write_config_dword(dev, reg, 0xffffffff); 135 pci_read_config_dword(dev, reg, &base); 136 137 if (!base) 138 { 139 /* this base-address register is unused */ 140 dev->resource[i].start = 0; 141 dev->resource[i].end = 0; 142 dev->resource[i].flags = 0; 143 continue; 144 } 145 146 /* 147 * We've read the base address register back after 148 * writing all ones and so now we must decode it. 149 */ 150 151 if (base & PCI_BASE_ADDRESS_SPACE_IO) 152 { 153 /* 154 * I/O space base address register. 155 */ 156 157 cmd |= PCI_COMMAND_IO; 158 159 base &= PCI_BASE_ADDRESS_IO_MASK; 160 mask = (~base << 1) | 0x1; 161 size = (mask & base) & 0xffffffff; 162 163 /* 164 * Align to multiple of size of minimum base. 165 */ 166 167 alignto = max_t(unsigned int, 0x040, size); 168 base = ALIGN(io_base, alignto); 169 io_base = base + size; 170 pci_write_config_dword(dev, reg, base | PCI_BASE_ADDRESS_SPACE_IO); 171 172 dev->resource[i].start = base; 173 dev->resource[i].end = dev->resource[i].start + size - 1; 174 dev->resource[i].flags = IORESOURCE_IO | PCI_BASE_ADDRESS_SPACE_IO; 175 176 DBG_DEVS(("layout_dev: IO address: %lX\n", base)); 177 } 178 else 179 { 180 unsigned int type; 181 182 /* 183 * Memory space base address register. 184 */ 185 186 cmd |= PCI_COMMAND_MEMORY; 187 type = base & PCI_BASE_ADDRESS_MEM_TYPE_MASK; 188 base &= PCI_BASE_ADDRESS_MEM_MASK; 189 mask = (~base << 1) | 0x1; 190 size = (mask & base) & 0xffffffff; 191 switch (type) 192 { 193 case PCI_BASE_ADDRESS_MEM_TYPE_32: 194 case PCI_BASE_ADDRESS_MEM_TYPE_64: 195 break; 196 197 case PCI_BASE_ADDRESS_MEM_TYPE_1M: 198 printk("bios32 WARNING: slot %d, function %d " 199 "requests memory below 1MB---don't " 200 "know how to do that.\n", 201 PCI_SLOT(dev->devfn), 202 PCI_FUNC(dev->devfn)); 203 continue; 204 } 205 206 /* 207 * Align to multiple of size of minimum base. 208 */ 209 210 alignto = max_t(unsigned int, 0x1000, size); 211 base = ALIGN(mem_base, alignto); 212 mem_base = base + size; 213 pci_write_config_dword(dev, reg, base); 214 215 dev->resource[i].start = base; 216 dev->resource[i].end = dev->resource[i].start + size - 1; 217 dev->resource[i].flags = IORESOURCE_MEM; 218 219 if (type == PCI_BASE_ADDRESS_MEM_TYPE_64) 220 { 221 /* 222 * 64-bit address, set the highest 32 bits 223 * to zero. 224 */ 225 226 reg += 4; 227 pci_write_config_dword(dev, reg, 0); 228 229 i++; 230 dev->resource[i].start = 0; 231 dev->resource[i].end = 0; 232 dev->resource[i].flags = 0; 233 } 234 } 235 } 236 237 /* 238 * Enable device: 239 */ 240 241 if (dev->class >> 8 == PCI_CLASS_NOT_DEFINED || 242 dev->class >> 8 == PCI_CLASS_NOT_DEFINED_VGA || 243 dev->class >> 8 == PCI_CLASS_DISPLAY_VGA || 244 dev->class >> 8 == PCI_CLASS_DISPLAY_XGA) 245 { 246 /* 247 * All of these (may) have I/O scattered all around 248 * and may not use i/o-base address registers at all. 249 * So we just have to always enable I/O to these 250 * devices. 251 */ 252 cmd |= PCI_COMMAND_IO; 253 } 254 255 pci_write_config_word(dev, PCI_COMMAND, cmd | PCI_COMMAND_MASTER); 256 257 pci_write_config_byte(dev, PCI_LATENCY_TIMER, (disable_pci_burst) ? 0 : 32); 258 259 if (bus_info != NULL) 260 bus_info->conf_device(dev); /* Machine dependent configuration. */ 261 262 DBG_DEVS(("layout_dev: bus %d slot 0x%x VID 0x%x DID 0x%x class 0x%x\n", 263 dev->bus->number, PCI_SLOT(dev->devfn), dev->vendor, dev->device, dev->class)); 264} 265 266/* 267 * static void layout_bus(struct pci_bus *bus) 268 * 269 * Layout memory and I/O for all devices on the given bus. 270 * 271 * Parameters: 272 * 273 * bus - bus. 274 */ 275 276static void __init layout_bus(struct pci_bus *bus) 277{ 278 unsigned int bio, bmem; 279 struct pci_dev *dev; 280 281 DBG_DEVS(("layout_bus: starting bus %d\n", bus->number)); 282 283 if (!bus->devices && !bus->children) 284 return; 285 286 /* 287 * Align the current bases on appropriate boundaries (4K for 288 * IO and 1MB for memory). 289 */ 290 291 bio = io_base = ALIGN(io_base, 4*KB); 292 bmem = mem_base = ALIGN(mem_base, 1*MB); 293 294 /* 295 * PCI devices might have been setup by a PCI BIOS emulation 296 * running under TOS. In these cases there is a 297 * window during which two devices may have an overlapping 298 * address range. To avoid this causing trouble, we first 299 * turn off the I/O and memory address decoders for all PCI 300 * devices. They'll be re-enabled only once all address 301 * decoders are programmed consistently. 302 */ 303 304 DBG_DEVS(("layout_bus: disable_dev for bus %d\n", bus->number)); 305 306 for (dev = bus->devices; dev; dev = dev->sibling) 307 { 308 if ((dev->class >> 16 != PCI_BASE_CLASS_BRIDGE) || 309 (dev->class >> 8 == PCI_CLASS_BRIDGE_PCMCIA)) 310 disable_dev(dev); 311 } 312 313 /* 314 * Allocate space to each device: 315 */ 316 317 DBG_DEVS(("layout_bus: starting bus %d devices\n", bus->number)); 318 319 for (dev = bus->devices; dev; dev = dev->sibling) 320 { 321 if ((dev->class >> 16 != PCI_BASE_CLASS_BRIDGE) || 322 (dev->class >> 8 == PCI_CLASS_BRIDGE_PCMCIA)) 323 layout_dev(dev); 324 } 325 326 DBG_DEVS(("layout_bus: bus %d finished\n", bus->number)); 327} 328 329/* 330 * static void pcibios_fixup(void) 331 * 332 * Layout memory and I/O of all devices on the PCI bus if 'pci_modify' is 333 * true. This might be necessary because not every m68k machine with a PCI 334 * bus has a PCI BIOS. This function should be called right after 335 * pci_scan_bus() in pcibios_init(). 336 */ 337 338static void __init pcibios_fixup(void) 339{ 340 if (pci_modify) 341 { 342 /* 343 * Set base addresses for allocation of I/O and memory space. 344 */ 345 346 io_base = bus_info->io_space.start + IO_ALLOC_OFFSET; 347 mem_base = bus_info->mem_space.start + MEM_ALLOC_OFFSET; 348 349 /* 350 * Scan the tree, allocating PCI memory and I/O space. 351 */ 352 353 layout_bus(pci_bus_b(pci_root.next)); 354 } 355 356 /* 357 * Fix interrupt assignments, etc. 358 */ 359 360 bus_info->fixup(pci_modify); 361} 362 363/* 364 * static void pcibios_claim_resources(struct pci_bus *bus) 365 * 366 * Claim all resources that are assigned to devices on the given bus. 367 * 368 * Parameters: 369 * 370 * bus - bus. 371 */ 372 373static void __init pcibios_claim_resources(struct pci_bus *bus) 374{ 375 struct pci_dev *dev; 376 int i; 377 378 while (bus) 379 { 380 for (dev = bus->devices; (dev != NULL); dev = dev->sibling) 381 { 382 for (i = 0; i < PCI_NUM_RESOURCES; i++) 383 { 384 struct resource *r = &dev->resource[i]; 385 struct resource *pr; 386 struct pci_bus_info *bus_info = (struct pci_bus_info *) dev->sysdata; 387 388 if ((r->start == 0) || (r->parent != NULL)) 389 continue; 390 if (r->flags & IORESOURCE_IO) 391 pr = &bus_info->io_space; 392 else 393 pr = &bus_info->mem_space; 394 if (request_resource(pr, r) < 0) 395 { 396 printk(KERN_ERR "PCI: Address space collision on region %d of device %s\n", i, dev->name); 397 } 398 } 399 } 400 401 if (bus->children) 402 pcibios_claim_resources(bus->children); 403 404 bus = bus->next; 405 } 406} 407 408/* 409 * int pcibios_assign_resource(struct pci_dev *dev, int i) 410 * 411 * Assign a new address to a PCI resource. 412 * 413 * Parameters: 414 * 415 * dev - device. 416 * i - resource. 417 * 418 * Result: 0 if successful. 419 */ 420 421int __init pcibios_assign_resource(struct pci_dev *dev, int i) 422{ 423 struct resource *r = &dev->resource[i]; 424 struct resource *pr = pci_find_parent_resource(dev, r); 425 unsigned long size = r->end + 1; 426 427 if (!pr) 428 return -EINVAL; 429 430 if (r->flags & IORESOURCE_IO) 431 { 432 if (size > 0x100) 433 return -EFBIG; 434 435 if (allocate_resource(pr, r, size, bus_info->io_space.start + 436 IO_ALLOC_OFFSET, bus_info->io_space.end, 1024)) 437 return -EBUSY; 438 } 439 else 440 { 441 if (allocate_resource(pr, r, size, bus_info->mem_space.start + 442 MEM_ALLOC_OFFSET, bus_info->mem_space.end, size)) 443 return -EBUSY; 444 } 445 446 if (i < 6) 447 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + 4 * i, r->start); 448 449 return 0; 450} 451 452void __init pcibios_fixup_bus(struct pci_bus *bus) 453{ 454 struct pci_dev *dev; 455 void *sysdata; 456 457 sysdata = (bus->parent) ? bus->parent->sysdata : bus->sysdata; 458 459 for (dev = bus->devices; (dev != NULL); dev = dev->sibling) 460 dev->sysdata = sysdata; 461} 462 463void __init pcibios_init(void) 464{ 465 printk("Linux/m68k PCI BIOS32 revision %x.%02x\n", MAJOR_REV, MINOR_REV); 466 467 bus_info = NULL; 468#ifdef CONFIG_HADES 469 if (MACH_IS_HADES) 470 bus_info = init_hades_pci(); 471#endif 472 if (bus_info != NULL) 473 { 474 printk("PCI: Probing PCI hardware\n"); 475 pci_scan_bus(0, bus_info->m68k_pci_ops, bus_info); 476 pcibios_fixup(); 477 pcibios_claim_resources(pci_root); 478 } 479 else 480 printk("PCI: No PCI bus detected\n"); 481} 482 483char * __init pcibios_setup(char *str) 484{ 485 if (!strcmp(str, "nomodify")) 486 { 487 pci_modify = 0; 488 return NULL; 489 } 490 else if (!strcmp(str, "skipvga")) 491 { 492 skip_vga = 1; 493 return NULL; 494 } 495 else if (!strcmp(str, "noburst")) 496 { 497 disable_pci_burst = 1; 498 return NULL; 499 } 500 501 return str; 502} 503#endif /* CONFIG_PCI */ 504