1/* 2 * cpufreq driver for Enhanced SpeedStep, as found in Intel's Pentium 3 * M (part of the Centrino chipset). 4 * 5 * Since the original Pentium M, most new Intel CPUs support Enhanced 6 * SpeedStep. 7 * 8 * Despite the "SpeedStep" in the name, this is almost entirely unlike 9 * traditional SpeedStep. 10 * 11 * Modelled on speedstep.c 12 * 13 * Copyright (C) 2003 Jeremy Fitzhardinge <jeremy@goop.org> 14 */ 15 16#include <linux/kernel.h> 17#include <linux/module.h> 18#include <linux/init.h> 19#include <linux/cpufreq.h> 20#include <linux/sched.h> /* current */ 21#include <linux/delay.h> 22#include <linux/compiler.h> 23 24#ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_ACPI 25#include <linux/acpi.h> 26#include <linux/dmi.h> 27#include <acpi/processor.h> 28#endif 29 30#include <asm/msr.h> 31#include <asm/processor.h> 32#include <asm/cpufeature.h> 33 34#define PFX "speedstep-centrino: " 35#define MAINTAINER "cpufreq@lists.linux.org.uk" 36 37#define dprintk(msg...) cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, "speedstep-centrino", msg) 38 39#define INTEL_MSR_RANGE (0xffff) 40 41struct cpu_id 42{ 43 __u8 x86; /* CPU family */ 44 __u8 x86_model; /* model */ 45 __u8 x86_mask; /* stepping */ 46}; 47 48enum { 49 CPU_BANIAS, 50 CPU_DOTHAN_A1, 51 CPU_DOTHAN_A2, 52 CPU_DOTHAN_B0, 53 CPU_MP4HT_D0, 54 CPU_MP4HT_E0, 55}; 56 57static const struct cpu_id cpu_ids[] = { 58 [CPU_BANIAS] = { 6, 9, 5 }, 59 [CPU_DOTHAN_A1] = { 6, 13, 1 }, 60 [CPU_DOTHAN_A2] = { 6, 13, 2 }, 61 [CPU_DOTHAN_B0] = { 6, 13, 6 }, 62 [CPU_MP4HT_D0] = {15, 3, 4 }, 63 [CPU_MP4HT_E0] = {15, 4, 1 }, 64}; 65#define N_IDS ARRAY_SIZE(cpu_ids) 66 67struct cpu_model 68{ 69 const struct cpu_id *cpu_id; 70 const char *model_name; 71 unsigned max_freq; /* max clock in kHz */ 72 73 struct cpufreq_frequency_table *op_points; /* clock/voltage pairs */ 74}; 75static int centrino_verify_cpu_id(const struct cpuinfo_x86 *c, const struct cpu_id *x); 76 77/* Operating points for current CPU */ 78static struct cpu_model *centrino_model[NR_CPUS]; 79static const struct cpu_id *centrino_cpu[NR_CPUS]; 80 81static struct cpufreq_driver centrino_driver; 82 83#ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_TABLE 84 85/* Computes the correct form for IA32_PERF_CTL MSR for a particular 86 frequency/voltage operating point; frequency in MHz, volts in mV. 87 This is stored as "index" in the structure. */ 88#define OP(mhz, mv) \ 89 { \ 90 .frequency = (mhz) * 1000, \ 91 .index = (((mhz)/100) << 8) | ((mv - 700) / 16) \ 92 } 93 94/* 95 * These voltage tables were derived from the Intel Pentium M 96 * datasheet, document 25261202.pdf, Table 5. I have verified they 97 * are consistent with my IBM ThinkPad X31, which has a 1.3GHz Pentium 98 * M. 99 */ 100 101/* Ultra Low Voltage Intel Pentium M processor 900MHz (Banias) */ 102static struct cpufreq_frequency_table banias_900[] = 103{ 104 OP(600, 844), 105 OP(800, 988), 106 OP(900, 1004), 107 { .frequency = CPUFREQ_TABLE_END } 108}; 109 110/* Ultra Low Voltage Intel Pentium M processor 1000MHz (Banias) */ 111static struct cpufreq_frequency_table banias_1000[] = 112{ 113 OP(600, 844), 114 OP(800, 972), 115 OP(900, 988), 116 OP(1000, 1004), 117 { .frequency = CPUFREQ_TABLE_END } 118}; 119 120/* Low Voltage Intel Pentium M processor 1.10GHz (Banias) */ 121static struct cpufreq_frequency_table banias_1100[] = 122{ 123 OP( 600, 956), 124 OP( 800, 1020), 125 OP( 900, 1100), 126 OP(1000, 1164), 127 OP(1100, 1180), 128 { .frequency = CPUFREQ_TABLE_END } 129}; 130 131 132/* Low Voltage Intel Pentium M processor 1.20GHz (Banias) */ 133static struct cpufreq_frequency_table banias_1200[] = 134{ 135 OP( 600, 956), 136 OP( 800, 1004), 137 OP( 900, 1020), 138 OP(1000, 1100), 139 OP(1100, 1164), 140 OP(1200, 1180), 141 { .frequency = CPUFREQ_TABLE_END } 142}; 143 144/* Intel Pentium M processor 1.30GHz (Banias) */ 145static struct cpufreq_frequency_table banias_1300[] = 146{ 147 OP( 600, 956), 148 OP( 800, 1260), 149 OP(1000, 1292), 150 OP(1200, 1356), 151 OP(1300, 1388), 152 { .frequency = CPUFREQ_TABLE_END } 153}; 154 155/* Intel Pentium M processor 1.40GHz (Banias) */ 156static struct cpufreq_frequency_table banias_1400[] = 157{ 158 OP( 600, 956), 159 OP( 800, 1180), 160 OP(1000, 1308), 161 OP(1200, 1436), 162 OP(1400, 1484), 163 { .frequency = CPUFREQ_TABLE_END } 164}; 165 166/* Intel Pentium M processor 1.50GHz (Banias) */ 167static struct cpufreq_frequency_table banias_1500[] = 168{ 169 OP( 600, 956), 170 OP( 800, 1116), 171 OP(1000, 1228), 172 OP(1200, 1356), 173 OP(1400, 1452), 174 OP(1500, 1484), 175 { .frequency = CPUFREQ_TABLE_END } 176}; 177 178/* Intel Pentium M processor 1.60GHz (Banias) */ 179static struct cpufreq_frequency_table banias_1600[] = 180{ 181 OP( 600, 956), 182 OP( 800, 1036), 183 OP(1000, 1164), 184 OP(1200, 1276), 185 OP(1400, 1420), 186 OP(1600, 1484), 187 { .frequency = CPUFREQ_TABLE_END } 188}; 189 190/* Intel Pentium M processor 1.70GHz (Banias) */ 191static struct cpufreq_frequency_table banias_1700[] = 192{ 193 OP( 600, 956), 194 OP( 800, 1004), 195 OP(1000, 1116), 196 OP(1200, 1228), 197 OP(1400, 1308), 198 OP(1700, 1484), 199 { .frequency = CPUFREQ_TABLE_END } 200}; 201#undef OP 202 203#define _BANIAS(cpuid, max, name) \ 204{ .cpu_id = cpuid, \ 205 .model_name = "Intel(R) Pentium(R) M processor " name "MHz", \ 206 .max_freq = (max)*1000, \ 207 .op_points = banias_##max, \ 208} 209#define BANIAS(max) _BANIAS(&cpu_ids[CPU_BANIAS], max, #max) 210 211/* CPU models, their operating frequency range, and freq/voltage 212 operating points */ 213static struct cpu_model models[] = 214{ 215 _BANIAS(&cpu_ids[CPU_BANIAS], 900, " 900"), 216 BANIAS(1000), 217 BANIAS(1100), 218 BANIAS(1200), 219 BANIAS(1300), 220 BANIAS(1400), 221 BANIAS(1500), 222 BANIAS(1600), 223 BANIAS(1700), 224 225 /* NULL model_name is a wildcard */ 226 { &cpu_ids[CPU_DOTHAN_A1], NULL, 0, NULL }, 227 { &cpu_ids[CPU_DOTHAN_A2], NULL, 0, NULL }, 228 { &cpu_ids[CPU_DOTHAN_B0], NULL, 0, NULL }, 229 { &cpu_ids[CPU_MP4HT_D0], NULL, 0, NULL }, 230 { &cpu_ids[CPU_MP4HT_E0], NULL, 0, NULL }, 231 232 { NULL, } 233}; 234#undef _BANIAS 235#undef BANIAS 236 237static int centrino_cpu_init_table(struct cpufreq_policy *policy) 238{ 239 struct cpuinfo_x86 *cpu = &cpu_data[policy->cpu]; 240 struct cpu_model *model; 241 242 for(model = models; model->cpu_id != NULL; model++) 243 if (centrino_verify_cpu_id(cpu, model->cpu_id) && 244 (model->model_name == NULL || 245 strcmp(cpu->x86_model_id, model->model_name) == 0)) 246 break; 247 248 if (model->cpu_id == NULL) { 249 /* No match at all */ 250 dprintk("no support for CPU model \"%s\": " 251 "send /proc/cpuinfo to " MAINTAINER "\n", 252 cpu->x86_model_id); 253 return -ENOENT; 254 } 255 256 if (model->op_points == NULL) { 257 /* Matched a non-match */ 258 dprintk("no table support for CPU model \"%s\"\n", 259 cpu->x86_model_id); 260#ifndef CONFIG_X86_SPEEDSTEP_CENTRINO_ACPI 261 dprintk("try compiling with CONFIG_X86_SPEEDSTEP_CENTRINO_ACPI enabled\n"); 262#endif 263 return -ENOENT; 264 } 265 266 centrino_model[policy->cpu] = model; 267 268 dprintk("found \"%s\": max frequency: %dkHz\n", 269 model->model_name, model->max_freq); 270 271 return 0; 272} 273 274#else 275static inline int centrino_cpu_init_table(struct cpufreq_policy *policy) { return -ENODEV; } 276#endif /* CONFIG_X86_SPEEDSTEP_CENTRINO_TABLE */ 277 278static int centrino_verify_cpu_id(const struct cpuinfo_x86 *c, const struct cpu_id *x) 279{ 280 if ((c->x86 == x->x86) && 281 (c->x86_model == x->x86_model) && 282 (c->x86_mask == x->x86_mask)) 283 return 1; 284 return 0; 285} 286 287/* To be called only after centrino_model is initialized */ 288static unsigned extract_clock(unsigned msr, unsigned int cpu, int failsafe) 289{ 290 int i; 291 292 /* 293 * Extract clock in kHz from PERF_CTL value 294 * for centrino, as some DSDTs are buggy. 295 * Ideally, this can be done using the acpi_data structure. 296 */ 297 if ((centrino_cpu[cpu] == &cpu_ids[CPU_BANIAS]) || 298 (centrino_cpu[cpu] == &cpu_ids[CPU_DOTHAN_A1]) || 299 (centrino_cpu[cpu] == &cpu_ids[CPU_DOTHAN_B0])) { 300 msr = (msr >> 8) & 0xff; 301 return msr * 100000; 302 } 303 304 if ((!centrino_model[cpu]) || (!centrino_model[cpu]->op_points)) 305 return 0; 306 307 msr &= 0xffff; 308 for (i=0;centrino_model[cpu]->op_points[i].frequency != CPUFREQ_TABLE_END; i++) { 309 if (msr == centrino_model[cpu]->op_points[i].index) 310 return centrino_model[cpu]->op_points[i].frequency; 311 } 312 if (failsafe) 313 return centrino_model[cpu]->op_points[i-1].frequency; 314 else 315 return 0; 316} 317 318/* Return the current CPU frequency in kHz */ 319static unsigned int get_cur_freq(unsigned int cpu) 320{ 321 unsigned l, h; 322 unsigned clock_freq; 323 cpumask_t saved_mask; 324 325 saved_mask = current->cpus_allowed; 326 set_cpus_allowed(current, cpumask_of_cpu(cpu)); 327 if (smp_processor_id() != cpu) 328 return 0; 329 330 rdmsr(MSR_IA32_PERF_STATUS, l, h); 331 clock_freq = extract_clock(l, cpu, 0); 332 333 if (unlikely(clock_freq == 0)) { 334 /* 335 * On some CPUs, we can see transient MSR values (which are 336 * not present in _PSS), while CPU is doing some automatic 337 * P-state transition (like TM2). Get the last freq set 338 * in PERF_CTL. 339 */ 340 rdmsr(MSR_IA32_PERF_CTL, l, h); 341 clock_freq = extract_clock(l, cpu, 1); 342 } 343 344 set_cpus_allowed(current, saved_mask); 345 return clock_freq; 346} 347 348 349#ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_ACPI 350 351static struct acpi_processor_performance *acpi_perf_data[NR_CPUS]; 352 353/* 354 * centrino_cpu_early_init_acpi - Do the preregistering with ACPI P-States 355 * library 356 * 357 * Before doing the actual init, we need to do _PSD related setup whenever 358 * supported by the BIOS. These are handled by this early_init routine. 359 */ 360static int centrino_cpu_early_init_acpi(void) 361{ 362 unsigned int i, j; 363 struct acpi_processor_performance *data; 364 365 for_each_possible_cpu(i) { 366 data = kzalloc(sizeof(struct acpi_processor_performance), 367 GFP_KERNEL); 368 if (!data) { 369 for_each_possible_cpu(j) { 370 kfree(acpi_perf_data[j]); 371 acpi_perf_data[j] = NULL; 372 } 373 return (-ENOMEM); 374 } 375 acpi_perf_data[i] = data; 376 } 377 378 acpi_processor_preregister_performance(acpi_perf_data); 379 return 0; 380} 381 382 383#ifdef CONFIG_SMP 384/* 385 * Some BIOSes do SW_ANY coordination internally, either set it up in hw 386 * or do it in BIOS firmware and won't inform about it to OS. If not 387 * detected, this has a side effect of making CPU run at a different speed 388 * than OS intended it to run at. Detect it and handle it cleanly. 389 */ 390static int bios_with_sw_any_bug; 391static int sw_any_bug_found(struct dmi_system_id *d) 392{ 393 bios_with_sw_any_bug = 1; 394 return 0; 395} 396 397static struct dmi_system_id sw_any_bug_dmi_table[] = { 398 { 399 .callback = sw_any_bug_found, 400 .ident = "Supermicro Server X6DLP", 401 .matches = { 402 DMI_MATCH(DMI_SYS_VENDOR, "Supermicro"), 403 DMI_MATCH(DMI_BIOS_VERSION, "080010"), 404 DMI_MATCH(DMI_PRODUCT_NAME, "X6DLP"), 405 }, 406 }, 407 { } 408}; 409#endif 410 411/* 412 * centrino_cpu_init_acpi - register with ACPI P-States library 413 * 414 * Register with the ACPI P-States library (part of drivers/acpi/processor.c) 415 * in order to determine correct frequency and voltage pairings by reading 416 * the _PSS of the ACPI DSDT or SSDT tables. 417 */ 418static int centrino_cpu_init_acpi(struct cpufreq_policy *policy) 419{ 420 unsigned long cur_freq; 421 int result = 0, i; 422 unsigned int cpu = policy->cpu; 423 struct acpi_processor_performance *p; 424 425 p = acpi_perf_data[cpu]; 426 427 /* register with ACPI core */ 428 if (acpi_processor_register_performance(p, cpu)) { 429 dprintk(PFX "obtaining ACPI data failed\n"); 430 return -EIO; 431 } 432 433 policy->shared_type = p->shared_type; 434 /* 435 * Will let policy->cpus know about dependency only when software 436 * coordination is required. 437 */ 438 if (policy->shared_type == CPUFREQ_SHARED_TYPE_ALL || 439 policy->shared_type == CPUFREQ_SHARED_TYPE_ANY) { 440 policy->cpus = p->shared_cpu_map; 441 } 442 443#ifdef CONFIG_SMP 444 dmi_check_system(sw_any_bug_dmi_table); 445 if (bios_with_sw_any_bug && cpus_weight(policy->cpus) == 1) { 446 policy->shared_type = CPUFREQ_SHARED_TYPE_ALL; 447 policy->cpus = cpu_core_map[cpu]; 448 } 449#endif 450 451 /* verify the acpi_data */ 452 if (p->state_count <= 1) { 453 dprintk("No P-States\n"); 454 result = -ENODEV; 455 goto err_unreg; 456 } 457 458 if ((p->control_register.space_id != ACPI_ADR_SPACE_FIXED_HARDWARE) || 459 (p->status_register.space_id != ACPI_ADR_SPACE_FIXED_HARDWARE)) { 460 dprintk("Invalid control/status registers (%x - %x)\n", 461 p->control_register.space_id, p->status_register.space_id); 462 result = -EIO; 463 goto err_unreg; 464 } 465 466 for (i=0; i<p->state_count; i++) { 467 if ((p->states[i].control & INTEL_MSR_RANGE) != 468 (p->states[i].status & INTEL_MSR_RANGE)) { 469 dprintk("Different MSR bits in control (%llu) and status (%llu)\n", 470 p->states[i].control, p->states[i].status); 471 result = -EINVAL; 472 goto err_unreg; 473 } 474 475 if (!p->states[i].core_frequency) { 476 dprintk("Zero core frequency for state %u\n", i); 477 result = -EINVAL; 478 goto err_unreg; 479 } 480 481 if (p->states[i].core_frequency > p->states[0].core_frequency) { 482 dprintk("P%u has larger frequency (%llu) than P0 (%llu), skipping\n", i, 483 p->states[i].core_frequency, p->states[0].core_frequency); 484 p->states[i].core_frequency = 0; 485 continue; 486 } 487 } 488 489 centrino_model[cpu] = kzalloc(sizeof(struct cpu_model), GFP_KERNEL); 490 if (!centrino_model[cpu]) { 491 result = -ENOMEM; 492 goto err_unreg; 493 } 494 495 centrino_model[cpu]->model_name=NULL; 496 centrino_model[cpu]->max_freq = p->states[0].core_frequency * 1000; 497 centrino_model[cpu]->op_points = kmalloc(sizeof(struct cpufreq_frequency_table) * 498 (p->state_count + 1), GFP_KERNEL); 499 if (!centrino_model[cpu]->op_points) { 500 result = -ENOMEM; 501 goto err_kfree; 502 } 503 504 for (i=0; i<p->state_count; i++) { 505 centrino_model[cpu]->op_points[i].index = p->states[i].control & INTEL_MSR_RANGE; 506 centrino_model[cpu]->op_points[i].frequency = p->states[i].core_frequency * 1000; 507 dprintk("adding state %i with frequency %u and control value %04x\n", 508 i, centrino_model[cpu]->op_points[i].frequency, centrino_model[cpu]->op_points[i].index); 509 } 510 centrino_model[cpu]->op_points[p->state_count].frequency = CPUFREQ_TABLE_END; 511 512 cur_freq = get_cur_freq(cpu); 513 514 for (i=0; i<p->state_count; i++) { 515 if (!p->states[i].core_frequency) { 516 dprintk("skipping state %u\n", i); 517 centrino_model[cpu]->op_points[i].frequency = CPUFREQ_ENTRY_INVALID; 518 continue; 519 } 520 521 if (extract_clock(centrino_model[cpu]->op_points[i].index, cpu, 0) != 522 (centrino_model[cpu]->op_points[i].frequency)) { 523 dprintk("Invalid encoded frequency (%u vs. %u)\n", 524 extract_clock(centrino_model[cpu]->op_points[i].index, cpu, 0), 525 centrino_model[cpu]->op_points[i].frequency); 526 result = -EINVAL; 527 goto err_kfree_all; 528 } 529 530 if (cur_freq == centrino_model[cpu]->op_points[i].frequency) 531 p->state = i; 532 } 533 534 /* notify BIOS that we exist */ 535 acpi_processor_notify_smm(THIS_MODULE); 536 printk("speedstep-centrino with X86_SPEEDSTEP_CENTRINO_ACPI " 537 "config is deprecated.\n " 538 "Use X86_ACPI_CPUFREQ (acpi-cpufreq) instead.\n" ); 539 540 return 0; 541 542 err_kfree_all: 543 kfree(centrino_model[cpu]->op_points); 544 err_kfree: 545 kfree(centrino_model[cpu]); 546 err_unreg: 547 acpi_processor_unregister_performance(p, cpu); 548 dprintk(PFX "invalid ACPI data\n"); 549 return (result); 550} 551#else 552static inline int centrino_cpu_init_acpi(struct cpufreq_policy *policy) { return -ENODEV; } 553static inline int centrino_cpu_early_init_acpi(void) { return 0; } 554#endif 555 556static int centrino_cpu_init(struct cpufreq_policy *policy) 557{ 558 struct cpuinfo_x86 *cpu = &cpu_data[policy->cpu]; 559 unsigned freq; 560 unsigned l, h; 561 int ret; 562 int i; 563 564 /* Only Intel makes Enhanced Speedstep-capable CPUs */ 565 if (cpu->x86_vendor != X86_VENDOR_INTEL || !cpu_has(cpu, X86_FEATURE_EST)) 566 return -ENODEV; 567 568 if (cpu_has(cpu, X86_FEATURE_CONSTANT_TSC)) 569 centrino_driver.flags |= CPUFREQ_CONST_LOOPS; 570 571 if (centrino_cpu_init_acpi(policy)) { 572 if (policy->cpu != 0) 573 return -ENODEV; 574 575 for (i = 0; i < N_IDS; i++) 576 if (centrino_verify_cpu_id(cpu, &cpu_ids[i])) 577 break; 578 579 if (i != N_IDS) 580 centrino_cpu[policy->cpu] = &cpu_ids[i]; 581 582 if (!centrino_cpu[policy->cpu]) { 583 dprintk("found unsupported CPU with " 584 "Enhanced SpeedStep: send /proc/cpuinfo to " 585 MAINTAINER "\n"); 586 return -ENODEV; 587 } 588 589 if (centrino_cpu_init_table(policy)) { 590 return -ENODEV; 591 } 592 } 593 594 /* Check to see if Enhanced SpeedStep is enabled, and try to 595 enable it if not. */ 596 rdmsr(MSR_IA32_MISC_ENABLE, l, h); 597 598 if (!(l & (1<<16))) { 599 l |= (1<<16); 600 dprintk("trying to enable Enhanced SpeedStep (%x)\n", l); 601 wrmsr(MSR_IA32_MISC_ENABLE, l, h); 602 603 /* check to see if it stuck */ 604 rdmsr(MSR_IA32_MISC_ENABLE, l, h); 605 if (!(l & (1<<16))) { 606 printk(KERN_INFO PFX "couldn't enable Enhanced SpeedStep\n"); 607 return -ENODEV; 608 } 609 } 610 611 freq = get_cur_freq(policy->cpu); 612 613 policy->governor = CPUFREQ_DEFAULT_GOVERNOR; 614 policy->cpuinfo.transition_latency = 10000; /* 10uS transition latency */ 615 policy->cur = freq; 616 617 dprintk("centrino_cpu_init: cur=%dkHz\n", policy->cur); 618 619 ret = cpufreq_frequency_table_cpuinfo(policy, centrino_model[policy->cpu]->op_points); 620 if (ret) 621 return (ret); 622 623 cpufreq_frequency_table_get_attr(centrino_model[policy->cpu]->op_points, policy->cpu); 624 625 return 0; 626} 627 628static int centrino_cpu_exit(struct cpufreq_policy *policy) 629{ 630 unsigned int cpu = policy->cpu; 631 632 if (!centrino_model[cpu]) 633 return -ENODEV; 634 635 cpufreq_frequency_table_put_attr(cpu); 636 637#ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_ACPI 638 if (!centrino_model[cpu]->model_name) { 639 static struct acpi_processor_performance *p; 640 641 if (acpi_perf_data[cpu]) { 642 p = acpi_perf_data[cpu]; 643 dprintk("unregistering and freeing ACPI data\n"); 644 acpi_processor_unregister_performance(p, cpu); 645 kfree(centrino_model[cpu]->op_points); 646 kfree(centrino_model[cpu]); 647 } 648 } 649#endif 650 651 centrino_model[cpu] = NULL; 652 653 return 0; 654} 655 656/** 657 * centrino_verify - verifies a new CPUFreq policy 658 * @policy: new policy 659 * 660 * Limit must be within this model's frequency range at least one 661 * border included. 662 */ 663static int centrino_verify (struct cpufreq_policy *policy) 664{ 665 return cpufreq_frequency_table_verify(policy, centrino_model[policy->cpu]->op_points); 666} 667 668/** 669 * centrino_setpolicy - set a new CPUFreq policy 670 * @policy: new policy 671 * @target_freq: the target frequency 672 * @relation: how that frequency relates to achieved frequency (CPUFREQ_RELATION_L or CPUFREQ_RELATION_H) 673 * 674 * Sets a new CPUFreq policy. 675 */ 676static int centrino_target (struct cpufreq_policy *policy, 677 unsigned int target_freq, 678 unsigned int relation) 679{ 680 unsigned int newstate = 0; 681 unsigned int msr, oldmsr = 0, h = 0, cpu = policy->cpu; 682 struct cpufreq_freqs freqs; 683 cpumask_t online_policy_cpus; 684 cpumask_t saved_mask; 685 cpumask_t set_mask; 686 cpumask_t covered_cpus; 687 int retval = 0; 688 unsigned int j, k, first_cpu, tmp; 689 690 if (unlikely(centrino_model[cpu] == NULL)) 691 return -ENODEV; 692 693 if (unlikely(cpufreq_frequency_table_target(policy, 694 centrino_model[cpu]->op_points, 695 target_freq, 696 relation, 697 &newstate))) { 698 return -EINVAL; 699 } 700 701#ifdef CONFIG_HOTPLUG_CPU 702 /* cpufreq holds the hotplug lock, so we are safe from here on */ 703 cpus_and(online_policy_cpus, cpu_online_map, policy->cpus); 704#else 705 online_policy_cpus = policy->cpus; 706#endif 707 708 saved_mask = current->cpus_allowed; 709 first_cpu = 1; 710 cpus_clear(covered_cpus); 711 for_each_cpu_mask(j, online_policy_cpus) { 712 /* 713 * Support for SMP systems. 714 * Make sure we are running on CPU that wants to change freq 715 */ 716 cpus_clear(set_mask); 717 if (policy->shared_type == CPUFREQ_SHARED_TYPE_ANY) 718 cpus_or(set_mask, set_mask, online_policy_cpus); 719 else 720 cpu_set(j, set_mask); 721 722 set_cpus_allowed(current, set_mask); 723 preempt_disable(); 724 if (unlikely(!cpu_isset(smp_processor_id(), set_mask))) { 725 dprintk("couldn't limit to CPUs in this domain\n"); 726 retval = -EAGAIN; 727 if (first_cpu) { 728 /* We haven't started the transition yet. */ 729 goto migrate_end; 730 } 731 preempt_enable(); 732 break; 733 } 734 735 msr = centrino_model[cpu]->op_points[newstate].index; 736 737 if (first_cpu) { 738 rdmsr(MSR_IA32_PERF_CTL, oldmsr, h); 739 if (msr == (oldmsr & 0xffff)) { 740 dprintk("no change needed - msr was and needs " 741 "to be %x\n", oldmsr); 742 retval = 0; 743 goto migrate_end; 744 } 745 746 freqs.old = extract_clock(oldmsr, cpu, 0); 747 freqs.new = extract_clock(msr, cpu, 0); 748 749 dprintk("target=%dkHz old=%d new=%d msr=%04x\n", 750 target_freq, freqs.old, freqs.new, msr); 751 752 for_each_cpu_mask(k, online_policy_cpus) { 753 freqs.cpu = k; 754 cpufreq_notify_transition(&freqs, 755 CPUFREQ_PRECHANGE); 756 } 757 758 first_cpu = 0; 759 /* all but 16 LSB are reserved, treat them with care */ 760 oldmsr &= ~0xffff; 761 msr &= 0xffff; 762 oldmsr |= msr; 763 } 764 765 wrmsr(MSR_IA32_PERF_CTL, oldmsr, h); 766 if (policy->shared_type == CPUFREQ_SHARED_TYPE_ANY) { 767 preempt_enable(); 768 break; 769 } 770 771 cpu_set(j, covered_cpus); 772 preempt_enable(); 773 } 774 775 for_each_cpu_mask(k, online_policy_cpus) { 776 freqs.cpu = k; 777 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); 778 } 779 780 if (unlikely(retval)) { 781 /* 782 * We have failed halfway through the frequency change. 783 * We have sent callbacks to policy->cpus and 784 * MSRs have already been written on coverd_cpus. 785 * Best effort undo.. 786 */ 787 788 if (!cpus_empty(covered_cpus)) { 789 for_each_cpu_mask(j, covered_cpus) { 790 set_cpus_allowed(current, cpumask_of_cpu(j)); 791 wrmsr(MSR_IA32_PERF_CTL, oldmsr, h); 792 } 793 } 794 795 tmp = freqs.new; 796 freqs.new = freqs.old; 797 freqs.old = tmp; 798 for_each_cpu_mask(j, online_policy_cpus) { 799 freqs.cpu = j; 800 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); 801 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); 802 } 803 } 804 set_cpus_allowed(current, saved_mask); 805 return 0; 806 807migrate_end: 808 preempt_enable(); 809 set_cpus_allowed(current, saved_mask); 810 return 0; 811} 812 813static struct freq_attr* centrino_attr[] = { 814 &cpufreq_freq_attr_scaling_available_freqs, 815 NULL, 816}; 817 818static struct cpufreq_driver centrino_driver = { 819 .name = "centrino", /* should be speedstep-centrino, 820 but there's a 16 char limit */ 821 .init = centrino_cpu_init, 822 .exit = centrino_cpu_exit, 823 .verify = centrino_verify, 824 .target = centrino_target, 825 .get = get_cur_freq, 826 .attr = centrino_attr, 827 .owner = THIS_MODULE, 828}; 829 830 831/** 832 * centrino_init - initializes the Enhanced SpeedStep CPUFreq driver 833 * 834 * Initializes the Enhanced SpeedStep support. Returns -ENODEV on 835 * unsupported devices, -ENOENT if there's no voltage table for this 836 * particular CPU model, -EINVAL on problems during initiatization, 837 * and zero on success. 838 * 839 * This is quite picky. Not only does the CPU have to advertise the 840 * "est" flag in the cpuid capability flags, we look for a specific 841 * CPU model and stepping, and we need to have the exact model name in 842 * our voltage tables. That is, be paranoid about not releasing 843 * someone's valuable magic smoke. 844 */ 845static int __init centrino_init(void) 846{ 847 struct cpuinfo_x86 *cpu = cpu_data; 848 849 if (!cpu_has(cpu, X86_FEATURE_EST)) 850 return -ENODEV; 851 852 centrino_cpu_early_init_acpi(); 853 854 return cpufreq_register_driver(¢rino_driver); 855} 856 857static void __exit centrino_exit(void) 858{ 859#ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_ACPI 860 unsigned int j; 861#endif 862 863 cpufreq_unregister_driver(¢rino_driver); 864 865#ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_ACPI 866 for_each_possible_cpu(j) { 867 kfree(acpi_perf_data[j]); 868 acpi_perf_data[j] = NULL; 869 } 870#endif 871} 872 873MODULE_AUTHOR ("Jeremy Fitzhardinge <jeremy@goop.org>"); 874MODULE_DESCRIPTION ("Enhanced SpeedStep driver for Intel Pentium M processors."); 875MODULE_LICENSE ("GPL"); 876 877late_initcall(centrino_init); 878module_exit(centrino_exit); 879