1#include <linux/init.h> 2#include <linux/bitops.h> 3#include <linux/mm.h> 4#include <asm/io.h> 5#include <asm/processor.h> 6 7#include "cpu.h" 8 9/* 10 * B step AMD K6 before B 9730xxxx have hardware bugs that can cause 11 * misexecution of code under Linux. Owners of such processors should 12 * contact AMD for precise details and a CPU swap. 13 * 14 * See http://www.multimania.com/poulot/k6bug.html 15 * http://www.amd.com/K6/k6docs/revgd.html 16 * 17 * The following test is erm.. interesting. AMD neglected to up 18 * the chip setting when fixing the bug but they also tweaked some 19 * performance at the same time.. 20 */ 21 22extern void vide(void); 23__asm__(".align 4\nvide: ret"); 24 25#define ENABLE_C1E_MASK 0x18000000 26#define CPUID_PROCESSOR_SIGNATURE 1 27#define CPUID_XFAM 0x0ff00000 28#define CPUID_XFAM_K8 0x00000000 29#define CPUID_XFAM_10H 0x00100000 30#define CPUID_XFAM_11H 0x00200000 31#define CPUID_XMOD 0x000f0000 32#define CPUID_XMOD_REV_F 0x00040000 33 34/* AMD systems with C1E don't have a working lAPIC timer. Check for that. */ 35static __cpuinit int amd_apic_timer_broken(void) 36{ 37 u32 lo, hi; 38 u32 eax = cpuid_eax(CPUID_PROCESSOR_SIGNATURE); 39 switch (eax & CPUID_XFAM) { 40 case CPUID_XFAM_K8: 41 if ((eax & CPUID_XMOD) < CPUID_XMOD_REV_F) 42 break; 43 case CPUID_XFAM_10H: 44 case CPUID_XFAM_11H: 45 rdmsr(MSR_K8_ENABLE_C1E, lo, hi); 46 if (lo & ENABLE_C1E_MASK) 47 return 1; 48 break; 49 default: 50 /* err on the side of caution */ 51 return 1; 52 } 53 return 0; 54} 55 56int force_mwait __cpuinitdata; 57 58static void __cpuinit init_amd(struct cpuinfo_x86 *c) 59{ 60 u32 l, h; 61 int mbytes = num_physpages >> (20-PAGE_SHIFT); 62 int r; 63 64#ifdef CONFIG_SMP 65 unsigned long long value; 66 67 /* Disable TLB flush filter by setting HWCR.FFDIS on K8 68 * bit 6 of msr C001_0015 69 * 70 * Errata 63 for SH-B3 steppings 71 * Errata 122 for all steppings (F+ have it disabled by default) 72 */ 73 if (c->x86 == 15) { 74 rdmsrl(MSR_K7_HWCR, value); 75 value |= 1 << 6; 76 wrmsrl(MSR_K7_HWCR, value); 77 } 78#endif 79 80 81 /* Bit 31 in normal CPUID used for nonstandard 3DNow ID; 82 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway */ 83 clear_bit(0*32+31, c->x86_capability); 84 85 r = get_model_name(c); 86 87 switch(c->x86) 88 { 89 case 4: 90#define CBAR (0xfffc) /* Configuration Base Address (32-bit) */ 91#define CBAR_ENB (0x80000000) 92#define CBAR_KEY (0X000000CB) 93 if (c->x86_model==9 || c->x86_model == 10) { 94 if (inl (CBAR) & CBAR_ENB) 95 outl (0 | CBAR_KEY, CBAR); 96 } 97 break; 98 case 5: 99 if( c->x86_model < 6 ) 100 { 101 /* Based on AMD doc 20734R - June 2000 */ 102 if ( c->x86_model == 0 ) { 103 clear_bit(X86_FEATURE_APIC, c->x86_capability); 104 set_bit(X86_FEATURE_PGE, c->x86_capability); 105 } 106 break; 107 } 108 109 if ( c->x86_model == 6 && c->x86_mask == 1 ) { 110 const int K6_BUG_LOOP = 1000000; 111 int n; 112 void (*f_vide)(void); 113 unsigned long d, d2; 114 115 printk(KERN_INFO "AMD K6 stepping B detected - "); 116 117 /* 118 * It looks like AMD fixed the 2.6.2 bug and improved indirect 119 * calls at the same time. 120 */ 121 122 n = K6_BUG_LOOP; 123 f_vide = vide; 124 rdtscl(d); 125 while (n--) 126 f_vide(); 127 rdtscl(d2); 128 d = d2-d; 129 130 if (d > 20*K6_BUG_LOOP) 131 printk("system stability may be impaired when more than 32 MB are used.\n"); 132 else 133 printk("probably OK (after B9730xxxx).\n"); 134 printk(KERN_INFO "Please see http://membres.lycos.fr/poulot/k6bug.html\n"); 135 } 136 137 /* K6 with old style WHCR */ 138 if (c->x86_model < 8 || 139 (c->x86_model== 8 && c->x86_mask < 8)) { 140 /* We can only write allocate on the low 508Mb */ 141 if(mbytes>508) 142 mbytes=508; 143 144 rdmsr(MSR_K6_WHCR, l, h); 145 if ((l&0x0000FFFF)==0) { 146 unsigned long flags; 147 l=(1<<0)|((mbytes/4)<<1); 148 local_irq_save(flags); 149 wbinvd(); 150 wrmsr(MSR_K6_WHCR, l, h); 151 local_irq_restore(flags); 152 printk(KERN_INFO "Enabling old style K6 write allocation for %d Mb\n", 153 mbytes); 154 } 155 break; 156 } 157 158 if ((c->x86_model == 8 && c->x86_mask >7) || 159 c->x86_model == 9 || c->x86_model == 13) { 160 /* The more serious chips .. */ 161 162 if(mbytes>4092) 163 mbytes=4092; 164 165 rdmsr(MSR_K6_WHCR, l, h); 166 if ((l&0xFFFF0000)==0) { 167 unsigned long flags; 168 l=((mbytes>>2)<<22)|(1<<16); 169 local_irq_save(flags); 170 wbinvd(); 171 wrmsr(MSR_K6_WHCR, l, h); 172 local_irq_restore(flags); 173 printk(KERN_INFO "Enabling new style K6 write allocation for %d Mb\n", 174 mbytes); 175 } 176 177 /* Set MTRR capability flag if appropriate */ 178 if (c->x86_model == 13 || c->x86_model == 9 || 179 (c->x86_model == 8 && c->x86_mask >= 8)) 180 set_bit(X86_FEATURE_K6_MTRR, c->x86_capability); 181 break; 182 } 183 184 if (c->x86_model == 10) { 185 /* AMD Geode LX is model 10 */ 186 /* placeholder for any needed mods */ 187 break; 188 } 189 break; 190 case 6: /* An Athlon/Duron */ 191 192 /* Bit 15 of Athlon specific MSR 15, needs to be 0 193 * to enable SSE on Palomino/Morgan/Barton CPU's. 194 * If the BIOS didn't enable it already, enable it here. 195 */ 196 if (c->x86_model >= 6 && c->x86_model <= 10) { 197 if (!cpu_has(c, X86_FEATURE_XMM)) { 198 printk(KERN_INFO "Enabling disabled K7/SSE Support.\n"); 199 rdmsr(MSR_K7_HWCR, l, h); 200 l &= ~0x00008000; 201 wrmsr(MSR_K7_HWCR, l, h); 202 set_bit(X86_FEATURE_XMM, c->x86_capability); 203 } 204 } 205 206 /* It's been determined by AMD that Athlons since model 8 stepping 1 207 * are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx 208 * As per AMD technical note 27212 0.2 209 */ 210 if ((c->x86_model == 8 && c->x86_mask>=1) || (c->x86_model > 8)) { 211 rdmsr(MSR_K7_CLK_CTL, l, h); 212 if ((l & 0xfff00000) != 0x20000000) { 213 printk ("CPU: CLK_CTL MSR was %x. Reprogramming to %x\n", l, 214 ((l & 0x000fffff)|0x20000000)); 215 wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h); 216 } 217 } 218 break; 219 } 220 221 switch (c->x86) { 222 case 15: 223 set_bit(X86_FEATURE_K8, c->x86_capability); 224 break; 225 case 6: 226 set_bit(X86_FEATURE_K7, c->x86_capability); 227 break; 228 } 229 if (c->x86 >= 6) 230 set_bit(X86_FEATURE_FXSAVE_LEAK, c->x86_capability); 231 232 display_cacheinfo(c); 233 234 if (cpuid_eax(0x80000000) >= 0x80000008) { 235 c->x86_max_cores = (cpuid_ecx(0x80000008) & 0xff) + 1; 236 } 237 238 if (cpuid_eax(0x80000000) >= 0x80000007) { 239 c->x86_power = cpuid_edx(0x80000007); 240 if (c->x86_power & (1<<8)) 241 set_bit(X86_FEATURE_CONSTANT_TSC, c->x86_capability); 242 } 243 244#ifdef CONFIG_X86_HT 245 /* 246 * On a AMD multi core setup the lower bits of the APIC id 247 * distingush the cores. 248 */ 249 if (c->x86_max_cores > 1) { 250 int cpu = smp_processor_id(); 251 unsigned bits = (cpuid_ecx(0x80000008) >> 12) & 0xf; 252 253 if (bits == 0) { 254 while ((1 << bits) < c->x86_max_cores) 255 bits++; 256 } 257 c->cpu_core_id = c->phys_proc_id & ((1<<bits)-1); 258 c->phys_proc_id >>= bits; 259 printk(KERN_INFO "CPU %d(%d) -> Core %d\n", 260 cpu, c->x86_max_cores, c->cpu_core_id); 261 } 262#endif 263 264 if (cpuid_eax(0x80000000) >= 0x80000006) 265 num_cache_leaves = 3; 266 267 if (amd_apic_timer_broken()) 268 set_bit(X86_FEATURE_LAPIC_TIMER_BROKEN, c->x86_capability); 269 270 if (c->x86 == 0x10 && !force_mwait) 271 clear_bit(X86_FEATURE_MWAIT, c->x86_capability); 272 273 /* K6s reports MCEs but don't actually have all the MSRs */ 274 if (c->x86 < 6) 275 clear_bit(X86_FEATURE_MCE, c->x86_capability); 276} 277 278static unsigned int __cpuinit amd_size_cache(struct cpuinfo_x86 * c, unsigned int size) 279{ 280 /* AMD errata T13 (order #21922) */ 281 if ((c->x86 == 6)) { 282 if (c->x86_model == 3 && c->x86_mask == 0) /* Duron Rev A0 */ 283 size = 64; 284 if (c->x86_model == 4 && 285 (c->x86_mask==0 || c->x86_mask==1)) /* Tbird rev A1/A2 */ 286 size = 256; 287 } 288 return size; 289} 290 291static struct cpu_dev amd_cpu_dev __cpuinitdata = { 292 .c_vendor = "AMD", 293 .c_ident = { "AuthenticAMD" }, 294 .c_models = { 295 { .vendor = X86_VENDOR_AMD, .family = 4, .model_names = 296 { 297 [3] = "486 DX/2", 298 [7] = "486 DX/2-WB", 299 [8] = "486 DX/4", 300 [9] = "486 DX/4-WB", 301 [14] = "Am5x86-WT", 302 [15] = "Am5x86-WB" 303 } 304 }, 305 }, 306 .c_init = init_amd, 307 .c_size_cache = amd_size_cache, 308}; 309 310int __init amd_init_cpu(void) 311{ 312 cpu_devs[X86_VENDOR_AMD] = &amd_cpu_dev; 313 return 0; 314} 315