1/* 2 * arch/cris/arch-v32/drivers/nandflash.c 3 * 4 * Copyright (c) 2004 5 * 6 * Derived from drivers/mtd/nand/spia.c 7 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com) 8 * 9 * $Id: nandflash.c,v 1.1.1.1 2007/08/03 18:51:41 Exp $ 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License version 2 as 13 * published by the Free Software Foundation. 14 * 15 */ 16 17#include <linux/slab.h> 18#include <linux/init.h> 19#include <linux/module.h> 20#include <linux/mtd/mtd.h> 21#include <linux/mtd/nand.h> 22#include <linux/mtd/partitions.h> 23#include <asm/arch/memmap.h> 24#include <asm/arch/hwregs/reg_map.h> 25#include <asm/arch/hwregs/reg_rdwr.h> 26#include <asm/arch/hwregs/gio_defs.h> 27#include <asm/arch/hwregs/bif_core_defs.h> 28#include <asm/io.h> 29 30#define CE_BIT 4 31#define CLE_BIT 5 32#define ALE_BIT 6 33#define BY_BIT 7 34 35static struct mtd_info *crisv32_mtd = NULL; 36/* 37 * hardware specific access to control-lines 38*/ 39static void crisv32_hwcontrol(struct mtd_info *mtd, int cmd) 40{ 41 unsigned long flags; 42 reg_gio_rw_pa_dout dout = REG_RD(gio, regi_gio, rw_pa_dout); 43 44 local_irq_save(flags); 45 switch(cmd){ 46 case NAND_CTL_SETCLE: 47 dout.data |= (1<<CLE_BIT); 48 break; 49 case NAND_CTL_CLRCLE: 50 dout.data &= ~(1<<CLE_BIT); 51 break; 52 case NAND_CTL_SETALE: 53 dout.data |= (1<<ALE_BIT); 54 break; 55 case NAND_CTL_CLRALE: 56 dout.data &= ~(1<<ALE_BIT); 57 break; 58 case NAND_CTL_SETNCE: 59 dout.data |= (1<<CE_BIT); 60 break; 61 case NAND_CTL_CLRNCE: 62 dout.data &= ~(1<<CE_BIT); 63 break; 64 } 65 REG_WR(gio, regi_gio, rw_pa_dout, dout); 66 local_irq_restore(flags); 67} 68 69/* 70* read device ready pin 71*/ 72int crisv32_device_ready(struct mtd_info *mtd) 73{ 74 reg_gio_r_pa_din din = REG_RD(gio, regi_gio, r_pa_din); 75 return ((din.data & (1 << BY_BIT)) >> BY_BIT); 76} 77 78/* 79 * Main initialization routine 80 */ 81struct mtd_info* __init crisv32_nand_flash_probe (void) 82{ 83 void __iomem *read_cs; 84 void __iomem *write_cs; 85 86 reg_bif_core_rw_grp3_cfg bif_cfg = REG_RD(bif_core, regi_bif_core, rw_grp3_cfg); 87 reg_gio_rw_pa_oe pa_oe = REG_RD(gio, regi_gio, rw_pa_oe); 88 struct nand_chip *this; 89 int err = 0; 90 91 /* Allocate memory for MTD device structure and private data */ 92 crisv32_mtd = kmalloc (sizeof(struct mtd_info) + sizeof (struct nand_chip), 93 GFP_KERNEL); 94 if (!crisv32_mtd) { 95 printk ("Unable to allocate CRISv32 NAND MTD device structure.\n"); 96 err = -ENOMEM; 97 return NULL; 98 } 99 100 read_cs = ioremap(MEM_CSP0_START | MEM_NON_CACHEABLE, 8192); 101 write_cs = ioremap(MEM_CSP1_START | MEM_NON_CACHEABLE, 8192); 102 103 if (!read_cs || !write_cs) { 104 printk("CRISv32 NAND ioremap failed\n"); 105 err = -EIO; 106 goto out_mtd; 107 } 108 109 /* Get pointer to private data */ 110 this = (struct nand_chip *) (&crisv32_mtd[1]); 111 112 pa_oe.oe |= 1 << CE_BIT; 113 pa_oe.oe |= 1 << ALE_BIT; 114 pa_oe.oe |= 1 << CLE_BIT; 115 pa_oe.oe &= ~ (1 << BY_BIT); 116 REG_WR(gio, regi_gio, rw_pa_oe, pa_oe); 117 118 bif_cfg.gated_csp0 = regk_bif_core_rd; 119 bif_cfg.gated_csp1 = regk_bif_core_wr; 120 REG_WR(bif_core, regi_bif_core, rw_grp3_cfg, bif_cfg); 121 122 /* Initialize structures */ 123 memset((char *) crisv32_mtd, 0, sizeof(struct mtd_info)); 124 memset((char *) this, 0, sizeof(struct nand_chip)); 125 126 /* Link the private data with the MTD structure */ 127 crisv32_mtd->priv = this; 128 129 /* Set address of NAND IO lines */ 130 this->IO_ADDR_R = read_cs; 131 this->IO_ADDR_W = write_cs; 132 this->hwcontrol = crisv32_hwcontrol; 133 this->dev_ready = crisv32_device_ready; 134 /* 20 us command delay time */ 135 this->chip_delay = 20; 136 this->eccmode = NAND_ECC_SOFT; 137 138 /* Enable the following for a flash based bad block table */ 139 this->options = NAND_USE_FLASH_BBT; 140 141 /* Scan to find existance of the device */ 142 if (nand_scan (crisv32_mtd, 1)) { 143 err = -ENXIO; 144 goto out_ior; 145 } 146 147 return crisv32_mtd; 148 149out_ior: 150 iounmap((void *)read_cs); 151 iounmap((void *)write_cs); 152out_mtd: 153 kfree (crisv32_mtd); 154 return NULL; 155} 156