1/* 2 * Register definitions for SM 3 * 4 * System Manager 5 */ 6#ifndef __ASM_AVR32_SM_H__ 7#define __ASM_AVR32_SM_H__ 8 9/* SM register offsets */ 10#define SM_PM_MCCTRL 0x0000 11#define SM_PM_CKSEL 0x0004 12#define SM_PM_CPU_MASK 0x0008 13#define SM_PM_HSB_MASK 0x000c 14#define SM_PM_PBA_MASK 0x0010 15#define SM_PM_PBB_MASK 0x0014 16#define SM_PM_PLL0 0x0020 17#define SM_PM_PLL1 0x0024 18#define SM_PM_VCTRL 0x0030 19#define SM_PM_VMREF 0x0034 20#define SM_PM_VMV 0x0038 21#define SM_PM_IER 0x0040 22#define SM_PM_IDR 0x0044 23#define SM_PM_IMR 0x0048 24#define SM_PM_ISR 0x004c 25#define SM_PM_ICR 0x0050 26#define SM_PM_GCCTRL 0x0060 27#define SM_RTC_CTRL 0x0080 28#define SM_RTC_VAL 0x0084 29#define SM_RTC_TOP 0x0088 30#define SM_RTC_IER 0x0090 31#define SM_RTC_IDR 0x0094 32#define SM_RTC_IMR 0x0098 33#define SM_RTC_ISR 0x009c 34#define SM_RTC_ICR 0x00a0 35#define SM_WDT_CTRL 0x00b0 36#define SM_WDT_CLR 0x00b4 37#define SM_WDT_EXT 0x00b8 38#define SM_RC_RCAUSE 0x00c0 39#define SM_EIM_IER 0x0100 40#define SM_EIM_IDR 0x0104 41#define SM_EIM_IMR 0x0108 42#define SM_EIM_ISR 0x010c 43#define SM_EIM_ICR 0x0110 44#define SM_EIM_MODE 0x0114 45#define SM_EIM_EDGE 0x0118 46#define SM_EIM_LEVEL 0x011c 47#define SM_EIM_TEST 0x0120 48#define SM_EIM_NMIC 0x0124 49 50/* Bitfields in PM_MCCTRL */ 51 52/* Bitfields in PM_CKSEL */ 53#define SM_CPUSEL_OFFSET 0 54#define SM_CPUSEL_SIZE 3 55#define SM_CPUDIV_OFFSET 7 56#define SM_CPUDIV_SIZE 1 57#define SM_HSBSEL_OFFSET 8 58#define SM_HSBSEL_SIZE 3 59#define SM_HSBDIV_OFFSET 15 60#define SM_HSBDIV_SIZE 1 61#define SM_PBASEL_OFFSET 16 62#define SM_PBASEL_SIZE 3 63#define SM_PBADIV_OFFSET 23 64#define SM_PBADIV_SIZE 1 65#define SM_PBBSEL_OFFSET 24 66#define SM_PBBSEL_SIZE 3 67#define SM_PBBDIV_OFFSET 31 68#define SM_PBBDIV_SIZE 1 69 70/* Bitfields in PM_CPU_MASK */ 71 72/* Bitfields in PM_HSB_MASK */ 73 74/* Bitfields in PM_PBA_MASK */ 75 76/* Bitfields in PM_PBB_MASK */ 77 78/* Bitfields in PM_PLL0 */ 79#define SM_PLLEN_OFFSET 0 80#define SM_PLLEN_SIZE 1 81#define SM_PLLOSC_OFFSET 1 82#define SM_PLLOSC_SIZE 1 83#define SM_PLLOPT_OFFSET 2 84#define SM_PLLOPT_SIZE 3 85#define SM_PLLDIV_OFFSET 8 86#define SM_PLLDIV_SIZE 8 87#define SM_PLLMUL_OFFSET 16 88#define SM_PLLMUL_SIZE 8 89#define SM_PLLCOUNT_OFFSET 24 90#define SM_PLLCOUNT_SIZE 6 91#define SM_PLLTEST_OFFSET 31 92#define SM_PLLTEST_SIZE 1 93 94/* Bitfields in PM_PLL1 */ 95 96/* Bitfields in PM_VCTRL */ 97#define SM_VAUTO_OFFSET 0 98#define SM_VAUTO_SIZE 1 99#define SM_PM_VCTRL_VAL_OFFSET 8 100#define SM_PM_VCTRL_VAL_SIZE 7 101 102/* Bitfields in PM_VMREF */ 103#define SM_REFSEL_OFFSET 0 104#define SM_REFSEL_SIZE 4 105 106/* Bitfields in PM_VMV */ 107#define SM_PM_VMV_VAL_OFFSET 0 108#define SM_PM_VMV_VAL_SIZE 8 109 110/* Bitfields in PM_IER */ 111 112/* Bitfields in PM_IDR */ 113 114/* Bitfields in PM_IMR */ 115 116/* Bitfields in PM_ISR */ 117 118/* Bitfields in PM_ICR */ 119#define SM_LOCK0_OFFSET 0 120#define SM_LOCK0_SIZE 1 121#define SM_LOCK1_OFFSET 1 122#define SM_LOCK1_SIZE 1 123#define SM_WAKE_OFFSET 2 124#define SM_WAKE_SIZE 1 125#define SM_VOK_OFFSET 3 126#define SM_VOK_SIZE 1 127#define SM_VMRDY_OFFSET 4 128#define SM_VMRDY_SIZE 1 129#define SM_CKRDY_OFFSET 5 130#define SM_CKRDY_SIZE 1 131 132/* Bitfields in PM_GCCTRL */ 133#define SM_OSCSEL_OFFSET 0 134#define SM_OSCSEL_SIZE 1 135#define SM_PLLSEL_OFFSET 1 136#define SM_PLLSEL_SIZE 1 137#define SM_CEN_OFFSET 2 138#define SM_CEN_SIZE 1 139#define SM_CPC_OFFSET 3 140#define SM_CPC_SIZE 1 141#define SM_DIVEN_OFFSET 4 142#define SM_DIVEN_SIZE 1 143#define SM_DIV_OFFSET 8 144#define SM_DIV_SIZE 8 145 146/* Bitfields in RTC_CTRL */ 147#define SM_PCLR_OFFSET 1 148#define SM_PCLR_SIZE 1 149#define SM_TOPEN_OFFSET 2 150#define SM_TOPEN_SIZE 1 151#define SM_CLKEN_OFFSET 3 152#define SM_CLKEN_SIZE 1 153#define SM_PSEL_OFFSET 8 154#define SM_PSEL_SIZE 16 155 156/* Bitfields in RTC_VAL */ 157#define SM_RTC_VAL_VAL_OFFSET 0 158#define SM_RTC_VAL_VAL_SIZE 31 159 160/* Bitfields in RTC_TOP */ 161#define SM_RTC_TOP_VAL_OFFSET 0 162#define SM_RTC_TOP_VAL_SIZE 32 163 164/* Bitfields in RTC_IER */ 165 166/* Bitfields in RTC_IDR */ 167 168/* Bitfields in RTC_IMR */ 169 170/* Bitfields in RTC_ISR */ 171 172/* Bitfields in RTC_ICR */ 173#define SM_TOPI_OFFSET 0 174#define SM_TOPI_SIZE 1 175 176/* Bitfields in WDT_CTRL */ 177#define SM_KEY_OFFSET 24 178#define SM_KEY_SIZE 8 179 180/* Bitfields in WDT_CLR */ 181 182/* Bitfields in WDT_EXT */ 183 184/* Bitfields in RC_RCAUSE */ 185#define SM_POR_OFFSET 0 186#define SM_POR_SIZE 1 187#define SM_BOD_OFFSET 1 188#define SM_BOD_SIZE 1 189#define SM_EXT_OFFSET 2 190#define SM_EXT_SIZE 1 191#define SM_WDT_OFFSET 3 192#define SM_WDT_SIZE 1 193#define SM_NTAE_OFFSET 4 194#define SM_NTAE_SIZE 1 195#define SM_SERP_OFFSET 5 196#define SM_SERP_SIZE 1 197 198/* Bitfields in EIM_IER */ 199 200/* Bitfields in EIM_IDR */ 201 202/* Bitfields in EIM_IMR */ 203 204/* Bitfields in EIM_ISR */ 205 206/* Bitfields in EIM_ICR */ 207 208/* Bitfields in EIM_MODE */ 209 210/* Bitfields in EIM_EDGE */ 211#define SM_INT0_OFFSET 0 212#define SM_INT0_SIZE 1 213#define SM_INT1_OFFSET 1 214#define SM_INT1_SIZE 1 215#define SM_INT2_OFFSET 2 216#define SM_INT2_SIZE 1 217#define SM_INT3_OFFSET 3 218#define SM_INT3_SIZE 1 219 220/* Bitfields in EIM_LEVEL */ 221 222/* Bitfields in EIM_TEST */ 223#define SM_TESTEN_OFFSET 31 224#define SM_TESTEN_SIZE 1 225 226/* Bitfields in EIM_NMIC */ 227#define SM_EN_OFFSET 0 228#define SM_EN_SIZE 1 229 230/* Bit manipulation macros */ 231#define SM_BIT(name) (1 << SM_##name##_OFFSET) 232#define SM_BF(name,value) (((value) & ((1 << SM_##name##_SIZE) - 1)) << SM_##name##_OFFSET) 233#define SM_BFEXT(name,value) (((value) >> SM_##name##_OFFSET) & ((1 << SM_##name##_SIZE) - 1)) 234#define SM_BFINS(name,value,old) (((old) & ~(((1 << SM_##name##_SIZE) - 1) << SM_##name##_OFFSET)) | SM_BF(name,value)) 235 236/* Register access macros */ 237#define sm_readl(port,reg) \ 238 __raw_readl((port)->regs + SM_##reg) 239#define sm_writel(port,reg,value) \ 240 __raw_writel((value), (port)->regs + SM_##reg) 241 242#endif /* __ASM_AVR32_SM_H__ */ 243